JP2527741B2 - Light control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a plurality of lighting devices such as a stage lighting device for a theater or a lighting device for a wedding reception hall, in which the brightness and color of the lighting lights are changed according to each scene. The present invention relates to a light control device that can be suitably implemented so that a scene can be created and rendered.

BACKGROUND ART FIG. 4 is a block diagram showing a typical prior art electrical configuration. The dimmer 1 includes, for example, three stages of preset fader trains pf1, pf2, pf3 and stage master faders pm1, pm2, pm3 for controlling outputs p1, p2, p3 of the respective stages.

For example pre-excisional Hue over da column pf1 the first stage has a pre excisional Hue over da _{F 11, F 12 ... F 1} n corresponding to n channels ch1~ channel chn described below, these n pre The outputs of the set faders F _{11 to} F ₁ n are selected by the multiplexer 2. The second and third stage preset fader trains pf2 and pf3 are also constructed in the same manner as the first stage preset fader train pf1, and are respectively set by multiplexers 3 and 4. Output is selected.

The operation of these three multiplexers 2, 3 and 4 is defined by the channel control unit 5, and each multiplexer
The outputs p1, p2, p3 selected by 2, 3, 4 are commonly input to the multiplication circuits 6, 7, 8 as outputs of the respective stages. Three
The outputs of the one-stage master faders pf1 to pf3 are also given to the three multiplying circuits 6, 7, and 8, respectively. In these three multiplication circuits 6, 7 and 8, each output is multiplied and
Sample and hold circuit 9 via two diodes D1 to D3
Commonly given to.

The three diodes D1 to D3 are the highest level selection circuits.
Make up 10. That is, by providing the highest level selection circuit 10, only the output having the highest level among the multiplication circuits 6, 7 and 8 is given to the sample hold circuit 9. The sample and hold circuit 9 sequentially outputs the output signal selected by the highest level selection circuit 10 to n preset channels ch1 to chn.
The sample and hold circuit 9 is controlled by the channel control unit 5 and has three multiplexers.
The same channel as that selected by 2, 3 and 4 is selected.

FIG. 5 is a graph for explaining the operation of the light control device 1. In this case, the two-stage preset fader row pf
Description will be given assuming that only 1, pf2 is used.

For example, the output p1 of the first stage is 30%, the output of the second stage is
When p2 is set to 60%, fix the stage master fader pm1 to 100% and set the stage master fader pm2 to 0.
The output when changing from 100% to 100% is shown in (2) of the same figure.

The level l1 of the output P6 of the multiplication circuit 6 is maintained at the level (30%) of the output p1 of the first stage because the stage master fader pm1 is fixed at 100%. On the other hand, the level l2 of the output p7 of the multiplication circuit 7 is 0% for the stage master fader pm2.
From 0% to 100%, there is a linear change from 0% to the level (60%) of the output p2 of the second stage. Therefore, at the output of the highest level selection circuit 10, the level l3 shown by the solid line in FIG.

Next, when the levels of the outputs p1 and p2 of the first stage and the second stage are respectively set to 100%, the stage master fader pm2 is changed from 0% to 100%, and the stage master fader pm1 is changed to 100%.
The output when cross-fading is performed by simultaneously changing from 0% to 0% is shown in FIG. In this case, the level 14 of the output p6 of the multiplication circuit 6 linearly changes from 100% to 0%, and the level 15 of the output p7 of the multiplication circuit 7 changes from 0% to 100%. Therefore, the highest level detection circuit 1
At the output of 0, the level 16 shown by the solid line in FIG. 1A is obtained.

When the crossfading is performed in the dimmer 1 in this way, the output level drops to the center around the point X1 where the two levels l4 and l5 intersect. This is because the highest level selection circuit 10 selects and outputs the highest level. In the cross fade with such a drop phenomenon, a smooth scene change cannot be performed, and a desired effect cannot be obtained. Therefore, a method of removing the highest level selection circuit 10 and adding the outputs of the multiplication circuits 6 to 8 can be considered. According to this method, the output level under the setting condition of (1) in FIG.
A level 17 is obtained, which is indicated by the chain double-dashed line. Therefore, this method allows for smooth crossfades.

On the other hand, if such a simple addition method is applied under the setting condition of FIG. 2B, the level 18 shown in FIG. 3C is obtained as the actual output level. That is, if the highest level is prioritized under the same setting condition (2) in FIG.
The level 13 shown in (3) is obtained, and by adding the outputs, the level 18 shown in (3) of the figure is obtained.

For example, when it is desired to set a scene at which a 60% level is output and a scene at which a 30% level is output at the same time, the director may want to set the actual output level to 60%. With the addition method, 90% in such situations
The level is output, and the director cannot set the desired scene.

It is an object of the present invention to provide a light control device capable of eliminating a middle drop phenomenon occurring in the process of performing crossfading and realizing a smooth crossfading.

Embodiment FIG. 1 is a block diagram showing the electrical construction of an embodiment of the present invention. The dimming device 21 of the present embodiment is basically a first level setting means of three stages of preset fader rows.
It includes PF1, PF2, PF3, and stage master faders PM1, PM2, PM3 which are second level setting means for controlling them.

The preset fader train PF1 is composed of n preset faders P ₁₁ , P ₁₂ , P ₁₃ ... P ₁ n, and the outputs of these n preset faders are sequentially selected by the multiplexer 31. It Pre excisional Hue over da column PF2, PF3 likewise each n pre excisional Hue over da _{P 21, P 23, ... P} 2 n; P 31, P
₃₂ , P ₃₃ ... P ₃ n, each of which has a multiplexer 32,
The output of each preset fader is sequentially selected by 33. These three multiplexers 31 to 33 selectively control the preset faders corresponding to the same channel by the channel control unit 30.

The respective stage outputs P1, P2, P3 selected and set by the three multiplexers 31, 32, 33 are input to the non-inverting input terminals of the comparators 23, 24, 25, respectively. These three comparators 23, 24, 25
The second-stage, first-stage, and third-stage outputs P2, P1, and P3 are input to the respective inverting input terminals of. By this, the comparator 2
Comparison signals X, Y and Z indicating the magnitude relations of the output levels of the outputs P3 and P2; the output P2 and the output P1; the output P1 and the output P3 are obtained at the outputs of 3, 24 and 25. These comparison signals
X, Y and Z are commonly given to the master control unit 26.

The levels set by the three-stage master faders PM1, PM2, PM3 are commonly given to the adder 27 and added in common. The output added by the adder 27 is given to the inverting input terminal of the comparator 28. A 100% detection level is applied to the non-inverting input terminal of the comparator 28. Therefore, whether the total sum of the levels set in the three-stage master faders PM1 to PM3 is 100% or more can be identified by the output D of the comparator 28. (Hereinafter, when the sum of the levels set in the three-stage master faders PM1 to PM3 is 100% or more, it is referred to as a first control state, and 100
When it is less than%, it is called the second control state. ) The output D of the comparator 28 is given to the stage master controller 26.

The master controller 26, based on the comparison signals X, Y, Z output from the three comparators 23 to 25 and the output D of the comparator 28, includes eight multiplexers 34, 35, 36, 37, which will be described later. 38,3
It controls the operation of 9,40,41 respectively. That is, in the master control unit 26, the output having the maximum level, the output having the second level, and the minimum level among the outputs P1, P2, and P3 based on the three comparison signals X, Y, and Z are output. (Hereinafter referred to as maximum output Pa, intermediate output Pb, and minimum output Pc, respectively) are discriminated, and the stage corresponding to each of these outputs is identified. Further, the output D of the comparator 28 identifies whether the three stage master faders PM1 to PM3 are in the first control state or the second control state.

The outputs P1 to P3 of the respective stages are commonly supplied to three multiplexers 37, 38, 39, respectively. Multiplexer 37-39
Then, the maximum output identified by the master control unit 26
Pa is selected and given to the multiplication circuit 51. Similarly, in the multiplexers 38 and 39, the intermediate output Pb and the minimum output Pc are selected, and the multiplication circuits 5 and 5 are selected.
Given to 2,53.

Further, the output levels of the three stage master faders PM1 to PM3 are commonly given to the multiplexers 34, 35 and 36 which are selection means. In the multiplexer 34, the maximum output
The output of the stage master fader (hereinafter referred to as the output PMa) corresponding to the stage where Pa is output is selected and given to the multiplication circuit 51. Similarly, in the multiplexers 35 and 36, the outputs of the stage master faders (hereinafter referred to as the intermediate output PMb and the minimum output PMc, respectively) corresponding to the stages to which the intermediate output Pb and the minimum output Pc are respectively output are selected. The outputs PMb and PMc are given to the multiplexers 40 and 41, respectively.

The output PMa selected by the multiplexer 34 is given to the multiplication circuit 51 and the adder 43. The output of the adder 43 is given to the multiplication circuit 44 together with the output PMb of the multiplexer 35, and the multiplication circuit 44
The output PMb _{1 of} is supplied to the multiplexer 40 and is also supplied to the multiplexer 41 via the adder 45.
The operations of the two adders 43 and 45 and the multiplication circuit 44 will be described later.

The multiplexer 40 selectively outputs the output PMb ₁ of the multiplication circuit 44 and the output PMb of the multiplexer 35, and supplies this to the multiplication circuit 52. That is, the master control unit
When the first control state is identified at 26, the output PMb of the multiplexer 35 is selected as the output of the multiplexer 40 (hereinafter referred to as the output PMB). On the other hand, when the second control state is identified, the output PMb _{1 of the} multiplication circuit 44 is selected. Similarly, for the output of the multiplexer 41 (hereinafter referred to as output PMC), when the first control state is identified, the output PMc of the multiplexer 36 is selected, and when the second control state is identified, The output PMc ₁ of the adder 45 is selected and given to the multiplication circuit 53.

The outputs K1, K2, and K3 of these three multiplication circuits 51 to 53 are added by the adder 54 and given to the sample hold circuit 55. The sample hold circuit 55 is the channel control unit.
Controlled by 30. That is, in the sample hold circuit 55, the channel control section 30 selectively outputs the output S of the adder 54 to the channels corresponding to the channels set by the three multiplexers 31 to 33.

Although the dimmer 21 of the present embodiment is provided with three stages of preset fader rows, the present invention is not limited to this, and more rows may be used.

FIG. 2 is a flow chart for explaining the operation of the light control device 21. The operation of the light control device 21 will be described below with reference to FIGS. 1 and 2.

In step n1, the stage having the maximum output Pa is identified based on the comparison signals X, Y, Z, whereby the maximum outputs PMa, P in the multiplexers 34, 37, respectively.
a is selectively output.

In step n2, the stage with the intermediate output Pb is identified in the same way, on the basis of which the multiplexers 35, 38
At, intermediate outputs PMb and Pb are selectively output.

In step n3, the stage having the minimum output Pc is identified, and based on this, the minimum outputs PMc, Pc are selectively output at the multiplexers 36, 39.

The maximum output P based on the three comparison signals X, Y, Z
a, the logic for selecting the intermediate output Pb and the minimum output Pc,
The results are shown in Table 1 below.

In step n4, the three-stage master fader PM1
It is determined whether or not the total sum of the levels set to PM3 is less than 100%. If less than 100%, the process proceeds to step n6, and if it exceeds 100%, the process proceeds to step n5.

In step n5, the two multiplexers 4
The two multiplexers 35 and 36 are connected to the outputs PMB and PMC of 0 and 41, respectively.
Outputs PMb and PMc of are selected.

In step n6, two multiplexers 40,41
Each output PMB, the output PMc ₁ output PMb ₁ and the adder 45 of the multiplication circuit 44 to the PMC are selected respectively.

Here, the output PMb ₁ of the multiplication circuit 44 and the output PM of the adder 45
c ₁ will be described. In the adder 43, arithmetic processing is performed so that the output PMa of the multiplexer 34 becomes (1-PMa). In the multiplication circuit 44, the output (1
-PMa) and the output PMb of the multiplexer 35 are multiplied, and this becomes the output PMb _{1 of the} multiplication circuit 44. That is, the level shown in the following first equation is obtained at this output PMb ₁ .

PMb ₁ = PMb × (1-PMa) (1) In the adder 45, the output PMc ₁ is subjected to arithmetic processing as shown by the following second equation.

PMc ₁ = 1- (PMb ₁ + PMa) (2) The processing in and after step n5 and step n6 proceeds to step n7. In step n7, the multiplexers 40 and 41 set in step n5 or step n6 are set.
Output PMB, PMC of each and the output PMa of the multiplexer 34,
The multiplication circuits 51, 52 and 53 perform arithmetic processing on the outputs Pa, Pb and Pc of the three multiplexers 37, 38 and 39. Therefore, the output S of the adder 54, to which the outputs K1 to K3 of the multiplication circuits 51 to 53 are added, has the level shown in the following third equation.

S = PMa × Pa + PMB × Pb + PMC × Pc (3) For reference, the three-stage master fader PM1
~ Adder 54 when PM3 is set to the first control state
And the output level of the output S2 of the adder 54 when it is set to the second control state are shown in the following fourth and fifth equations.

S1 = PMa × Pa + PMb × Pb + PMc × Pc (4) S2 = PMa × Pa + PMb ₁ × Pb × PMc ₁ × Pc (5) FIG. 3 is a graph for explaining an operation example of the dimmer 21. . As the operating condition of (1) in the figure, both the output P1 of the first stage and the output P2 of the second stage are set to 100%, the stage master fader PM1 is changed from 100% to 0%, and the stage master fader PM2 is set. Suppose that changes from 0% to 100% at the same time. Outputs Pa, Pb, Pc of multiplexers 37-39 and output PM of multiplexers 34-36
It is assumed that outputs as shown in the following sixth to eleventh equations are selected for a, PMb, and PMc.

Pa = P1 (6) Pb = P2 (7) Pc = P3 (= 0) (8) PMa = PM1 (9) PMb = PM2 (10) PMc = PM3 (= 0) (11) In such a case, even if the stage master faders PM1 and PM2 are changed as described above, the total sum is always 10
Since it is set to 0%, in the master control unit 26, the first
The control state is identified. Therefore, multiplexer 40
Output PMB of the multiplexer 35 output PMb (= PM2)
Is selected, and the output K2 of the multiplication circuit 52 is expressed by the following twelfth expression.

K2 = P2 × PM2 (12) (PM2; 0% → 100%) On the other hand, the output K1 of the multiplication circuit 51 is given by the following thirteenth expression.

K1 = P1 × PM1 (13) (PM1; 100% → 0%) In this way, the output K1 changes from 100% to 10%,
The output K2 changes from 0% to 100%.

As a result, the output level of the adder 54 is always 100%.
Is held. Therefore, when such cross-fading is performed, it is possible to eliminate the phenomenon of center drop described in the section of the prior art.

Next, as the operating condition of (2) in the figure, the output P1 of the first stage is set to 30%, the output P2 of the second stage is set to 60%, and the stage master fader PM1 is set to 100%. It is assumed that the master fader PM2 is fixed and changed from 0% to 100%. The outputs Pa, Pb, Pc of the multiplexers 37 to 39 and the outputs PMa, PMb, PMc of the multiplexers 34 to 36 are
It is assumed that the output shown in the following Equations 14 to 19 is selected.

Pa = P2 (14) Pb = P1 (15) Pc = P3 (= 0) (16) PMa = PM2 (17) PMb = PM1 (18) PMc = PM3 (= 0) (19) In this case, as the output K1 of the multiplication circuit 51, the level shown in the following Expression 20 is obtained.

K1 = P2 × PM2 (20) (PM2; 0% → 100%) That is, this output K1 changes from 0% to 60%.
Further, under the operation condition of (2) in the figure, since the second control state is identified by the master control unit 26, the multiplexer 40
The output PMb ₁ of the multiplication circuit 44 is selected as the output PMB of. Therefore, at the output K2 of the multiplication circuit 52, the level shown in the following Expression 21 is obtained.

K2 = P1 × PM1 (1-PM2) (21) (PM1; 100%, PM2; 0% → 100%) Therefore, the output K2 changes from 30% to 0%, and the output of the adder 54 S2 is as shown by the solid line in (2) of the figure.
It varies linearly from 30% to 60%.

It should be noted here that the output K2 of the multiplication circuit 52 is reduced from 30% to 0% by changing the stage master fader PM2 from 0% to 100% with the stage master fader PM1 fixed at 100%. That is. That is, under this operating condition, the second control state is detected by the master control unit 26, so that the output PMb of the multiplexer 35 is converted into the output PMb1 through the arithmetic processing. As a result, even if the stage master fader PM2 is changed to 100%, the output level of the output K2 of the multiplication circuit becomes 0%, so the final output S2 is 60%.
Maintained at%.

In other words, if you want to play a scene that outputs 60% level and a scene that outputs 30% level at the same time,
Finally, the 60% level is set, so that it is possible to obtain a desired effect. As described above, in this embodiment, in the cross fade relating to the next scene to be set next from the current scene that is currently set, no matter what level is set in the stage corresponding to the current scene and the next scene, The crossfades can be performed, and the effect of the effect can be remarkably improved.

Effect As described above, according to the present invention, it is possible to eliminate the phenomenon of a middle drop in which the illumination level drops in the process of performing crossfading, and it is possible to realize a smooth crossfade, and the staging effect is significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the electrical configuration of a light control device 21 which is an embodiment of the present invention, FIG. 2 is a flow chart for explaining the operation of the light control device 21, and FIG. 3 is a light control device. FIG. 4 is a graph for explaining an operation example of FIG. 21, FIG. 4 is a block diagram showing an electrical configuration of a typical conventional light control device 1, and FIG.
The figure is a graph for explaining the prior art. 21 …… dimming device, 23, 24, 25, 28 …… comparator, 26 …… master controller, 27, 45, 54 …… adder, 31 to 41 …… multiplexer, 44, 51, 52, 53 ...... Multiply circuit, PM1 to PM3 …… Stage master fader, PF1, PF2, PF3 …… Preset fader row

Claims (1)

(57) [Claims] 1. A plurality of stages of first level setting means for individually responding to a lighting load and setting a dimming level of the lighting load, and a dimming level of the lighting load as the first level setting means. A dimming device that continuously changes within a level set to, and includes second level setting means provided corresponding to each of the stages, each of which is set in the first level setting means. The level discriminating means for discriminating the magnitude relation between the levels and the second level setting means corresponding to the respective stages in the descending order of the stage outputs Pa, Pb, Pc, ..., Pn which are assumed based on the level discriminating process. Selection means for selecting the outputs PMa, PMb, PMc, ..., PMn, and outputs PMa, PMb, PMc, ..., PMn from the selection means and the outputs of the respective stages
When performing a calculation process with Pa, Pb, Pc, ..., Pn to obtain a dimming control signal, when the sum of the outputs PMa, PMb, PMc, ..., PMn is within a predetermined range, The level S of the light control signal is [However, A dimmer that is characterized by performing a calculation process of the type represented by.