JP2528998B2 - Scan converter control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Outline Industrial Application Field of the Invention Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Working Example Example Effect of the Invention [Summary] Regarding the control circuit of the scan converter that rearranges the matrix data and changes the clock at the input / output terminal of the arithmetic unit, the purpose is to enable high-speed real-time processing of image data using dedicated hardware. , A plurality of memories used for writing data and reading data alternately according to a given switching signal,
Scan converter including a write address counter that outputs a write address and outputs a write completion signal according to a predetermined count value, and a read address counter that outputs a read address and outputs a read completion signal according to a predetermined count value In the control circuit of, the data input control means for activating the count operation of the write address counter in response to the data input signal requesting the data capture and controlling the stop of the count operation in response to the write completion signal, and the write completion signal Accordingly, the logical value of the switching signal is inverted and the memory switching control means for switching the surface of the memory and the count operation of the read address counter are activated in response to the write completion signal, and the count operation of the count operation is performed in response to the read completion signal. Data output control for stop control Make up and a stage.

[Industrial applications]

The present invention relates to a scan converter control circuit for rearranging matrix data and changing input / output data clocks and operation clocks at input / output terminals of an arithmetic unit for performing high-speed matrix operation.

[Conventional technology]

In digital transmission of an image signal having a wide frequency band, band compression encoding is performed to reduce the bit rate (band compression) by utilizing the correlation in the spatial axis and time axis directions.

By the way, since an image signal has a characteristic that power is concentrated in a low frequency component, band compression is performed by an orthogonal transform coding method (for example, discrete cosine transform (DCT)) capable of separating image data into frequency components. Has been done.

In this DCT conversion, the input data X, a predetermined square matrix C according to the conversion method, and the output data Y when the transposed matrix C ^t thereof can be obtained by the calculation process of Y = CXC ^t .

In order to perform this arithmetic processing at high speed by dedicated hardware, the matrix data of the input and output of the arithmetic unit (for example, image data of 8 × 8 blocks) is rearranged, the data input / output clock and the arithmetic clock. I have to change trains.

FIG. 8 is a block diagram showing a DCT encoding circuit composed of a scan converter and an arithmetic unit for performing the processes of and.

In the figure, the input image data is sent to the computing unit 82 via the scan converter 81. In the calculator 82,
Predetermined arithmetic processing is performed using the coefficient data provided from the memory 83, and the output data is transmitted via the scan converter 84.

Here, the scan converters 81 and 84 are each configured by a two-sided memory in which writing and reading are alternately performed, and a control unit (software) that controls surface switching and controls a write address and a read address of the corresponding memory. It had been. The operation of the scan converter will be described below with reference to FIG.

FIG. 9A shows the timing of surface switching and writing / reading switching. 64 data is input to one RAM of the two-sided memory according to the data input signal XDIN,
Writing is performed according to the writing order shown in FIG. 9B, that is, the input order by the "vertical scan" (DT-IN).
Upon completion of the writing, the reading is performed according to the reading order shown in FIG. 9C, that is, the output order by the "zigzag scan" (DT-OUT). On the other hand, 64 data is input to the other RAM of the two-sided memory in response to the next data input signal XDIN, the same writing is performed, and then the reading is performed.

As described above, the scan converter includes the two-sided memory and alternately switches between writing and reading,
Further, by controlling the scanning direction at the time of writing and reading, it is possible to rearrange the data to be continuously input.

[Problems to be Solved by the Invention]

By the way, writing to each memory constituting the scan converter is alternately switched according to the data input signal XDIN. Further, reading is performed after the end of the data writing. As described above, the surface switching processing is performed independently for each memory of the two-sided memory, but in the past, this processing was controlled by software (program). Further, such software requires a certain number of program steps, and there is a limit to the reduction of the effective required time.

Therefore, it has not been possible to obtain a processing speed that can deal with continuous real-time processing of image data.

It is an object of the present invention to provide a scan converter control circuit that controls a scan converter using dedicated hardware and enables high-speed real-time processing of image data.

[Means for solving the problem]

 FIG. 1 is a block diagram of the principle of the present invention.

In the figure, a plurality of memories 11 ₁ and 11 ₂ are alternately used for data writing and data reading according to a switching signal applied.

The write address counter 12 outputs a write address and outputs a write completion signal according to a predetermined count value.

The read address counter 13 outputs a read address and outputs a read completion signal according to a predetermined count value.

The data input control means 14 activates the count operation of the write address counter 12 in response to a data input signal requesting data capture, and controls the stop of the count operation in response to a write completion signal.

The memory switching control means 15 inverts the logical value of the switching signal in response to the write completion signal, and the memories 11 ₁ , 1
1 Switch the surface of ₂ .

The data output control means 16 activates the count operation of the read address counter 13 according to the write completion signal, and controls the stop of the count operation according to the read completion signal.

[Work]

According to the present invention, the data input control means 14 activates the count operation of the write address counter 12 in response to the data input signal, and the write address counter 12 is selected according to the switching signal provided from the memory switching control means 15. A write address is given to one of 11 ₁ and 11 ₂ , and a data input operation is performed.

Further, in response to the write completion signal, the data input control means 14 stops the counting operation of the write address counter 12, and the memory switching control means 15 inverts the logical value of the switching signal to switch the surfaces of the memories 11 ₁ and 11 ₂ . I do.

The data output control means 16 activates the counting operation of the read address counter 13 in response to the write completion signal, and the read address counter 13 responds to the switching signal provided from the memory switching control means 15 with the data fetched. A read address is given to the memory in which is stored, and a data output operation is performed.

The data output control means 16 responds to the read completion signal by
The operation of the read address counter 13 is stopped.

Therefore, by using dedicated hardware, the memories 11 ₁ , 1 corresponding to the state transition of the scan converter in response to the data input signal, the write completion signal, and the read completion signal.
It is possible to realize a control circuit of the scan converter that performs the surface switching control of 1 ₂ .

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a diagram showing a configuration of an embodiment of the scan converter.

In the figure, the scan converter comprises a control circuit 20 according to the present invention and the following circuits controlled by its output.

The input data DT-IN is given to each data input of the RAMs 22 ₁ and 22 ₂ via the D-type flip-flop 21. RAM22 ₁ , 2
Each output of 2 ₂ is connected to a multiplexer (MUL) 24 via registers (REG) 23 ₁ , 23 ₂ , respectively, and output data DT-OUT is sent from the output. A RAM switching signal (hereinafter, referred to as “switching signal”) CHNG is given to selectors (SEL) 25 ₁ and 25 ₂ , and its logical value “0”,
Select the corresponding input terminal signal according to "1" and RA
It is sent to the address pin ADR of M22 ₁ and 22 ₂ . Selector 25 ₁
The terminal 0 of the write address WADR, the read address in the read address RADR, terminal 0 of the selector 25 ₂ to the terminal 1 R
A write address WADR is connected to the ADR and the terminal 1. The write enable control signal WTE is the clock signal M
R via OR gate 26 which takes the logical sum with CLK, and OR gate 27 ₁ which takes the logical sum with switching signal CHNG
AM22 with given _1, switching signal C of the opposite logical value
It is given to the RAM 22 ₂ via the OR gate 27 ₂ which takes the logical sum with the HNG (XWE). That is, the write enable control signal WTE obtained via the OR gate 26 is the switching signal C
The write enable signal XWE is given to only one of the RAMs 22 ₁ and 22 ₂ according to HNG. Switching signal CHNG
Is a multiplexer 24 via a D flip-flop 28.
And the corresponding input terminal signals (output data of RAM 22 ₁ and RAM 22 ₂ ) are selected according to the logical values “0” and “1”. The clock signal MCLK is a D-type flip-flop 2
₁ , 28 and registers 23 ₁ , 23 ₂ .

3 and 4 are block diagrams showing the configuration of the control circuit 20 according to the embodiment. Note that FIG. 3 corresponds to the data input control means and the memory switching control means, and FIG. 4 corresponds to the data output control means. Further, the read address RADR, the write address WADR, the write enable control signal WTE, and the switching signal CHNG are given from the control circuit 20.

In FIG. 3, the data input signal XDIN is sent to the write address counter (WAC) 3 via the D-type flip-flop 31.
It is given to the load terminal LD of 2 and the inverter 33, 3
Write address counter control circuit composed of 4 ₁ , 34 ₂ , AND gates 35 ₁ , 35 ₂ and JK flip-flop 36
Given to 37. Write address count enable signal XW output from the write address counter control circuit 37
ACEN is applied to the count enable terminal EN of the write address counter 32 and also the D-type flip-flop 38.
Is output as a write enable control signal WTE. Further, in the write address counter 32, all bits of its parallel input terminal are fixedly set to low level, and the parallel output terminal is connected to one input of the comparator 39 and is also shown in FIG. Selector 2 shown
5,25 is connected ₂ to (write address WADR). The write address counter 32 is previously provided to the other input of the comparator 39.
The bit pattern corresponding to the count value (= 3E (hexadecimal number)) for detecting the end of counting is fixedly set, and its output is provided with the write completion signal WE, and is also composed of an OR gate 41 and D-type flip-flops 42 and 43. The memory switching control circuit 44 and the write address counter control circuit 37 are connected to the other inputs.

In the write address counter control circuit 37, one output is set to high level only when both the applied data input signal XDIN and the write completion signal WE are low level, and the other output is set to high level only when both are high level. The logic circuit to be constituted by inverters 33, 34 ₁ , 34 ₂ and AND gates 35 ₁ , 35 ₂ receives each output.
The write address count enable signal XWACEN is output from the inverted output of the JK flip-flop 36 (corresponding to the other output described above).

In the memory switching control circuit 44, one input connected to the output of the comparator 39 is connected to an OR gate 41 that takes the logical sum of the clock signal MCLK, and its output is the clock of the D-type flip-flop 42 forming a T-type flip-flop. It is connected to a terminal C, and its output terminal Q is output as a switching signal CHNG via a D-type flip-flop 43.

The write address counter 32, the D-type flip-flops 31, 38, 43, the JK flip-flop 36 and the register
The clock signal MCLK is given to 40, and the reset terminals of the JK flip-flop 36 and the D-type flip-flop 42 and the preset terminals of the D-type flip-flop 38,
The reset signal XRST is given.

In FIG. 4, the write completion signal WE is given to the load terminal LD of the read address counter (RAC) 45, and the inverters 46, 47 ₁ , 47 ₂ and AND gates 48 ₁ , 48 _{2 are also provided.}
And a read address counter control circuit 50 including a JK flip-flop 49. The read address count enable signal XRACEN output from the read address counter control circuit 50 is the read address counter 45.
It is given to the count enable pin EN of. Further, in the read address counter 45, all bits of the parallel input terminal are fixedly set to low level, the parallel output terminal is connected to one input of the comparator 51, and the selectors 25 ₁ and 25 are connected via the register 52. Connected to ₂ (read address RADR). A bit pattern corresponding to the count value (= 3E) for detecting the count end of the read address counter 45 is fixedly set in advance to the other input of the comparator 51, and its output gives the read completion signal RE and the read address counter control. Connected to the other input of circuit 50.

The read address counter control circuit 50 sets one output to a high level only when both the write completion signal WE and the read completion signal RE that are applied are at a low level, and the other output is at a high level only when both are at a high level. The logic circuit to be configured by inverters 46, 47 ₁ , 47 ₂ and AND gates 48 ₁ , 48 ₂ receives each output.
The read address count enable signal XRACEN is output from the inverted output of the JK flip-flop 49 (corresponding to the other output described above).

A clock signal MCLK is applied to the read address counter 45, the JK flip-flop 49 and the register 52, and a reset signal XRST is applied to the reset terminal of the JK flip-flop 49.

In the scan converter configured as described above, the data input signal XD
The RAM 22 ₁ , 2 outputs an IN signal, a write completion signal WE, a read completion signal RE, and a control signal according to the state of the scan converter at the timing when these signals are given.
2 _2, controls the operation of the write address counter 32 and read address counter 45.

 FIG. 5 is a state transition diagram of the scan converter.

In the figure, the states (1) to (8) that can be taken by the scan converter transit in the direction of the arrow indicated by the solid line. Further, each state is represented by four parameters showing the operation mode of the RAM 22 ₁ , the operation mode of the RAM 22 ₂ , the state of the write address counter 32, and the state of the read address counter 45, which are shown in order from the left in FIG. . RAM22 ₁ ,
The 22 _second operation mode, "W" indicates the capture mode of the data, "R" indicates a read mode data. Regarding the states of the write address counter 32 and the read address counter 45, "C" indicates that counting is in progress, and "φ" indicates that they are stopped or all of their bits are set to "0".

Also, on the arrow indicating that it will stop in the same state,
"W /" and the symbol attached thereto indicate the operating state of the write address counter 32, and "R /" and the symbol attached thereto indicate the operating state of the read address counter 45. Further, the symbol "CU" added here indicates a state in which counting up is possible, and "DI" indicates an operation prohibited state. The symbols shown on the arrow (“WE”, “RE”,
"XDIN") indicates the condition under which the corresponding state transition occurs,
A plurality of symbols shown together indicate the case where the corresponding conditions are given at the same time.

Further, ~, '~' indicate the flow of state transitions indicated by dotted arrows.

FIG. 6 is an operation timing chart of the scan converter corresponding to the state transition diagram.

As shown in FIG. 6 (a), FIG. 5 shows the state transition until the data input signal XDIN is applied and the output of the captured data is completed in the state where the data capturing operation and the output operation are not performed. Shows the flow of.

The control circuit 20 controls as follows.

When the reset signal XRST is given, the memory switching control circuit 44 outputs the low level switching signal XCHNG,
The RAM 22 ₁ is selected as the data fetch memory and the RAM 22 ₂ is selected as the data read memory by the selectors 25 ₁ and 25 ₂ , the OR gates 27 ₁ and 27 ₂ and the multiplexer 24 (FIG. 5 (1)).

When the data input signal XDIN is applied in this state, the write address counter control circuit 37 outputs a low level write address count enable signal XWACEN. Further, the write address counter 32 outputs all the write addresses WADR in synchronization with the clock signal MCLK by setting all the bits to the low level by the data input signal XDIN given to the load terminal LD. Also, D-type flip-flop
38 outputs a low-level write enable control signal WTE, the RAM 22 ₁ is supplied with the write enable signal XWE via the OR gate 27 ₁ , and the input data DT-IN is sequentially written to the RAM 22 ₁ (see FIG. )).

The comparator 39 outputs the write completion signal WE when the output of the write address counter 32 becomes “3E (hexadecimal number)”. The write address counter control circuit 37 returns the write address count enable signal WACEN to the high level in response to this signal.
32 stops counting operation after reaching the final count value. Further, the memory switching control circuit 44 inverts the switching signal CHNG in response to the supplied write completion signal WE, and uses the RAM 22 ₂ as a memory to be used for the next write operation.
And the output of the RAM 22 ₁ is connected to the output end of the scan converter via the multiplexer 24 (5th
Figure (3)).

On the other hand, the read address counter control circuit 50 outputs a low level read address count enable signal XRACEN in response to the applied write completion signal WE. In response to this signal, the read address counter 45 has all its bits reset, and outputs the read address RADR in synchronization with the clock signal MCLK. This read address RADR
R via selector 25 ₁ when the switching signal CHNG is specified
Given AM22 _1, the data read from the RAM 22 ₁ is output through the multiplexer 24. Comparator 51
Outputs the read completion signal RE when the output of the read address counter 45 becomes “3E (hexadecimal number)”. The read address counter control circuit 50 returns the read address count enable signal RACEN to the high level in response to this signal, so that the read address counter 45 stops the counting operation after reaching the final count value (FIG. 5). (4)).

FIG. 5 shows a state transition flow when the next data input signal XDIN is applied during the output operation of the fetched data as shown in FIG. 6 (b).

The control circuit 20 controls as follows.

Even during reading of the data written in the RAM 22 _1,
RAM 22 ₂ by the data input signal XDIN is given in the previous state (FIG. 5 (3)) the write operation of data is started, the write address counter 32, under control of the write address counter control circuit 37, Write address WA
The DR is output, the D-type flip-flop 38 outputs the low-level write enable control signal WTE, and the RAM 22 ₂ is supplied with the write enable signal XWE via the OR gate 27 ₂ . Therefore, the input data DT-IN is sequentially written to the RAM 22 ₂ in parallel with the data output operation on the RAM 22 ₁ (FIG. 5 (7)).

When the count value of the read address counter 45 becomes “3E (hexadecimal number)”, the comparator 51 outputs the read completion signal RE.
The read address counter 45 outputs, under the control of the read address counter control circuit 50 according to this signal,
The counting operation is stopped ((5) in FIG. 5).

When the count value of the write address counter 32 becomes “3E (hexadecimal)”, the comparator 39 outputs the write completion signal WE.
The write address counter 32 outputs, under the control of the write address counter control circuit 37 according to this signal,
Stop counting operation. The memory switching control circuit 44 also switches the switching signal CHNG in response to the write completion signal WE.
And the RAM 22 ₁ is selected as a memory to be used for the next write operation, and the output of the RAM 22 ₂ is connected to the output end of the scan converter via the multiplexer 24 (FIG. 5 (6)).

As shown in FIG. 6 (c), FIG. 5 shows the data input signal XD
The flow of state transition when ING is given is shown.

The control circuit 20 controls as follows.

Data written in RAM 22 ₁ is already read, RAM 2
In the state where data is written in 2 ₂ ((5) in Fig. 5), write completion signal WE and data input signal XDIN
Are simultaneously given, the write address counter control circuit 37 holds the write address count enable signal WACEN at the low level, and the write address counter 32 continues the output operation of the write address WADR. Further, the D-type flip-flop 38 outputs the low level write enable control signal WTE, and the RAM 22 ₁ receives the write enable signal X.
WE is given. Therefore, the input data DT-IN is sequentially written to the RAM 22 ₁ in parallel with the output operation of the data on the RAM 22 ₂ . The read address counter 45 outputs the read address RADR under the control of the read address counter control circuit 50 in response to the write completion signal WE. This read address RADR is specified by the switching signal CHNG.
Given RAM 22 _2, data read from the RAM 22 ₂ is output through a multiplexer 24 (FIG. 5 (8)).

Next, read completion signal RE and write completion signal
When WE is given at the same time, the write address counter control circuit 37 causes the write address count enable signal WACEN.
Is returned to the high level, the write address counter 32 is stopped, and the read address counter control circuit 50 holds the read address count enable signal RACEN at the low level, so that the read address counter continues the output operation of the read address. . Further, the memory switching control circuit 44 inverts the switching signal CHNG in response to the write completion signal WE, the RAM 22 ₂ is selected for the next write operation, and the output of the RAM 22 ₁ is output by the multiplexer 24.
It is connected to the output terminal of the scan converter via (FIG. 5 (3)).

FIG. 5 shows a state transition flow when the next data input signal XDIN is applied at the time point when the data capturing operation and the data output operation are simultaneously completed, as shown in FIG. 6 (d).

The control circuit 20 controls as follows.

When the data input signal XDIN, the write completion signal WE, and the read completion signal RE are given simultaneously, the write address counter control circuit 37 and the read address counter control circuit 50 output their respective output signals (write address count enable signal WACEN, read address count enable signal). The memory switching control circuit 44 inverts the switching signal CHNG according to the write completion signal WE. Therefore, the RAMs 22 ₁ and 22 ₂ are alternately used to perform the data fetching operation and the data reading operation in parallel (FIGS. 5 (7) and (8)).

In addition, "~" shown in FIG.
Same as ~ except that the side of the RAM used for reading is different.

FIG. 7 is a timing chart showing an example of the operation of this embodiment.

In the figure, the states (3), (5), (7), and (8) of the scan converter at each timing are the states (3), (5), (7), and (7) shown in FIG. 5, respectively.
It matches (8).

As described above, in the present embodiment, the dedicated hardware can perform the independent switching processing for each memory with respect to the two-sided memory used for writing and reading data, and the control for controlling the scan converter at high speed. A circuit can be realized.

In this embodiment, by operating the write address counter 32 and the read address counter 45 with different clock signals, the clock signal transfer processing can be performed via the RAMs 22 ₁ and 22 ₂ .

〔The invention's effect〕

As described above, according to the present invention, a control circuit capable of controlling the scan converter at high speed can be realized by using dedicated hardware.

Therefore, high-speed real-time processing of continuous image data becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of a scan converter, FIG. 3 is a diagram showing the configuration of an embodiment of data input control means and memory switching control means, and FIG. FIG. 5 is a diagram showing an embodiment configuration of the data output control means, FIG. 5 is a state transition diagram of the scan converter, FIG. 6 is an operation timing chart of the scan converter corresponding to the state transition diagram, and FIG. 7 is an operation diagram of this embodiment. 8 is a timing chart showing an example, FIG. 8 is a block diagram showing a DCT encoding circuit, and FIG. 9 is a diagram explaining the operation of the scan converter. In the figure, 11 ₁ and 11 ₂ are memories, 12 is a write address counter, 13 is a read address counter, 14 is a data input control means, 15 is a memory switching control means, 16 is a data output control means, 20 is a control circuit, 21 , 28, 31, 38, 42, 43 are D-type flip-flops, 22 ₁ , 22 ₂ are RAM (RAM), 23 ₁ , 23 ₂ , 40, 52 are registers (REG), 24 is a multiplexer (MUL), 25 ₁ , 25 ₂ is a selector (SEL), 26, 27 ₁ , 27 ₂ , 41 is an OR gate, 32 is a write address counter (WAC), 33, 34 ₁ , 34 ₂ , 46, 47 ₁ , 47 ₂ is an inverter, 35 ₁ , 35 ₂ , 48 ₁ , and 48 ₂ are AND gates, 36 and 49 are JK flip-flops, 37 is a write address counter control circuit, 39 and 51 are comparators (CMP), 44 is a memory switching control circuit, and 45 is a read address. Counter (RAC), 50 is read address counter control circuit, 81, 8 4 is a scan converter, 82 is a computing unit, and 83 is a memory.

Claims (1)

(57) [Claims] 1. A plurality of memories (11 ₁ , 11 ₂ ) used for data writing and data reading alternately according to a given switching signal and a write address, and a write completion signal according to a predetermined count value. Write address counter (12)
And a read address counter that outputs a read address and a read completion signal according to a predetermined count value (13)
In the control circuit of the scan converter including and, the count operation of the write address counter (12) is activated in response to the data input signal requesting data capture, and the stop operation of the count operation is controlled in response to the write completion signal. A data input control means (14) for performing, and a memory switching control means (15) for inverting the logical value of the switching signal in accordance with the write completion signal and performing surface switching of the memory (11 ₁ , 11 ₂ ). A data output control means (16) for starting the count operation of the read address counter (13) in response to the write completion signal and for controlling the stop of the count operation in response to the read completion signal. Characteristic scan converter control circuit.