JP2529328B2 - Video special playback device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video special playback device for performing still image playback or trick play such as strobe using a field memory in a video device such as a VTR or a video disc.

2. Description of the Related Art In a video device such as a VTR or a video disc, when performing still image reproduction or special reproduction such as strobe, a memory for one field is usually used from the viewpoint of memory capacity. However, the television signal has a 4-field sequence configuration in which the phase of the color burst signal makes one cycle in 4 fields, and the phase of the color burst signal becomes discontinuous if the memory for 1 field is simply read. Reproducibility becomes poor. Also, regarding the sync signal, the television signal has a configuration in which the position of the vertical sync signal is different in the half horizontal scanning period between the even field and the odd field due to interlacing.
If the memory for one field is simply read out, the position of the vertical synchronizing signal is fixed to either the even field or the odd field, and the interlacing does not occur. Further, one field of the television signal has a 262.5 horizontal scanning period, and if the read address of the memory is returned to the start address for each field, the position of the horizontal synchronizing signal shifts by 1/2 horizontal scanning period. Therefore, when performing special reproduction using the memory for one field, it is necessary to pay attention to the continuity of the vertical synchronizing signal, the horizontal synchronizing signal, and the color burst signal.

As such a special reproduction apparatus for video in consideration of continuity of the vertical synchronization signal, the horizontal synchronization signal and the color burst signal, for example, "special reproduction system for constant linear velocity (CLV) disk" (1986, Television National conference)
A method such as shown in 1 is conventionally known.

FIG. 5 is a block diagram showing the configuration of a conventional video special playback device. This conventional video special playback device does not write the vertical synchronizing signal and the horizontal synchronizing signal in the memory, but adds the vertical synchronizing signal and the horizontal synchronizing signal in synchronization with the reference synchronizing signal after reading them. , Maintain the continuity of vertical and horizontal sync signals. For color burst signals,
A delay circuit that can invert the phase of the color burst signal (about 140ns) after reading from the memory and a circuit that detects discontinuity of the color burst signal are provided. This is a method of maintaining continuity of the color burst signal by switching between a signal that does not pass through the circuit and a signal that passes through the delay circuit.

The operation of the conventional video special playback device will be described below with reference to FIG.

In FIG. 5, 501 is an A / D converter that converts an analog video signal into a digital signal, (A / D) 502 is a memory that can store the video signal, such as a RAM, 50
3 is a D / A that converts a digital video signal into an analog signal
A converter (D / A), 504 is a write clock generation circuit for generating a write clock in synchronization with an input video signal, 505 is a write address control circuit for controlling the write address of the memory 2, and 506 is A read address control circuit for controlling the read address of the memory 2 and a read clock generation circuit 507 for generating a read clock synchronized with the reference synchronization signal. Further, 510 is a video signal input terminal, 520 is a video signal output terminal, 530 is a sync signal separation circuit, 540 is a sync signal insertion circuit, 550 is a reference sync signal generation circuit for generating a sync signal as a reference, 560 is a delay circuit that delays the video signal by an amount (about 140 ns) that the phase of the color burst signal is inverted, 570 is a color burst signal discontinuity detection circuit for detecting discontinuity of the color burst signal, and 580 is a selector. is there.

The operation of the conventional video special playback device configured as described above will be described below.

First, the video signal input from the input terminal 510 of the device is A
It is input to the / D converter (A / D) 501 and is also sent to the sync signal separation circuit 530, where the horizontal sync signal and the vertical sync signal are separated. The analog video signal input to the A / D converter (A / D) 501 is converted into a digital video signal here and sent to the memory 502. On the other hand, in the write clock generation circuit 504, the write clock is generated in synchronization with the horizontal sync signal separated by the sync signal separation circuit 530. The write address control circuit 505 controls the write address of the memory 502 in synchronization with the horizontal sync signal and the vertical sync signal separated by the sync signal separation circuit 530. At this time, the write address control circuit 505 controls the memory 502 during the period of the horizontal synchronizing signal and the vertical synchronizing signal.
The write address of is fixed.
Therefore, video signals other than the horizontal synchronizing signal and the vertical synchronizing signal are written in the memory 502. The contents written in the memory 502 are shown in FIG. It shows one horizontal scanning period of a video signal (video signal), and shows what is written in the memory 2 for one field of video signal (playback screen).

On the other hand, in the reference synchronization signal generation circuit 550, a horizontal synchronization signal and a vertical synchronization signal, which serve as a reference when the memory 502 is read, are generated and input to the synchronization signal insertion circuit 540 and the read clock generation circuit 507. The read clock generation circuit 507 generates a stable read clock synchronized with the reference horizontal sync signal generated by the reference sync signal generation circuit 550. Read address control circuit 506
Then, the read address of the memory 502 is controlled in synchronization with the reference horizontal synchronizing signal and the vertical synchronizing signal generated by the reference synchronizing signal generation circuit 550. Therefore, the video signal is read from the memory 502 in synchronization with the synchronization signal generated by the reference synchronization signal generation circuit 550, and the D / A converter (D / A) 50
Sent to 3. The D / A converter (D / A) 503 converts the digital video signal read from the memory 502 into an analog video signal and outputs it. Furthermore, the synchronization signal insertion circuit 40
Then, the reference horizontal synchronizing signal and the vertical synchronizing signal generated by the reference synchronizing signal generating circuit 550 are converted to the D / A converter (D / A) 503.
Inserted in the analog video signal converted by. Therefore, a video signal synchronized with the reference synchronization signal generated by the reference synchronization signal generation circuit 550 is obtained from the synchronization signal insertion circuit 540. By the way, the video signal written in the memory 502 is data for one field, and if this is read out in the field cycle, the phase of the color subcarrier will be the same for each field, and the 4-field sequence (color subcarrier) The phase is not continuous). That is, the output signal of the synchronization signal insertion circuit 50 is
The horizontal sync signal and vertical sync signal are continuous, but the phase of the color subcarrier is 180 degrees for each field (90 degrees shift due to vertical sync signal insertion, 90 degrees accompanying reset of the memory read address) The signal is deviated by (deviation). The color burst signal discontinuity detection circuit 570, the delay circuit 560, and the selector 580 are provided to correct the phase of this color subcarrier. First, the color burst signal discontinuity detection circuit 570 is composed of a phase comparator or the like, monitors the phase of the color subcarrier during the color burst period for each line, and detects the discontinuity of the color subcarrier phase. To do. The delay circuit 560 delays the video signal so that the phase of the color subcarrier is inverted (about 140n).
s) It is a delay circuit, and the selector 580 switches between the signal passing through the delay circuit 560 and the signal not passing through the delay circuit 560 according to the detection signal from the color burst signal discontinuity detection circuit 570. That is, when the operation of the color burst signal discontinuity detection circuit 570 detects phase discontinuity (shift of 180 degrees) of the color subcarrier, the selector 580 causes the delay circuit 5 to operate.
By switching to a signal that has passed 60 (a signal that is delayed by 180 degrees in the phase of the color subcarrier) and a signal that does not pass the delay circuit 560, the phase of the color subcarrier from the sync signal insertion circuit 540 can be different for each field. Corrects continuous video signals. Therefore, from the output terminal 520 of the device, in synchronization with the reference synchronization signal generated by the reference synchronization signal generation circuit 550, and
A video signal in which the phases of the color subcarriers are continuous is output.

With the above configuration, a video special playback device is configured,
Independently of the input video signal, a horizontal sync signal, a vertical sync signal, and a video signal in which the phases of the color subcarriers are continuous are output.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In this conventional method, a horizontal synchronizing signal and a vertical synchronizing signal are not stored in a memory, a video signal is read from the memory,
By inserting the sync signal after converting to the analog video signal, the continuity of the sync signal is maintained, and the phase of the color subcarrier is also read from the memory and converted to the analog video signal, and then the color The phase discontinuity of the subcarrier is detected and corrected. Therefore, there are problems that the number of analog parts increases, the circuit configuration becomes complicated, and the cost increases.

Means for Solving the Problems The present invention has been made in view of the above point, and it is possible to store a video signal for one field including a synchronization signal in a memory and control a read address when reading from the memory. Thus, the read address control circuit is configured so that the horizontal synchronizing signal, the vertical synchronizing signal, and the phase of the color subcarrier are continuous.

The present invention has the above-described configuration, and when reading from the memory, the horizontal synchronizing signal is loaded by loading the address that is offset by 1/2 horizontal scanning period for each field as the starting address for the horizontal synchronizing signal. To maintain continuity and read the vertical sync signal,
In the field to which the offset of 1/2 horizontal scanning period is given, the continuity of the vertical synchronizing signal is maintained by returning the offset, and furthermore, the offset is given by 180 degrees in the cycle of the color subcarrier as the start address for each frame. The phase continuity of the color subcarrier is maintained by reading out the color subcarrier.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a video special reproduction apparatus according to the present invention. In FIG. 1, 10 is a video signal input terminal, and 20 is a video signal output terminal. In addition, 1 is A / which converts an analog video signal to digital.
D converter (A / D), 2 is a memory such as RAM that can store one field of video signal,
3 is a D / A converter (D / A) for converting a digital video signal read from the memory to analog, 4 is a write clock generation circuit for generating a clock for writing to the memory, and 5 is a memory clock The write address control circuit 6 for controlling the write address is a read address control circuit for controlling the read address of the memory, and 7 is a read clock generating circuit for generating a clock for reading the memory. Further, 601 is a vertical sync signal address control circuit that controls the read address generated by the read address control circuit 6 so that the continuity of the vertical sync signal is maintained when reading from the memory, and 602 is also the horizontal sync signal address control circuit. A horizontal sync signal address control circuit that controls the read address control circuit 6 so that the continuity of the sync signal is maintained, and a burst 602 that similarly controls the read address control circuit 6 so that the phase of the color subcarrier becomes continuous. This is a signal address control circuit. Further, 30 is a sync signal separation circuit that separates a sync signal component included in the video signal, and 50 is a reference sync signal generation circuit that generates a reference sync signal when reading from the memory.

The operation of the special playback device for video according to the present invention configured as described above will be described below with reference to FIG.

The analog video signal input from the input terminal 10 of the device is sent to the A / D converter (A / D) 1 and is also sent to the sync signal separation circuit 30 where the horizontal sync signal and the vertical sync signal are separated. It The analog video signal input to the A / D converter (A / D) 1 is converted into a digital video signal here and sent to the memory 2. On the other hand, in the write clock generation circuit 4, the write clock is generated in synchronization with the horizontal sync signal separated by the sync signal separation circuit 30. The write address control circuit 5 controls the write address of the memory 2 in synchronization with the horizontal sync signal and the vertical sync signal separated by the sync signal separation circuit 30. At this time, the write address control circuit 5 is different from the case of the conventional example shown in FIG. 5 in that it is configured to continuously generate addresses even during the period of the synchronizing signal in the video signal. The video signal for one field including the sync signal is written.

On the other hand, in the reference synchronization signal generation circuit 50, a horizontal synchronization signal and a vertical synchronization signal which serve as a reference when the memory 2 is read are generated, and in the read clock generation circuit 7,
A read clock synchronized with the reference horizontal sync signal is generated. The read address control circuit 6 generates a read address in synchronization with the reference horizontal sync signal and the vertical sync signal generated by the reference sync signal generation circuit 50, and at the same time, the vertical sync signal address control circuit 601 and the horizontal sync signal address control. The read address of the memory 2 is controlled by the circuit 602 and the burst signal address control circuit 603 so that the phase of the vertical synchronizing signal, the horizontal synchronizing signal and the color subcarrier of the video signal read from the memory 2 are continuous. Control.

Here, a method of controlling the read address of the memory in the read address control circuit 6 will be described. Second
The figure shows the contents written in the memory 2. In the figure, symbols (1) to (4) show the phases of the color subcarriers of the video signal.

First, the operation of the horizontal synchronization signal address control circuit 602 will be described. The vertical synchronizing signal generated by the reference synchronizing signal generating circuit 50 is synchronized in the 262.5 horizontal scanning period. Therefore, the video signal read from the start address of the memory, that is, the position (p) in FIG. The first field ends at position (q). Next, when the start address of the second field is loaded, the continuity of the horizontal synchronizing signal is maintained by loading the position (r) shifted by 1/2 horizontal scanning period instead of the position (p) in FIG. At this time, the end address of the second field is the position (s). After the third field, the continuity of the horizontal synchronizing signal is similarly maintained by repeating the above. That is, the horizontal sync signal address control circuit 60
2 is 1/2 the start address of memory for each field
By shifting only the horizontal scanning period, the continuity of the horizontal synchronizing signal of the read video signal is maintained.

Next, the operation of the vertical sync signal address control circuit 601 will be described. The video signal read by shifting the start address by 1/2 horizontal scanning period for each field in order to maintain the continuity of the horizontal synchronization signal is As a result, the 262 horizontal scanning periods and the 263 horizontal scanning periods appear alternately as the period of the vertical synchronizing signal. Therefore, as the cycle of the vertical sync signal
The vertical synchronization signal address control circuit 601 operates as follows so that the 262.5 horizontal scanning period is always maintained. That is, when the position (p) in FIG. 2 is loaded as the start address of the memory, it is read as it is without doing anything, and when the position (r) in FIG. 2 is loaded as the start address of the memory, vertical reading is performed. In order to prevent the sync signal from being read early, when reading just before the vertical sync signal, the previous address is reloaded for 1/2 horizontal scanning period, and the address is read again immediately after the vertical sync signal is read. Is returned to the position shifted by 1/2 horizontal scanning period. FIG. 3 is a diagram for explaining reading of the vertical synchronizing signal. The above operation will be described with reference to FIG. 3. When the position (p) shown in FIG. 2 is loaded as the start address of the memory, as shown in FIG. 3 (a), during the vertical synchronizing signal period. Also, when the position (r) shown in FIG. 2 is read as the start address of the memory, as shown in FIG. 3B, immediately before the vertical synchronizing signal (FIG. 3B). When the data is read up to the position (r ₁ ) shown in ( ₁ ), (r ₂ ) is reloaded as the read address, and immediately after the vertical synchronizing signal (when read up to the position (r ₃ ) shown in FIG. 3 (b), read once again loaded as address (r ₄₎ are. Thus the vertical synchronizing signal address control circuit 601, when the address is shifted by half a horizontal scanning period as the start address of the memory is loaded, the vertical synchronizing signal is read Just before the address is read out, the previous address is reloaded for 1/2 horizontal scanning period, and immediately after the vertical sync signal is read, the address after that is read again for 1/2 horizontal scanning period. The continuity of the vertical sync signal is maintained.

Next, the operation of the burst signal address control circuit 603 will be described. FIG. 4 shows the phase of the color subcarrier of the read video signal in consideration of the continuity of the horizontal synchronizing signal and the vertical synchronizing signal. . In FIG. 4, the phase of the color subcarrier is continuous between the first field and the second field and between the third field and the fourth field, but between the second field and the third field,
The phases are inverted between the fourth field and the first field. Therefore, the burst signal address control circuit 603 loads the start address without giving an offset in the first field and the second field in FIG. 4, and uses it as the start address when reading the third field and the fourth field. , The phase continuity of the color subcarrier is maintained by loading the address shifted by 180 ° in the cycle of the color subcarrier.
That is, in FIG. 4, when reading the third field, the address indicating (t ′) is loaded as the start address, not the position (t) in FIG. Load the address at (v ') instead of at position (v) in (d).

At this time, the phases of the color subcarriers of the read video signal are p → q → r → in order from the first field shown in FIG.
s → t ′ → u ′ → v ′ → w ′, and the phase continuity of the color subcarrier is maintained. Therefore, the burst signal address control circuit 603 loads the address shifted by π in the cycle of the color subcarrier for each two fields as the start address of the memory, thereby ensuring the continuity of the phase of the color subcarrier of the read video signal. Hold.

With the above configuration, the vertical synchronization signal address control circuit 60
1. Horizontal sync signal address control circuit 602, burst signal address control circuit 603, and read address control circuit 6
The horizontal sync signal, the vertical sync signal, and the video signal read out while maintaining the phase continuity of the color subcarrier are then sent to the D / A converter (D / A) 3 for analog video. It is converted into a signal and output from the output terminal 20.

EFFECTS OF THE INVENTION As is clear from the above embodiments, in the video special reproduction apparatus according to the present invention, the video signal is read from the memory.
After D / A conversion, without adding sync signal,
The video signal is stored in the memory including the sync signal,
At the time of reading, by controlling the read address, the horizontal sync signal, the vertical sync signal, and the color subcarrier are maintained in phase continuity and read, so the circuit configuration is simplified, the cost is reduced, and the reliability is improved. The practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a video special playback device according to the present invention, FIG. 2 is an explanatory diagram showing a storage state of a memory in the video special playback device according to the present invention, and FIG. 3 is a book. FIG. 4 is an explanatory view of the operation of reading the video signal from the memory in consideration of the continuity of the synchronizing signal in the video special reproduction apparatus according to the invention, and FIG. 4 shows the phase continuity of the color subcarriers in the video special reproduction apparatus according to the present invention. FIG. 5 is a block diagram showing a configuration of a conventional video special playback device, and FIG. 6 shows a storage state of the memory in the conventional video special playback device. FIG. 1,501 …… A / D converter (A / D), 2,502 …… Memory, 3,503
...... D / A converter (D / A), 4,504 …… Write clock generation circuit, 5,505 …… Write address control circuit, 6,506…
... Read address control circuit, 7,507 ... Read clock generation circuit, 10,510 ... Input terminal, 20,520 ... Output terminal, 30,530 ... Sync signal separation circuit, 540 ... Sync signal insertion circuit, 50,550 ... Reference sync signal generation circuit , 560 ... Delay circuit, 570 ... Color burst signal discontinuity detection circuit, 5
80 ... Selector, 601 ... Vertical sync signal address control circuit, 602 ... Horizontal sync signal address control circuit, 603 ... Burst signal address control circuit.

Front page continuation (72) Inventor Kojiro Matsumoto 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-53-85116 (JP, A) JP-A-61-189081 (JP) , A)

Claims (1)

(57) [Claims] 1. A control method for the reading means, comprising: storage means for at least one field capable of storing a composite video signal including a synchronization signal; and read means for controlling a read address of the storage means. , A horizontal synchronizing signal continuity holding means by loading an address which is offset by 1/2 horizontal scanning period for each field as a start address, and the vertical synchronizing signal can be read by using the 1/2 horizontal scanning as a start address. In the field to which the period offset is given, the vertical synchronization signal continuity holding means by returning the offset, and further, the color sub-pixel by offsetting and reading by 180 degrees in the cycle of the color sub-carrier as a start address for each frame The video special feature is characterized by comprising carrier wave phase continuity maintaining means. Reproducing apparatus.