JP2529720B2 - Direct memory access device - Google Patents

Description

Detailed Description [Table of Contents] Outline Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problem Action Example Effect of the invention [Overview] Between multiple channels and memory Direct memory access (DMA) device that directly transfers data in the above, with the aim of providing a direct memory access device that enables efficient data transfer regardless of bus usage conditions Of the channels, the bus with the highest priority is given to the bus mastership management unit that grants the mastership of the bus and each channel is provided with the bus mastership management unit. Until the bus control right management means is used, and the bus is used when the bus control right acquisition of the channel is permitted by the bus control right management means. A plurality of memory access means for initiating direct memory access of the channel; and a plurality of request delay means for delaying a bus mastership acquisition request given from the memory access means to the bus mastership management means by a set time. Have.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access device in which data is transferred between a plurality of channels and a memory by a DMA method.

This device can be used in systems that control a large number of lines, where each line is a separate channel from one another.

Channels that can be used for DMA transfer are determined according to the priority of bus use right acquisition, and data transfer is often performed in the singles step mode.

[Prior Art] FIG. 4 shows an example of a line controller which performs a DMA transfer in a single step mode. The memory 40 (main memory) and the I / O registers 42 of channels 1, 2, 3, and 4 are shown. -1,42-2,42-
Data transfer between 3,42-4 and DMA controller 44-
1,44-2,44-3,44-4.

And data communication is being performed with the other devices via the I / O registers 42-1, 42-2, 42-3, 42-4 and the line, and by performing the data transfer, The data of each line is written in the memory 40, and the data of the memory 40 is sent to each line.

It also acquires the right to use the bus 46 to transfer data to the memory 40
The channel 1, 2, 3 or 4 that can be executed between and is determined by the priority encoder / decoder 48. In the priority encoder / decoder 48, the channels for which the usage right can be acquired are shown in the truth table shown in FIG. Therefore it has been decided.

From the line side of these channels 1, 2, 3, and 4 I / O register 42-
DMA controller 44-1, 4 via 1, 42-2, 42-3, 42-4
Input / output request signal I / OREQ1, I / OREQ2, I to 4-2,44-3,44-4
When / OREQ3 and I / OREQ4 are given, DMA controller 44-
Priority encoder from 1,44-2,44-3,44-4
Request signal to the decoder 48 to acquire bus mastership BREQ1, BREQ2, BR
EQ3 and BREQ4 are issued.

Bus 46 with its priority encoder / decoder 48
When the channel that can acquire the mastership of the bus is determined according to the contents of Fig. 5, the DMA controller 44-1, 44-2, 44-3 or 44-4 of the corresponding channel is granted the acquisition of the bus mastership. The signals PRN-1, PRN-2, PRN-3 or PRN-4 are output.

In FIG. 5, it is shown that the acquisition of the bus control right with the value “1” is not allowed with the value “0”, and also from FIG. 5 (D), (E), and (F). As you can see, the acquisition of bus control is channel 1, channel 2, channel
3, Channel 4 has priority.

The operation of this conventional example is explained in FIG.
46 is empty when the bus signal BUSY shown in FIG.

And, in the same figure (B), (C), (D), (E), the request signals BREQ1, BREQ2, BREQ3, BREQ for acquiring the bus control right are shown.
4 is continuously sent out sequentially from the DMA controllers 44-1, 44-2, 44-3, 44-4. In this case, DMA transfer is first performed with the channel 1 having the highest priority. Be done.

When the DMA transfer is completed, the priority of the channel 2 becomes the highest, so that the DMA transfer is next performed with the channel 2 as shown in FIG.

When the data transfer with channel 2 is completed,
Since the request signal REQ1 for acquiring the bus mastership is repeatedly issued from the channel 1 in the single step mode as shown in FIG. 6B, the DMA transfer is restarted with the channel 1 as shown in FIG. It

Therefore, as shown in (D) and (E) of FIG.
Although the bus control right acquisition request signals BREQ3 and BREQ4 are issued from the devices, the permission signals PRN3 and PRN4 are issued to the channels 3 and 4 as shown in (H) and (I) of the figure. No DMA transfer is performed between them.

[Problems to be Solved by the Invention] As described above, in the conventional case, each channel and memory 40
When a single-step mode DMA transfer is started between and, the bus 46 is occupied by the high-priority channel.

For this reason, a channel having a low priority for acquiring the bus use right cannot acquire the bus control right and cannot perform the DMA transfer.

Therefore, even if a channel with low priority requests data transfer, only a small number of channels with high priority actually perform data transfer, and overall data transfer efficiency decreases. To do.

The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a direct memory access device capable of efficient memory access without occupying a bus control right in a channel having a high priority. It is in.

[Means for Solving the Problems] In order to achieve the above object, an apparatus according to the present invention has a first
It is configured as shown.

In the figure, among the channels required to acquire the bus control right, a bus control right management means for permitting the bus control right to the channel having the highest priority and a bus for the channel are provided for each channel. The bus mastership management means is requested until the bus mastership management means permits the acquisition of the mastership, and when the bus mastership management means permits the bus mastership management of the channel, A plurality of memory access means for initiating direct memory access; and a plurality of request delay means for delaying a bus control right acquisition request given from the memory access means to the bus control right management means by a set time. Has been done.

[Operation] According to the present invention, the bus mastership acquisition request for each channel is delayed, and therefore a request having a higher priority that occurs later is delayed.

Therefore, even in the channel with a lower priority that occurred earlier,
The bus right can be acquired by utilizing the gap generated by the delay, and each channel can access the memory equally depending on the setting of the delay time.

[Embodiment] A preferred embodiment of an apparatus according to the present invention will be described below with reference to the drawings.

FIG. 2 illustrates an example of the line control device, and the number of channels is 15 in this example.

And channel 1 is said to be for HLD, and it is 4 Kbps at 48 Kbps.
It corresponds to the line.

Channel 2, channel 3 ... Channel 15 are for CDT, and can support a maximum of 3 lines in the 44-bit format of 1200 bps, and the total number of them is 32 lines.

Here, the DMA controller 44 of channels 1, 2, 3 ... 15
-1,44-2,44-3 ... 44-15 output signal request signals BREQ1,2,3 ... 15 from the bus masters are delay circuits 50-1,5
It is given to the priority encoder / decoder 48 via 0-2, 50-3 ... 50-15, respectively.

The signal delay time by these delay circuits 50-1, 50-2, 50-3 ... 50-15 is set so that the bus control is evenly distributed to channels 1, 2, 3 ... 15. Next, the setting example will be described.

When 16bit = 1 word is accessed at a time with channel 1, Channel 1 is at least 83 μse as shown in
It is necessary to obtain bus control for each c.

Also, since CDT44bti is 2 words, As shown by the equation, the channels 2, 3, ... 15 need to acquire the bus mastership at least every 6111 μsec.

Furthermore, if bus performance is required such that the bus occupation time required for each input / output of each channel is 2 μsec, 1
In order to evenly distribute the bus control right to the 5 lines, a delay time of 30 μsec is required as shown by the formula of 2 × 15 = 30 (μsec).

The delay time (= 30μsec) is shorter than the shortest access cycle of HDL and CDT (= 83μsec, = 6111μsec), so the request signal BREQ1, BREQ2, B for bus mastership is obtained for 30μsec.
By delaying REQ3 ... BREQ15, it becomes possible to distribute the bus control right to all the channels while satisfying the required performance.

The operation of this embodiment is described in FIG. 3, in which bus control is evenly distributed to channels 1, 2, 3, and 4.

Here, as in the conventional example, the same figures (B), (C),
Request signal BREQ for bus mastership as in (D) and (E)
Although 1, BREQ2, BREQ3, and BREQ4 are sequentially generated, they are delayed by the delay circuits 50-1, 50-2, 50-3, and 50-4, and therefore, in (B) and (C) of FIG. Request signal BREQ1, BREQ2
Is delayed by the required time (same for signals BREQ3, BREQ ...).

Therefore, when the memory access for channel 1 is performed as shown in FIG. 6F and the memory access for channel 2 is performed as shown in FIG. 7G, the request signal BREQ1 is provided as shown in FIG. Is delayed, the same figure (D),
Of the request signals BREQ3 and BREQ4 in phase competing with each other (E), access to the channel 3 having the higher priority is permitted as shown in FIG.

Even when the memory access is completed, the request signals BREQ1 and BREQ2 are delayed from the signal BERQ4 in the same figure (E) as shown in the same figure (B) and (C).
As described above, the acquisition of the bus control right is permitted for the channel 4 having the lowest priority, and the memory access for the channel 4 is performed.

During the access, the delayed request signal BREQ1 of channel 1 is given to the priority encoder / decoder 48 as shown in FIG. 7 (B), so that memory access of channel 1 is performed after channels 3 and 4.

As described above, according to the present embodiment, the bus mastership acquisition request is delayed by a predetermined time, so that the bus 46 is not occupied by a small number of specific channels (1, 2 ...). It becomes possible to evenly distribute the bus control right to all channels 1, 2, 3 ... 15.

Therefore, channels with different priorities 1, 2, 3, ... 15
Memory access can be performed evenly, which enables efficient data communication.

Further, according to the present embodiment, the delay circuits 50-1, 50-2, 50-3
... 50-10 is DMA controller 44-1,44-2,44-3
..Priority encoders provided on the 44-15 side
Since it is not provided on the decoder 48 side, the delay circuit 50-1,
It is possible to easily set delay times of 50-2, 50-3 ... 50-15 according to the corresponding line.

It is also possible to provide means corresponding to the delay circuits 50-1, 50-2, 50-3, ... 50-15 on the priority encoder / decoder 48 side.

[Effects of the Invention] According to the present invention as described above, the request for bus mastership is delayed by a predetermined time, so that direct memory access is performed between a plurality of channels and a memory in a single step mode. Even in such a case, the channel with the lower priority can perform the memory access, so that the memory access concentration on the channel with the higher priority can be avoided and the data transfer of the device can be made efficient.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the invention, FIG. 2 is an explanatory view of the configuration of the embodiment, FIG. 3 is an explanatory view of the operation of the embodiment, FIG. 4 is an explanatory view of the configuration of a conventional device, and FIG. FIG. 6 is an explanatory diagram of the order of priority of acquisition, and FIG. 6 is an explanatory diagram of the operation of the conventional device. 40 ... Memory 42-1,42-2,42-3,42-4 ... 42-15 ... I / O register 44-1,44-2,44-3,44-4 ... 44 −15 …… DMA controller 46 …… Bus 48 …… Priority encoder / decoder 50-1,50−2,50-3 ・ ・ ・ 50−15 …… Delay circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Yamana 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited Ltd. 72) Inventor Ryosuke Hirose 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takahiro Yamamoto 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP 62 -67653 (JP, A)

Claims (1)

(57) [Claims] 1. A bus (10) is provided to a channel having the highest priority among the channels required to acquire the bus control right.
Bus control right management means (12) for permitting the acquisition of the control right of the bus and the bus control right management means provided for each channel until the bus control right management means (12) permits the acquisition of the bus control right of the corresponding channel. A plurality of memory access means for requesting (12) and starting direct memory access of the channel using the bus (10) when the bus mastership management means (12) permits the acquisition of the bus mastership of the channel. (14-1,
14-2 ... 14-n) and a request for bus mastership given from the memory access means (14-1, 14-2 ... 14-n) to the bus mastership management means (12) are set. A direct memory access device comprising: a plurality of request delay means (16-1, 16-2 ... 16-n) for respectively delaying by time.