JP2530834B2 - Data laminated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data stacking circuit that stacks serial data, and more particularly to a data stacking circuit that stores stacking data in a storage unit that can be written and read in word units.

[Prior Art and its Problems] As a method of stacking serial data having a limited length, a multiple shift register method and a multiple RAM method have been conventionally known.

5 and 6 are schematic circuit diagrams showing a conventional data stacking method.

In the multiple shift register system shown in FIG. 5, multiple stages of shift registers 101 are connected in series, and after writing serial data from the highest stage to the lowest stage, each shift register 101
The parallel data is obtained by reading the data at the same time from.

However, this method has a problem that the length of processable data is fixed because the data length of serial data and the number of bits of the shift register must match. In addition, since it is difficult to obtain an inexpensive shift register, it becomes expensive as a whole.

In the multiple RAM system shown in FIG. 6, a 1-bit RAM (Random
Access memory) 102 is arranged in a plurality of stages, each stage is selected by a decoder, serial data is written, and they are simultaneously read to obtain parallel data.

This method is more flexible in terms of data length than the above-mentioned multiple shift register method. However, it is necessary to provide a 1-bit RAM for the number of bits of the parallel data, and there is a problem in that the read time is delayed due to variations in characteristics among the RAMs.

Further, since there are few types of 1-bit RAM, there is a problem that the unnecessary memory portion increases depending on the length of serial data.

[Means for Solving Problems] The present invention is intended to solve the above-mentioned conventional problems, and an object thereof is to flexibly cope with the length of serial data and to provide a small number of storage elements. It is an object of the present invention to provide a data laminated circuit capable of performing high-speed laminating processing using the data laminated circuit.

A data stacking circuit of the present invention includes a storage unit capable of writing and reading in word units, a data storage unit that temporarily stores data for one word consisting of a plurality of bits read from the storage unit, and a storage unit that stores the data in the data storage unit. A selection unit composed of a number of selectors corresponding to the respective bits of the stored word, wherein each selector of the selection unit receives each bit of the word temporarily stored in the data storage unit as a first input.
, A second input to which serial data is commonly input, and a decoder to select one of the bit input to the first input and the serial data input to the second input. And a third input to which the decoder output of the selector is input, the decoder according to the count value of the stage counter that advances in accordance with a signal representing the data length of the storage means. The serial data is sequentially written only to the bit selected by the selecting means, and the serial data is stacked and stored in the storage means.

[Operation] As described above, in order to perform serial data stacking processing by using the storage unit capable of writing and reading in word units, at least one storage unit having a sufficient capacity is provided, and the data length corresponding to the capacity is provided. The following serial data having an arbitrary data length can be stacked.

Further, since the operation is performed in word units, high speed processing and high speed reading are possible.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic circuit diagram of an embodiment of a data laminated circuit according to the present invention.

In this embodiment, the RAM 1 of 8 bits × 2048 words is used as the storage means capable of reading and writing word by word.

In the figure, each terminal of the input / output port of RAM1 is a D-type flip-flop 2 (hereinafter referred to as "DF
F2 ". ) Is connected to each input terminal, and is further connected to the pull-up resistor 3. The DFF 2 temporarily holds the data for one word read from the RAM _1, and then outputs each bit to the selectors A _{1 to} A ₈ .

The selectors A _{1 to} A ₈ respectively input the data from the DFF 2 bit by bit and also input serial data. Then, either one is selected according to the decoder output from the decoder 4, and the selected 8-bit data is output to the RAM 1. The details will be described later.

The decoder 4 outputs a selection signal to any of the selectors A _{1 to} A ₈ according to the count value from the stage counter 5.

The stage counter 5 receives a pulse representing the data length from the RAM address counter 6 as a stage counter pulse and outputs the count value to the decoder 4. Therefore, the count value is incremented for each data length, and represents the stacking stage of data.

The address counter 6 advances by the count pulse from the control circuit 7 and
Specify the address of RAM1. Here, since the RAM 1 has 2048 words, the address counter 6 requires 11 bits at maximum. When data is written to RAM1 for the data length, the stage counter pulse is sent to the stage counter 5 to move to the next stage.
And outputs the count value to the start address of RAM1.

The control circuit 7 outputs a read pulse φr and a write pulse φw for performing the data stacking process, and a reset pulse for resetting each counter.

The present embodiment has such a basic configuration, and serial data is stacked and written in the RAM 1 by the write pulse WP input to the control circuit 7, and the stacked data is read as parallel data by the read pulse RP.

FIG. 2 is a partial equivalent circuit diagram of this embodiment. In addition, here, only one arbitrary selector is shown among the selectors A _{1 to} A ₈ .

In the figure, the write pulse φw from the control circuit 7 is input to the decoder 4 and each selector A as a gate signal through the inverter 10. The serial data is input to each selector A as negative logic serial data through the inverter 11.

In the selector A, one output from the decoder 4 and the gate signal are input to the AND circuit 12, and the output is input to the open collector NAND circuit 13. NAND circuit 13
Further, 1-bit positive logic data from DFF2 is input to.

Further, the NOR circuit 14 receives the serial data and each inverted signal of the decoder output, and the AND output thereof is input to the open collector inverter 15.

The outputs of the NAND circuit 13 and the inverter 15 are wired-OR connected and connected to the input / output port of the RAM1. This data is negative logic.

Next, the operation of the selector A will be described based on the truth table shown below.

(When the gate signal is at "L" level) The decoder output is at "H" level in all the selectors A. Therefore, regardless of the serial data and the data from DFF2, the output becomes "H" level in all the selectors A and does not affect the outside. That is, the selector A is in the OFF state.

(When the gate signal is at "H" level) As for the decoder output, only one output designated by the count value of the stage counter 5 becomes "L" level, and the other outputs become "H" level.

(1) If not specified by the stage counter 5, the decoder output in the selector A is at "H" level, so the AND output is at "H" level and the AND output is independent of serial data. Therefore, the gate of the NAND circuit 13 is opened, and the inverted version of the output of DFF2 is output as RAM1.
Is written to.

That is, the selector A not designated by the stage counter 5 selects the output of DFF2 and writes it to the bit of the corresponding stage of RAM1.

(2) When specified by the stage counter 5, the decoder output in the selector A is at "L" level.
The AND output is always at "L" level and the gate of the NAND circuit 13 is closed. On the other hand, the gate of the NOR circuit 14 is opened,
The inverted serial data (AND output) is further inverted by the inverter 15 and written to the RAM 1 as an output.

That is, the selector A designated by the stage counter 5 selects the serial data and writes it to the bit of the corresponding stage of the RAM1.

Next, the data stacking operation of this embodiment will be described with reference to FIGS.

3A and 3B are explanatory views of the data stacking operation in this embodiment. However, "1" indicates "H" level, "0" indicates "L" level, RAM is negative logic, DFF is positive logic, and serial data is negative logic.

For convenience of explanation, here, as shown in FIG.
The serial data with a data length of n bits is negative logic in RAM1 and is the first stage
It is assumed that C ₁ to the third stage C _{3 are} stacked. In addition,
The stacking operation is started when the write pulse WP is input to the control circuit 7.

When the writing of the data in the third stage C ₃ is completed and the count pulse is output from the control circuit 7, the RAM address counter 6 specifies the head address AD ₁ of RAM ₁ and outputs the stage counter pulse.

The step counter 5 advances by the step counter pulse,
Specify the fourth stage C ₄ . In response to this, the decoder 4 is in a ready state for providing the "L" level decoder output only to the selector A ₄ and the "H" level output to the other selectors, and the gate signal becomes "H" level. Give output. That is, as described above, the selectors A _{1 to} A ₈ are
Only selector A ₄ selects serial data and the other selectors are in condition to select the output from DFF 2.

In this state, the read pulse φr is output from the control circuit 7, and as shown in FIG.
The 1-word data of the address AD ₁ is inverted and stored in DFF2.

Then, the control circuit 7 outputs the write pulse φw, and as described in FIG. 2, only the selector A ₄ corresponding to the fourth stage selects the serial data, and the other selectors select the data of DFF2. . As a result, the bit of the fourth stage C ₄ among the data of the address AD ₁ of RAM 1, is stored first bit "0" of the serial data, the other stages data DFF2 is stored as it is.

When the processing of the address AD ₁ is completed, the control circuit 7 outputs a count pulse to the address counter 6 to increment the counter and designates the next address AD ₂ of the RAM 1. Then, the same processing is performed on the data of the address AD ₂ . That is, of the 8-bit data of address AD _2, the second bit “0” of serial data is stored in the bit corresponding to the fourth stage C ₄ , and the data of DFF 2 is stored in the bit corresponding to the other stage.

By performing such an operation up to the address ADn, the third
As shown in FIG. (B), the serial data of n bits shown in (A) is laminated to the fourth stage C ₄ of RAM 1.

When the processing for the address ADn is completed and the next count pulse is input to the RAM address counter 6, the RAM address counter 6 again designates the start address AD _{1 of} RAM ₁ , and outputs the stage counter pulse to output the stage counter 5
Step forward. As a result, the decoder 4 is in a ready state for providing an "L" level output to the selector A ₅ corresponding to the fifth stage.

Similarly, the stage counter 5 is incremented each time the address ADn is reached in each stage, and serial data is stacked up to the eighth stage C ₈ .

When the stacking process of serial data is completed, read pulse RP
Can be read as parallel data by inputting to the control circuit 7. That is, the control circuit 7 reads out the outputs of the read pulse φr to RAM1 and DFF2, to sequentially DFF2 the 8-bit data stacked up address AD _1-ADn by the address counter 6, DF
The stacked data is read out as parallel data from the output terminal of F2 to the outside.

FIG. 4 is a schematic configuration diagram of an image input device which is an application example of the present embodiment.

In the figure, the laminated circuit 201 and the RAM 1 correspond to the present embodiment (FIG. 1).

The light reflected by the reading object 202 forms an image on the line sensor 204 by the imaging optical system 203, and one line of image data is read by scanning the line sensor 204 in the direction of arrow X. The reading target 202 is, for example, an inspection object for inspecting a pattern, an inspection object having a fine pattern, an original document for image processing, a photograph, or the like.

The reading target 202 relatively moves in the arrow Y direction orthogonal to the arrow X direction, and the line sensor 204 sequentially reads the linear image data each time.

The data read by the line sensor 204 is subjected to processing such as amplification and binarization by the signal processing circuit 205, and is input to the laminated circuit 201 as serial data.

The laminated circuit 201 performs the above-described processing to laminate and store the serial image data in the RAM 1. Therefore, RAM1
Stores image data in the same format as that captured by the area sensor. For example, it is possible to store the area-shaped image information of the read target 202 in the RAM 1 in the same area.

Then, the data of RAM1 can be read as parallel data by the read pulse RP.

[Effects of the Invention] As described in detail above, the data stacking circuit according to the present invention has a storage means having a sufficient capacity for performing serial data stacking processing using a storage means capable of writing and reading in word units. By providing at least one, it is possible to stack serial data having an arbitrary data length equal to or shorter than the data length corresponding to the capacity. Therefore, the flexibility regarding the data length is significantly improved as compared with the conventional one.

Further, since the storage means is integrated, there is no variation in the reading time, which is advantageous in terms of cost. further,
Since the storage means operates in units of words, high speed processing and high speed reading of parallel data are possible.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of one embodiment of a data laminated circuit according to the present invention, FIG. 2 is a partial equivalent circuit diagram of this embodiment, and FIGS. 3 (A) and 3 (B) are the same. FIG. 4 is an explanatory diagram of a data stacking operation in the embodiment, FIG. 4 is a schematic configuration diagram of an image input device which is an application example of the present embodiment, and FIGS. 5 and 6 are schematic views showing a conventional data stacking method. It is a circuit diagram. 1 …… RAM 2 …… D type flip-flop 5 …… Stage counter 6 …… Address counter A _{1 to} A ₈ …… Selector

Claims (1)

(57) [Claims] 1. A storage means capable of writing and reading in word units, a data holding means for temporarily holding data of one word consisting of a plurality of bits read from the storage means, and the data holding means. A selector having a number of selectors corresponding to each bit of the word, wherein each selector of the selector has a first input to which each bit of the word temporarily held in the data holding unit is input; A second input to which serial data is commonly input,
A third input to which a decoder output from the decoder is input to select either one of the bit input to the first input and the serial data input to the second input, Controls each selector of the selecting means in accordance with the count value of the stage counter which advances in accordance with a signal representing the data length of the storage means, whereby the serial connection is performed only on the bit selected by the selecting means. A data stacking circuit, which is configured to sequentially write data and store the serial data in a stacked manner in the storage means.