JP2531805B2 - Digital PLL circuit - Google Patents

Description

The present invention relates to a digital PLL circuit, and more particularly to a digital PLL including a semiconductor integrated circuit.

[Conventional technology]

Conventionally, in this type of digital PLL circuit, as shown in FIG. 3, a variable frequency dividing circuit 20 is controlled by a microcomputer 21 by a code signal 3 to divide an input signal 1 into a frequency equivalent to a reference signal 6. . The reference signal generation circuit 23 has an internal or external oscillator, generates a reference signal 6 with a clock obtained from this, and outputs it to the phase comparison circuit 22.
The system clock 8 synchronized with is output to the outside.
The microcomputer 21 uses the frequency setting signal 9 to change the frequency divider circuit.
The code to 20 is determined, and the code signal 3 is output to the variable frequency dividing circuit. The phase comparison circuit 22 compares the phases of the output signal 2 of the variable frequency dividing circuit 20 and the reference signal 6 with each other, and when the synchronization is not established, outputs the advance / delay signal 5 to the correction circuit 24 to establish the synchronization. In this case, the synchronization establishment signal 4 is output to the outside.
The correction circuit 24 outputs the correction signal 7 to the reference signal generation circuit 23 based on the result of the lead / lag of the output signal 2 of the variable frequency dividing circuit 20. With the above circuit configuration, the frequency range in which the input signal 1 can be locked is obtained from the frequency of the reference signal 6 and the frequency division ratio of the variable frequency dividing circuit 20. For example, when the reference signal 6 is 1 KHz and the frequency dividing ratio of the variable frequency dividing circuit 20 is 1/1 to 1/64,
The lockable frequency range of input signal 1 is 1KHz to 64KHz
Becomes

[Problems to be Solved by the Invention]

The conventional digital PLL circuit described above is a variable frequency divider circuit 20.
Therefore, there is a drawback in that a control program must be used. Further, as the frequency of the input signal becomes higher, the frequency division ratio becomes larger, so that the variable frequency divider circuit 20 becomes complicated and the scale of the control program becomes large. Further, there is a drawback that the frequency of the input signal must be externally controlled each time the frequency of the input signal changes so that the frequency of the input signal can be divided into the same frequency.

An object of the present invention is to solve the above-mentioned drawbacks, to eliminate the need for a variable frequency dividing circuit, to reduce the scale of a control program, and to eliminate the need for external frequency division control.
To provide a circuit.

[Means for solving the problem]

The configuration of the present invention is a reference signal generation circuit that generates a reference signal to be synchronized with an input signal, a phase comparison circuit that compares the phases of the input signal and the reference signal, and outputs a lead / lag signal. In a digital PLL circuit including a correction circuit that applies a correction signal to the reference signal generation circuit based on the lead / lag signal so as to establish synchronization of the reference signal, the frequency of the input signal is determined. A frequency determination circuit that outputs a determination signal, and a clock generation circuit that outputs a specific clock signal based on the determination signal, by generating a reference signal of the reference signal generation circuit based on the specific clock signal, It is characterized in that a frequency range that can be synchronized with the input signal is obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a logic block diagram showing a digital PLL circuit according to an embodiment of the present invention. In Figure 1, this digital PL
In the L circuit, the input signal 1 is input to the frequency determination circuit 31 and further to the phase comparison circuit 30. The determination signal 4 of the frequency determination circuit 31 is input to the clock generation circuit 32. The specific clock generated by the clock generation circuit 32 is input to the reference signal generation circuit 33. The reference signal 6 generated by the reference signal generation circuit 33 is input to the phase comparison circuit 30 and further outputs a system clock 8 synchronized with the input signal 1 to the outside. The synchronization non-establishment signal 3 output from the phase comparison circuit 30 is input to the correction circuit 34 and the synchronization establishment signal 2 is output to the outside.
The correction signal 7 output from the correction circuit 34 is input to the reference signal generation circuit 33.

The frequency determination circuit 31 determines the frequency of the input signal 1,
The determination signal 4 is output to the clock generation circuit 32.

As shown in FIG. 4 (a), the frequency determination circuit 31 receives the input signal 1 and receives the counter number output lines 57, 58, 5
9,60 are output, and a D flip-flop (F / F) 52, a reset F / F 53, four inverters 61, and a two-input AND circuit 62 are provided, where F / F52, F / F53 Operates by a signal from the basic clock 11 in the clock generation circuit 32. FIG. 4B shows a timing chart when the circuit counter has five stages in FIG.
The output waveforms of the F52, the AND circuit 62, and the F / F53 with reset are output signals 72, 73, 74, 75, 76. For example, by configuring as shown in FIG. 4A, the frequency of the input signal 1 can be determined by the number of counts in a half cycle. In this circuit, the clock is set to 1 MHz and the count number, that is, the judgment signal 4 in FIG.
When the decimal is [100], the frequency of the input signal is 1MHz / (100
X2) = 5 KHz can be determined. The clock generation circuit 32 generates a specific clock 5 for the input signal 1 according to the determination signal 4 of the frequency determination circuit 31. As shown in FIG. 5, the specific clock 5 is the basic clock of the reference signal 6, and therefore has a resolution for establishing synchronization. For example, assuming that 10% of one cycle of the input signal 1 is one resolution, the frequency of the specific clock 5 is the frequency of the input signal 1.
10 times. In other words, the cycle is 1/10 times. The reference signal generation circuit 33 inputs the specific clock 5, generates a reference signal 6 having a frequency equivalent to that of the input signal 1 by dividing the specific clock 5 and outputs the reference signal 6 to the phase comparison circuit 30. The system clock 8 synchronized with is output to the outside. The phase comparison circuit 30 compares the phases of the input signal 1 and the reference signal 6 with each other, and outputs a lead / lag signal 3 to the correction circuit 34 when the synchronization is not established, and when the synchronization is established. The synchronization establishment signal 2 is output to the outside. Correction circuit 34
Outputs the correction signal 7 to the reference signal generating circuit 33 based on the result of the advance / delay of the input signal 1. With the above circuit configuration, by generating the specific clock 5 from the frequency of the input signal 1 and making the frequency of the reference signal 6 equal to the frequency of the input signal 1, the range of the clock frequency can be obtained for the input signal 1 and the specific frequency can be specified. By increasing the frequency of the clock 5, the correction width can be reduced and the resolution can be easily increased. Furthermore, if the frequency of the selected input signal 1 is within the lock frequency range, it is possible to synchronize at that frequency simply by changing the frequency of the input signal 1.

FIG. 2 is a circuit diagram showing a digital PLL circuit related to the present invention.

In FIG. 2, the frequency determining circuit 31 of FIG. 1 is omitted in this digital PLL circuit, and the other circuit block parts are almost the same as in FIG. In FIG. 2, the frequency judgment is performed by the phase comparison circuit 30 by judging the phase. That is, the phase difference between the input signal 1 and the reference signal 6 is detected, and if the phase difference is within a predetermined allowable range, the frequency of the reference signal 6 can be determined to be the frequency of the input signal 1 and the clock generation circuit 32 There is no need to change the frequency of the special clock 5. If the phase difference is large, by changing the frequency of the special clock 5 of the clock generation circuit 32 so that the phase difference can be determined to be within the allowable range, the frequency range in which the input signal can be locked, as in FIG. Can be obtained.

〔The invention's effect〕

As described above, the present invention has the means for determining the frequency of the input signal and the clock generation circuit for producing the operation clock of the reference signal generation circuit based on the result of the means, thereby providing the variable frequency dividing circuit and the control program. Is unnecessary, and if the frequency of the selected input signal is within the lock frequency range, synchronization can be achieved at that frequency simply by changing the frequency of the input signal, and the resolution for establishing synchronization increases. effective.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital PLL circuit according to an embodiment of the present invention, FIG. 2 is a block diagram relating to the present invention, FIG. 3 is a block diagram of a conventional digital PLL circuit, and FIG. FIG. 4 is a circuit diagram showing a circuit example of the frequency determination circuit of FIG.
4B is a timing diagram showing the operation waveforms of FIG. 4A, and FIG. 5 is a timing diagram showing the operation waveforms of the clocks between the logic blocks of FIG. 1 ... Input signal, 2 ... Synchronization establishment signal, 8 ... System clock, 9 ... Frequency setting signal, 11 ... Basic clock inside clock generation circuit, 20 ... Variable frequency dividing circuit, 21 ...
Microcomputer, 22,30 ... Phase comparison circuit, 23, 33 ... Reference signal generation circuit, 2, 34 ... Correction circuit, 32 ... Clock generation circuit, 31 ... Frequency determination circuit, 52 ... D type flip-flop , 53 …… Flip-flop with reset, 61 …… Inverter, 62 …… AND circuit.

Claims (1)

(57) [Claims] 1. A reference signal generation circuit for generating a reference signal to be synchronized with an input signal, a phase comparison circuit for comparing the phases of the input signal and the reference signal and outputting a lead / lag signal, In a digital PLL circuit including a correction circuit that applies a correction signal to the reference signal generation circuit based on the lead / lag signal so as to establish synchronization of the reference signal, the frequency of the input signal is determined and determined. A frequency determining circuit that outputs a signal, and a clock generating circuit that outputs a specific clock signal based on the determination signal, by generating a reference signal of the reference signal generating circuit based on the specific clock signal, A digital PLL circuit characterized in that a frequency range that can be synchronized with an input signal is obtained.