JP2533951B2 - Method for manufacturing bipolar semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a bipolar semiconductor device having high reliability and excellent frequency characteristics in a large current region.

[Conventional technology]

FIG. 5 is a conceptual diagram showing a bipolar transistor manufactured by a conventional method for manufacturing a bipolar semiconductor device.

As shown in FIG. 5, an N type epitaxial layer 4 is formed on a P type silicon substrate 1 on which an N ⁺ type buried layer 2 and a P ⁺ type buried layer 3 to be a channel stopper are formed. the Si ₃ N ₄ film used in the LOCOS method on the surface (not shown) is deposited by the LP-CVD method (low-pressure CVD method), the Si ₃ N
After removing the _four films, an oxide film is grown on the surface to a desired thickness to form the element isolation region 8.

Next, the remaining Si ₃ N ₄ film is removed, and the collector wall diffusion layer 5 is formed by ion implantation of N-type impurities and thermal diffusion treatment.
Is formed, and boron is similarly implanted into the base region and heat-treated and diffused to form the P ⁺ -type active base diffusion layer 6.

Next, a SiO ₂ film 9 is formed on the entire surface by CVD, for example, with a film thickness of 250 nm
After the deposition, the SiO ₂ film 9 is etched to form an emitter diffusion window X, and a polysilicon film 12 serving as an emitter extraction electrode is deposited on this surface to a thickness of 300 nm, for example.

Next, arsenic having a dose of about 1 × 10 ¹⁶ cm ^-2 is ion-implanted on the polysilicon film 9 to be an emitter electrode, and an N ⁺ -type emitter diffusion layer 13 is formed by heat treatment. Further, the polysilicon film 12 is etched by anisotropic dry etching to form an emitter electrode larger than the emitter diffusion window X, and then the BPSG film 10 is formed on this surface.
This heat treatment flattens the surface. Then, after forming each contact window, each metal wiring pattern 11 is formed.

[Problems to be Solved by the Invention]

However, in the bipolar semiconductor device manufactured by the conventional manufacturing method as shown in FIG. 5, the N ⁺ -type emitter diffusion layer 13 serving as the emitter region has the polysilicon film 9
Since it is formed by only one diffusion of arsenic from, the junction surface between the emitter region and the base region is linear when the depth of the emitter region is deeply about 0.1 to 0.2 μ, and The impurity concentration in the emitter region also changes monotonically. As a result, there are the following problems.

(1) In the conventional bipolar semiconductor device, when a reverse bias is applied between the emitter and the base, the electric field strength increases on the surface of the transistor and a so-called avalanche current (breakdown current) flows, so that hot carriers are generated at the junction. Occurs, and the hot carriers penetrate into the oxide film (SiO ₂ film 9) formed above the semiconductor interface where the emitter / base junction is formed to form a trap at the interface. Recombination current flows.
As a result, the current amplification factor of the bipolar semiconductor device is changed, so that there is a problem that reliability is deteriorated.

(2) In an ultra-high-speed bipolar semiconductor device, it is necessary to have a high f _T (collector cutoff frequency). However, when a large emitter current is passed in order to obtain a high f _T , the base width is widened and the effect ( (Kirk effect) occurs, and conversely causes a significant decrease in f _T.

In view of the above problems, an object of the present invention is to provide a method of manufacturing a bipolar semiconductor device having high reliability and having high-speed characteristics even when a large current is introduced.

[Means for solving the problem]

The method for manufacturing a bipolar semiconductor device according to claim 1, wherein a step of forming an insulating film on the first-conductivity-type single-crystal first semiconductor region serving as a collector, and the step of forming an insulating film in the first semiconductor region. A step of forming a second conductive type second semiconductor region to be a base; a step of forming an emitter opening in the insulating film; and a conductive film on the insulating film and the opening in which the opening is formed. Forming the first conductive type first emitter region at least directly under the emitter opening by introducing a first conductive type impurity into the conductive film; and the conductive film. The impurities of the first conductivity type through the second
Forming a second emitter region of the first conductivity type connected to the inside of the first emitter region by injecting into the semiconductor region of the first emitter region, and inverting the junction between the first emitter region and the base region. The impurity concentration of the first emitter region is set so that the directional current is controlled by the tunnel current.

A method for manufacturing a bipolar semiconductor device according to a second aspect is the method for manufacturing a bipolar semiconductor device according to the first aspect, wherein the bipolar semiconductor device is formed on the opening in the step of forming the first emitter region of the first conductivity type. As a method for introducing impurities of the first conductivity type into the conductor film, a second conductor film is formed on the conductor film formed on the opening, and the first conductor is applied to the second conductor film. It is characterized in that a method of introducing a type impurity and then diffusing the impurity into the conductor film formed on the opening is used.

The method for manufacturing a bipolar semiconductor device according to claim 3, wherein a step of forming a first insulating film on the first-conductivity-type single-crystal first semiconductor region serving as a collector, and the first semiconductor Forming a second conductive type second semiconductor region serving as a base in the region; forming a first opening for an emitter in the first insulating film; and a first opening for the emitter By introducing an impurity of the first conductivity type into the second semiconductor region through
Forming a first emitter region of the first conductivity type at least around the first opening for the emitter; and providing a second insulating film in contact with the inside of the periphery of the first opening, Forming a second opening for an emitter that is narrower than the first opening; and introducing an impurity of a first conductivity type through the second opening to connect a first conductivity type of the first conductivity type to the first emitter region. Forming a second emitter region, and setting an impurity concentration of the first emitter region so that a reverse current of a junction between the first emitter region and the base region is dominated by a tunnel current. Is characterized by.

The method for manufacturing a bipolar semiconductor device according to claim (4), wherein an insulating film is formed on the first conductivity type single crystalline first semiconductor region serving as a collector, and in the first semiconductor region. Forming a second conductive type second semiconductor region serving as a base; forming a first opening for an emitter in the insulating film; and an insulating film having the first opening for an emitter formed therein. And a step of forming a conductor film on the first opening, a step of introducing a first conductivity type impurity into the conductor film, and a step of introducing the impurity-containing conductor film inside the opening. Forming a second opening for an emitter that is narrower than the first opening by contacting and leaving the same; and impurities of the first conductivity type from the remaining conductor film in the second semiconductor region. First by spreading to
Forming a conductive type first emitter region, and forming a first conductive type second emitter region connected to the first emitter region by introducing a first conductive type impurity through the second opening. And the impurity concentration of the first emitter region is set so that the reverse current of the junction between the first emitter region and the base region is dominated by the tunnel current.

[Action]

The bipolar semiconductor device of the present invention has the following actions.

(1) The impurity concentration of the first emitter region in contact with the insulating film is set higher than the impurity concentration of the second emitter region, or the impurity concentration gradient is increased so that the emitter region and the base region in the vicinity Since the tunnel current is made to easily flow between the junction and the junction, the avalanche current that causes hot carriers can be suppressed.

(2) Immediately below the opening for the emitter of the insulating film, a wide first emitter region spreading outward from the opening, and the first emitter region
By forming the second emitter region having a narrow width immediately below the emitter region and forming the emitter region in a two-step structure, it is possible to suppress the base width widening effect (Kirk effect) at the time of driving a large current.

〔Example〕

1 (a), (b), (c), (d), and (e) are process cross-sectional views for explaining a method of manufacturing a bipolar semiconductor device according to the first embodiment of the present invention.

As shown in FIG. 1 (a), a P-type silicon single crystal substrate
An N ⁺ buried layer 21, a P ⁺ buried layer 22 as a channel stopper for electrically isolating elements from each other, and an N type epitaxial layer 23 having a desired film thickness and serving as an N type first semiconductor region 23.
After forming, the Si ₃ N ₄ film (not shown) used for the LOCOS method (local oxidation method) is deposited on this surface by the LP-CVD method (low pressure CVD method). Next, the Si ₃ N ₄ film in the element isolation region is removed,
By oxidizing this surface, the element isolation region 27 having a desired thickness is formed. Next, the remaining Si ₃ N ₄ film is also removed, and N-type impurity ion implantation and heat treatment diffusion are performed on this surface.
A collector wall diffusion layer 24 is formed, boron is further implanted into the base region, and heat treatment diffusion is performed to form a P-type active base diffusion layer 25 serving as a P-type second semiconductor region. Then, after depositing the SiO ₂ film 28 serving as the first insulating film on the entire surface (for example, a film thickness of 250 nm) by the LP-CVD method, a resist pattern 34 is formed on this surface.

Next, as shown in FIG. 1B, the resist pattern 34
After forming the opening 100 for the first emitter by etching the SiO ₂ film 28 by using, arsenic (for example, dose amount 1 × 10 ¹⁶ cm ^-2 ) is implanted into the ion and heat treatment is performed. By diffusion, an N ⁺⁺ emitter diffusion layer 30a (first emitter region) which becomes a part of the emitter is formed.

At this time, the N ⁺⁺ emitter diffusion layer 30a (first emitter region)
Is the opening for the first emitter formed in the SiO ₂ film 28.
It is determined by the width of 100, ion implantation energy, and heat treatment time.

Further, the shape of the N ⁺⁺ emitter diffusion layer 30a (first emitter region) has a wide width that extends outward from the opening 100 for the first emitter.

Next, as shown in FIG. 1 (c), the SiO ₂ film 28 and N ⁺⁺
The opening 1 for the first emitter is formed in a part of the emitter diffusion layer 30a.
A resist pattern 35 (second insulating film) to be the opening 200 for the second emitter having a pattern width narrower than 00 is formed. Then, arsenic (for example, a dose amount of 2 × 10 ¹⁵ cm ^-2 ) is ion-implanted into the opening 200, and is subjected to heat treatment diffusion to form an N ⁺ emitter diffusion layer 30b which becomes a main part of the emitter.
(Second emitter region) is formed.

The width of the N ⁺ emitter diffusion layer 30b (second emitter region) is determined by the width of the second emitter opening 200 formed by the register pattern 35, ion implantation energy, heat treatment time, and the like.

Therefore, N ⁺⁺ emitter diffusion layer 30a, N ⁺ emitter diffusion layer 3
Ion implantation energy, heat treatment time and opening 100 for the first emitter, opening 200 for the second emitter when forming 0b
By appropriately adjusting the width of the N ⁺ emitter diffusion layers 30a and 30b, the N ^{+ +} emitter diffusion layer 30a and the N ⁺ emitter diffusion layer 30b can have a two-stage structure.

This N ⁺ emitter diffusion layer 30b (second emitter region)
Is narrower than the N ⁺⁺ emitter diffusion layer 30a (first emitter region), has a deep junction depth with the lower layer, and has a low impurity concentration.

Next, as shown in FIG. 1D, a resist pattern 35
The first emitter opening 100 and SiO ₂
A polysilicon film 29 is formed on the surface of the film 28. And the first
A resist pattern 31 slightly larger than the width of the emitter opening 100 is formed.

Next, as shown in FIG. 1 (e), the polysilicon film 29 is etched by anisotropic dry etching using the resist pattern 31 to form an emitter extraction electrode 40.
Is formed, and a BPSG film 32 to be a protective film is further deposited on the entire surface, and then the surface is planarized by heat treatment. And this
After forming the contact windows for the emitter, collector, and base on the BPSG film 32, the metal wiring patterns 33 are formed.

The major characteristic of the bipolar semiconductor device manufactured in this way is that the N ⁺⁺ emitter diffusion layer 30a that becomes a part of the emitter is formed.
This means that (the emitter region in FIG. 1) and the N ⁺ emitter diffusion layer 30b (second emitter region), which is the main part of the emitter having a lower concentration than that, have a two-stage structure.

2 (a), (b), (c), (d), (e),
(F) is a process sectional view illustrating a method for manufacturing a bipolar semiconductor device according to a second embodiment of the present invention.

As shown in FIG. 2 (a), in the same manner as in the first embodiment, the N ⁺ buried layer 21, the P ⁺ buried layer 22, and the N-type first layer are formed on the P-type silicon single crystal substrate 20. N-type epitaxial layer 23 serving as a semiconductor region, element isolation region 27, collector wall diffusion layer 24, and P-type active base diffusion layer serving as a P-type second semiconductor region
Form 25. Then, SiO that becomes an insulating film is formed by the LP-CVD method.
_After depositing the ₂ film 28 on the entire surface (for example, a film thickness of 250 nm), a resist pattern 34 is formed on this surface.

Next, as shown in FIG. 2B, the resist pattern 34
The SiO ₂ film 28 is etched by using, to form the opening 100 for the emitter. Then, a polysilicon film 29a is formed on the surface of the opening 100 for the emitter and the SiO ₂ film 28 (for example, a film thickness of 50 nm).

Next, as shown in FIG. 2 (c), this polysilicon film
29a is transmitted and arsenic (eg dose 2 × 10 ¹⁵ c
m ⁻² ) is ion-implanted and a heat treatment diffusion is performed to form an N ⁺ emitter diffusion layer 30c (second emitter region) which becomes a main part of the emitter.

At this time, the N ⁺ emitter diffusion layer 30c (second emitter region)
Is determined by the inner width of the polysilicon film 29a and is narrower than the usual diffusion from the polysilicon film 29a.

Next, as shown in FIG. 2D, a polysilicon film 29a is formed.
A polysilicon film 29b serving as a second conductor film is formed on the surface of the film (for example, the film thickness is 280 nm). Then, arsenic (for example, a dose amount of 1 × 10 ¹⁶ cm ^-2 ) is ion-implanted on this surface, and a heat treatment diffusion is performed to form an N ⁺⁺ emitter diffusion layer 30d (first emitter region) which becomes a part of the emitter. .

The shape of the N ⁺⁺ emitter diffusion layer 30d (first emitter region) has a wide width that extends outward from the emitter opening 100.

The width of the N ⁺ emitter diffusion layer 30c (second emitter region) and the N ⁺⁺ emitter diffusion layer 30d (first emitter region) is
It is determined by the width of the opening 100 formed in the SiO ₂ film 28. This is because the N ⁺ emitter diffusion layer 30c (second emitter region) and the N ⁺⁺ emitter diffusion layer 30d (first emitter region) are formed on the opening 100 in the first polysilicon film 2
This is because it is formed by ion implantation through the 9a and the second polysilicon film 29b.

Therefore, N ⁺⁺ emitter diffusion layer 30d, N ⁺ emitter diffusion layer 3
The structure of the N ⁺⁺ emitter diffusion layer 30d and the N ⁺ emitter diffusion layer 30c can be adjusted in a self-aligned manner by adjusting the ion implantation energy, the heat treatment time, and the width of the emitter opening 100 when the 0c is formed. It can have a stepped structure.

Next, as shown in FIG. 2E, a resist pattern 31 is formed on the surface of the second polysilicon film 29b.

Finally, as shown in FIG. 2 (f), the polysilicon film 29 is etched by anisotropic dry etching using the resist pattern 31 to form an emitter extraction electrode 40, and a protective film. After depositing the BPSG film 32 formed on the entire surface, the surface is planarized by heat treatment. Then, after forming contact windows of the emitter, collector, and base on the BPSG film 32, each metal wiring pattern 33 is formed.

The big feature of the bipolar semiconductor device manufactured in this way is that the N ⁺⁺ emitter diffusion layer 30d which becomes a part of the emitter is formed.
This means that the (first emitter region) and the N ⁺ emitter diffusion layer 30c (second emitter region), which is the main part of the emitter having a lower concentration than this, have a two-stage structure.

3 (a), (b), (c), (d), (e),
(F) is a process sectional view illustrating a method for manufacturing a bipolar semiconductor device according to a third embodiment of the present invention.

As shown in FIG. 3A, in the same manner as in the first embodiment, the N ⁺ buried layer 21, the P ⁺ buried layer 22, and the N-type first layer are formed on the P-type silicon single crystal substrate 20. N-type epitaxial layer 23 serving as a semiconductor region, element isolation region 27, collector wall diffusion layer 24, and P-type active base diffusion layer serving as a P-type second semiconductor region
Form 25. Then, after depositing the SiO ₂ film 28a (for example, a film thickness of 250 nm) to be the first insulating film on the entire surface by the LP-CVD method, a resist pattern 34 is formed on this surface.

Next, as shown in FIG. 3B, the resist pattern 34
By etching the SiO ₂ film 28a using
After the opening 100 for the emitter is formed, arsenic (for example, a dose amount of 1 × 10 ¹⁶ cm ^-2 ) is ion-implanted into the opening 100 at a low energy of about 25 keV or less, and heat treatment diffusion is performed to form Forming an N ^{+ +} emitter diffusion layer 30e (first emitter region).

The shape of the N ⁺⁺ emitter diffusion layer 30e (first emitter region) has a wide width that extends outward from the opening 100 for the first emitter.

Next, as shown in FIG. 3 (c), a SiO ₂ film 28b (for example, a film thickness of 250 nm) serving as a _second insulating film is formed on the surface of the SiO ₂ film 28 ^a .

Next, as shown in FIG. 3 (d), the SiO ₂ film 28b, which is the second insulating film, is etched by 250 nm by anisotropic dry etching so that the SiO ₂ film 28a in the region adjacent to the SiO ₂ film 28a is etched. _{2 The} film 28b is left.

Thereby, the second emitter opening 200 having a width smaller than the width of the first emitter opening 100 can be formed in a self-aligned manner.

Then, arsenic (for example, a dose amount of 2 × 10 ¹⁵ cm ^-2 ) is ion-implanted into the opening 200 for the second emitter with high energy of about 50 keV or more, and N ⁺ emitter diffusion which becomes a main part of the emitter is formed by heat treatment diffusion. A layer 30f (second emitter region) is formed.

This N ⁺ emitter diffusion layer 30f (second emitter region)
Is narrower than the N ⁺⁺ emitter diffusion layer 30e (first emitter region), has a deep junction depth with the lower layer, and has a low impurity concentration.

Next, as shown in FIG. 3E, a polysilicon film 29 is formed on the entire surface, and a resist pattern 31 is formed on this surface.

Finally, as shown in FIG. 3 (f), the polysilicon film 29 is etched by anisotropic dry etching using the resist pattern 31 to form an emitter extraction electrode 40, and a protective film. After depositing the BPSG film 32 formed on the entire surface, the surface is planarized by heat treatment. Then, after forming contact windows of the emitter, collector, and base on the BPSG film 32, each metal wiring pattern 33 is formed.

The major characteristic of the bipolar semiconductor device manufactured in this way is that the N ⁺⁺ emitter diffusion layer 30e that becomes a part of the emitter is formed.
This means that the (first emitter region) and the N ⁺ emitter diffusion layer 30f (second emitter region), which is the main part of the emitter having a lower concentration than this, have a two-stage structure.

4 (a), (b), (c), (d), (e),
(F) is a process sectional view illustrating a method for manufacturing a bipolar semiconductor device according to a third embodiment of the present invention.

As shown in FIG. 4 (a), in the same manner as in the first embodiment, the N ⁺ buried layer 21, the P ⁺ buried layer 22, and the N-type first layer are formed on the P-type silicon single crystal substrate 20. N-type epitaxial layer 23 serving as a semiconductor region, element isolation region 27, collector wall diffusion layer 24, and P-type active base diffusion layer serving as a P-type second semiconductor region
Form 25. Then, SiO that becomes an insulating film is formed by the LP-CVD method.
After depositing the _two films 28 (for example, a film thickness of 250 nm) on the entire surface, a resist pattern 34 is formed on this surface.

Next, as shown in FIG. 4B, the resist pattern 34
The SiO ₂ film 28 is etched by using
After forming 100, the SiO ₂ film 28 and the opening 100 for the emitter are formed.
A polysilicon film 29c (for example, a film thickness of 330 nm) to be a conductor film is formed on the surface of the. Then, this polysilicon film 29c
Arsenic (for example, a dose amount of 1 × 10 ¹⁶ cm ^-2 ) is ion-implanted therein at a low energy of about 25 keV or less.

Next, as shown in FIG. 4 (c), a polysilicon film 29c is formed.
Is etched by an anisotropic dry etching method to leave a polysilicon film 29c having a high concentration of arsenic implanted on the side wall of the SiO ₂ film 28.

Then, by heat-treating the remaining polysilicon film 29c, the arsenic implanted in the polysilicon film 29c is diffused to form the N ⁺⁺ emitter diffusion layer 30g (first emitter region) which becomes a part of the emitter. Form. The shape of the N ⁺⁺ emitter diffusion layer 30g (first emitter region) is a ring shape, and the outer diameter of the N ⁺⁺ emitter diffusion layer 30g is wider than the opening 100 for the emitter.

Next, as shown in FIG. 4 (d), an opening 10 is formed for the emitter.
Arsenic (for example, a dose amount of 2 × 10 ¹⁵ cm ^-2 ) is ion-implanted at a high energy of about 50 keV or more into 0, and an N ⁺ emitter diffusion layer 30h (second portion) which becomes the main part of the emitter by heat treatment diffusion
Forming an emitter region).

This N ⁺ emitter diffusion layer 30h (second emitter region)
Has a deep junction depth with the layer below the N ⁺⁺ emitter diffusion layer 30g (first emitter region) and a low impurity concentration. Therefore, by adjusting the N ⁺ emitter diffusion layer 30h and the N ⁺⁺ emitter diffusion layer 30g ion implantation energy during formation of the leaving width of the thermal diffusion time and leaving polysilicon film 29C as appropriate, the N ⁺ emitter diffusion The structure of the layer 30h and the N ⁺⁺ emitter diffusion layer 30g can be made a two-stage structure in a self-aligned manner.

Next, as shown in FIG. 4E, a polysilicon film 29b is formed on the entire surface, and a resist pattern 31 is formed on this surface.

Finally, as shown in FIG. 4 (f), the polysilicon film 29b is etched by anisotropic dry etching using the resist pattern 31 to form an emitter extraction electrode 40, and a protective film. After depositing the BPSG film 32 formed on the entire surface, the surface is planarized by heat treatment. Then, after forming contact windows of the emitter, collector, and base on the BPSG film 32, each metal wiring pattern 33 is formed.

The characteristic of the bipolar semiconductor device manufactured in this way is that the N ⁺⁺ emitter diffusion layer 30g (first emitter region) having a high impurity concentration is formed as a part of the emitter and the low concentration N ⁺ emitter diffusion is formed as a main part of the emitter. It has a two-stage structure in which the layer 30h (second emitter region) is formed.

〔The invention's effect〕

The bipolar semiconductor device of the present invention has the following effects.

(1) The impurity concentration of the first emitter region in contact with the insulating film is set higher than the impurity concentration of the second emitter region, or the impurity concentration gradient is increased so that the emitter region and the base region in the vicinity It is possible to prevent hot carriers from invading the insulating film covering the upper surface between the junctions by facilitating the tunnel current to flow between the junctions with and. As a result, the current amplification factor of the bipolar semiconductor device can be stabilized and the reliability can be improved.

(2) Immediately below the opening for the emitter of the insulating film, a wide first emitter region spreading outward from the opening, and the first emitter region
By forming the second emitter region having a narrow width immediately below the emitter region and forming the emitter region in a two-step structure, it is possible to suppress the base width widening effect (Kirk effect) at the time of driving a large current. As a result, it is possible to maintain a high f _T (collector cutoff frequency) up to a larger current region, so that it is possible to manufacture a bipolar semiconductor device having higher speed than the conventional one.

[Brief description of drawings]

FIGS. 1 (a), (b), (c), (d), and (e) are process cross-sectional views for explaining the manufacturing method of the bipolar semiconductor device of the first embodiment of the present invention, and FIG. ), (B),
(C), (d), (e), (f) are process cross-sectional views for explaining the method for manufacturing the bipolar semiconductor device of the second embodiment of the present invention, and FIGS. 3 (a), (b), (). c), (d),
(E) and (f) are process cross-sectional views for explaining the method of manufacturing the bipolar semiconductor device according to the third embodiment of the present invention, and FIGS. 4 (a), (b), (c), (d), ( e) and (f) are process cross-sectional views for explaining a method for manufacturing a bipolar semiconductor device according to a fourth embodiment of the present invention, and FIG. 5 is a concept showing a bipolar transistor manufactured by a conventional method for manufacturing a bipolar semiconductor device. It is a figure. 23 ... N epitaxial layer (first semiconductor region), 25 ...
... P-type active base diffusion layer (second semiconductor region), 28 ...
SiO ₂ film (insulating film), 29a, 29b, 29c ... Polysilicon film (conductor film), 30a, 30d, 30e, 30g ... N ⁺⁺ emitter diffusion layer (first emitter region), 30b, 30c, 30f, 30h …… N ⁺ emitter diffusion layer (second emitter region), 100 …… Emitter opening

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Hori 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-52-25580 (JP, A)

Claims (4)

(57) [Claims] 1. A step of forming an insulating film on a first-conductivity-type single-crystal first semiconductor region serving as a collector, and a second-conductivity-type second substrate serving as a base in the first semiconductor region. A step of forming a semiconductor region, a step of forming an opening for an emitter in the insulating film, a step of forming a conductive film on the insulating film and the opening in which the opening is formed, Forming a first conductivity type first emitter region at least directly under the emitter opening by introducing a first conductivity type impurity into the first conductive type impurity, and removing the first conductivity type impurity through the conductor film. Forming a second emitter region of the first conductivity type that is connected to the inside of the first emitter region by injecting into the second semiconductor region, wherein the first emitter region and the base region are formed. Reverse junction current tunnels As governed by the flow method of bipolar semiconductor device and sets the impurity concentration of the first emitter region. 2. A method of introducing impurities of the first conductivity type into a conductor film formed on the opening in the step of forming the first emitter region of the first conductivity type A second conductor film is formed on the body film, impurities of the first conductivity type are introduced into the second conductor film, and then the impurities are diffused into the conductor film formed on the opening. The method for manufacturing a bipolar semiconductor device according to claim 1, wherein the method is used. 3. A step of forming a first insulating film on a first-conductivity-type single-crystal first semiconductor region serving as a collector, and a second-conductivity type serving as a base in the first semiconductor region. Forming a second semiconductor region, forming a first opening for an emitter in the first insulating film, and adding an impurity of a first conductivity type through the first opening for an emitter. Forming a first conductivity type first emitter region at least around the first opening for the emitter by introducing the first emitter region into the second semiconductor region; and contacting the inside of the periphery of the first opening. Forming a second opening for an emitter that is narrower than the first opening by providing a second insulating film; and introducing a first conductivity type impurity through the second opening, Second of first conductivity type connected to one emitter region And a step of forming a miter region, wherein the impurity concentration of the first emitter region is set so that a reverse current of a junction between the first emitter region and the base region is dominated by a tunnel current. Method for manufacturing bipolar semiconductor device. 4. A step of forming an insulating film on a first-conductivity-type single-crystalline first semiconductor region that serves as a collector, and a second-conductivity-type second substrate that serves as a base in the first semiconductor region. A step of forming a semiconductor region, a step of forming a first opening for an emitter in the insulating film, an insulating film having the first opening for an emitter formed thereon, and a conductor on the first opening. A step of forming a film; a step of introducing impurities of the first conductivity type into the conductor film; and a step of leaving the conductor film in which the impurities are introduced in contact with the inside of the opening. Forming a second opening for an emitter that is narrower than the opening; and diffusing the impurity of the first conductivity type into the second semiconductor region from the remaining conductive film, Forming a first emitter region; Forming a second emitter region of the first conductivity type connected to the first emitter region by introducing an impurity of the first conductivity type through the opening, and forming a second emitter region of the first conductivity type and the base region. A method of manufacturing a bipolar semiconductor device, wherein the impurity concentration of the first emitter region is set so that the reverse current of the junction is dominated by the tunnel current.