JP2536199B2 - Counter device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter device such as a timer / counter equipped with an information processing device, which can be controlled by software and has a load register.

[Prior Art] In the prior art, the value handled by the read / write operation of the reload register is the value of the reload register itself, and the value handled by the read / write operation of the counter is the value of the counter itself.

FIG. 3 is a block diagram showing a conventional timer / counter with a reload register. In the figure, 1 is a reload register, 2 is a counter, 3 is a switch for controlling start / stop of the counter 2 by controlling transmission of an input clock Φ to the counter 2, 4 is data connected to a processor or the like not shown. It's a bus.

In the above configuration, when the reload register 1 is read / written by software, data is transferred between the data bus 4 and the reload register 1 (this operation is indicated by an arrow 5 in the figure). When the counter 2 is read / written by software, data is transferred between the data bus 4 and the counter 2 (this operation is indicated by an arrow 6 in the figure). Counter 2 is the terminal count value (the final count value determined by the hardware configuration of the counter,
Normally, when all bits "0" or all bits "1" are reached), the content of the reload register 1 is loaded into the counter 2 (this operation is shown by an arrow 7 in the figure).

[Problems to be Solved by the Invention] By the way, for important operations in the application of the timer / counter,
There is "correction of counter value during operation". In this case, the operation of delaying the generation of the terminal count value by n clocks is performed. In the above-described timer / counter with a reload register according to the prior art, the value itself of the counter 2 needs to be rewritten, so that the “corrected counter value” needs to be calculated by software using the correction required value n. "Corrected counter value" is However, the "S / W overhead" cannot be predicted in detail because of the hardware constraints of the processor that executes the software (such as instruction execution time and bus availability). Therefore, there is a problem in that an accurate “corrected counter value” cannot be calculated, and thus an accurate “correction of counter value during operation”, which is essential for high-speed real-time control or the like, cannot be realized.

FIG. 4 illustrates the above contents. The counter value is read at timing A, the corrected counter value is calculated during period C, and the result is written to the counter at timing B. The period C is the interval from timing A to timing B, but this cannot be predicted accurately, which causes a problem.

The present invention has been made to solve the above problems, and an object thereof is to obtain a counter value that can be accurately corrected during operation.

[Means for Solving the Problem] According to the present invention, an adding means for adding a value written by software and the current value of the counter, and an output of the adding means during the operation of the counter in association with the start and stop of the counter. It is provided with a switching means for writing a value to the counter and writing the value written by the software to the counter as it is while the counter is stopped.

Further, during the counter operation, the period from writing by software to writing the output value of the adding means in the counter is determined only by the operating time of the adding means.

[Operation] In the present invention, the value handled in the writing operation to the counter during operation is not the value of the counter itself but the “correction required value” that is truly necessary for the correction of the counter, and the current value of the counter is read by software. ~ Without adding the correction calculation procedure, the addition means provided in the apparatus adds the correction required value written by the software, and the result is loaded into the counter via the switching means.
That is, it is written. Further, the value handled by the writing operation to the counter while stopped is the counter value itself, and the value written by the software is written to the counter as it is through the switching means. Therefore, the initial value of the counter can be easily set. it can.

In addition, the period from the writing of the correction required value to the counter during operation to the correction of the counter value is determined only by the operation overhead of the adding means, that is, the operation time, so it is extremely short and is not subject to hardware restrictions of the processor. .

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a timer with a reload register according to an embodiment.
It is a block diagram showing a counter, the same as the conventional example of FIG.
Alternatively, the same reference numerals are used for corresponding portions and the description thereof will be omitted. In the figure, 11 is a data bus 4 by software.
A counter buffer for temporarily storing a value written via the counter, an output of the counter buffer 11, that is, a value written by software and an output of the counter 2,
That is, an adder circuit (adder means) for adding and outputting the current value of the counter 2, 13 is a switch when the switch 3 is closed,
That is, the switch is controlled so as to be closed when the counter 2 is operating, and allows the addition result of the adder circuit 12 to be written in the counter 2. Reference numeral 14 is a switch 3 when the switch 3 is open, that is, the counter 2 is stopped. In this case, the switches 13 and 14 are controlled so as to be closed so that the value written by software can be directly written in the counter 2, and the switches 13 and 14 constitute the switching means of the main subject.

 Next, the operation will be described.

Read reload register 1 by software /
When writing is performed, data is transferred between the data bus 4 and the reload register 1 as in the conventional case (this operation is indicated by an arrow 5 in the figure). When the counter 2 reaches the terminal count value, the contents of the reload register 1 are loaded into the counter 2 as in the conventional case (this operation is indicated by the arrow 7 in the figure).

On the other hand, the writing operation to the counter 2 by software differs depending on whether the counter 2 is operating or stopped. The value handled in the writing operation to the counter 2 during operation is a correction required value. At this time, since the switch 3 is closed, the switch 13 is closed and the switch 14 is open. Here, when writing to the counter 2 by software,
Data is transferred from the data bus 4 to the counter buffer 11 (this operation is indicated by the arrow 15 in the figure). When the data is written in the counter buffer 11, the adder circuit 12
Adds the content of the counter buffer 11, that is, the correction required value of the counter 2, and the content of the counter 2 at that time, that is, the current value of the counter 2, and switches the result.
Write back to counter 2 via 13. The operation of writing back the value to the counter 2 occurs only once when the writing to the counter 2 is performed by software. Further, the value handled by the writing operation to the counter 2 which is stopped is the counter value itself. At this time, since the switch 3 is open, the switch 13 is open and the switch 14 is closed. Therefore, the counter 2 which is stopped for the initial value setting
When writing is performed by software, data is transferred from the data bus 4 to the counter 2 via the switch 14, and the value of the counter itself is written. When the counter 2 is read by software, the data is transferred from the counter 2 to the data bus 4. The value handled by the reading operation of the counter 2 is the value of the counter 2 itself (indicated by the arrow 16 in the figure).

FIG. 2 shows a write operation by software to the counter 2 during operation. When the correction required value is written in the counter 2 operating at the timing B, the counter value is corrected after the period C. Here, the period C is for the adder circuit 12
Since it is determined only by the operation overhead of, the uncertainty is extremely short and the uncertainty of the processor hardware limits the uncertainty. Further, at this time, the processor does not need to read the counter value through software and perform correction calculation, so that the load is significantly reduced.

[Effects of the Invention] As described above, according to the present invention, the addition means for adding the value written by software and the current value of the counter, and the above addition during the operation of the counter in conjunction with the start and stop of the counter. Since the output ratio of the means is written in the counter and the value written by the software is written in the counter as it is while the counter is stopped, the counter can be corrected accurately while operating, and the correction calculation by the software can be performed. Is not required, the load on the processor can be reduced. In addition, it is easy to set the initial value to the stopped counter.

Further, during the counter operation, the period from the writing by the software to the writing of the output value of the adding means to the counter is determined only by the operating time of the adding means, so it is extremely short and is not restricted by the hardware of the processor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a timer / counter with a reload register according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the embodiment of the present invention, and FIG. 3 is a reload register according to the prior art. FIG. 4 is a configuration diagram showing a built-in timer / counter, and FIG. 4 is a timing diagram for explaining the operation according to the conventional technique. 1 is a reload register, 2 is a counter, 3 is a switch,
4 is a data bus, 11 is a counter buffer, 12 is an adder circuit (adding means), and 13 and 14 are switches (switching means). In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A counter device having a counter readable and writable by software, comprising: an addition means for adding a value written by software and a current value of the counter; A counter device comprising: a switching means for writing the output value of the adding means to the counter during operation and for writing the value written by the software to the counter while the counter is stopped. 2. The counter device according to claim 1, wherein during the counter operation, the period from the writing by the software to the writing of the output value of the adding means in the counter is determined only by the operating time of the adding means. .