JP2538779B2 - Speed conversion circuit - Google Patents

Description

DETAILED DESCRIPTION [Outline] When a terrestrial transmission line having different signal transmission speeds and a speed conversion circuit for converting the signal transmission speed are provided between satellite transmission lines, output from the speed conversion circuit For effective use of the bandwidth in the satellite transmission line for transmitting the signal to be transmitted, the terrestrial transmission line for transmitting the signal including multiple lines in one frame and the frame of the same width unlike this transmission speed Of the same number of lines, the data is written using the write clock corresponding to the transmission speed of the terrestrial transmission line and the read clock corresponding to the transmission speed of the satellite transmission line. In a speed conversion circuit for transmission speed conversion, such as having a memory 8 for reading data using, the speed changes in accordance with line setting information indicating the number of lines in use on the terrestrial transmission line. And a read clock generation means 9 for generating a read clock synchronized with the write clock, and the data from the memory in which the data from the terrestrial transmission line has been written is read by the read clock from the read clock generation means and the satellite system is read. Send it to the transmission line.

[Industrial applications]

The present invention relates to an improvement in a speed conversion circuit, for example, a speed conversion circuit used in a satellite communication terminal device.

Generally, a signal transmitted from a terrestrial transmission line at a transmission rate required by the transmission line is converted into a transmission rate required by a satellite transmission line in a speed conversion circuit and then transmitted.
In this case, the ratio of the transmission rate on the terrestrial transmission line to the transmission rate on the satellite transmission line is constant.

On the other hand, in recent years, digital technology has been actively introduced into various communication systems, and in particular, a modulator / demodulator with a variable transmission speed is being put to practical use.

Therefore, the characteristics of such a modulator / demodulator should be fully exhibited.
Moreover, in order to effectively use the band, a variable speed speed conversion circuit is required instead of the conventional constant ratio speed conversion circuit.
This is because the lower the transmission rate, the narrower the frequency band used.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 shows an example of format of terrestrial signals. Hereinafter, with reference to FIG.
The operation of the figure will be described.

First, as shown in FIG. 6, as the terrestrial signal write data, 24 lines of the same frame sync pulse and 8 bit voice data as the reference signal a are inserted in the time interval of 125 μs (8 KHz). , Write clock (hereinafter abbreviated as W-CKL) is (8 × 24 + 1) × 8KHz = 154
It becomes 4KHz.

Then, when this voice data is input to the speed conversion circuit having the line setting function shown in FIG. 5, it is converted into parallel by the serial / parallel conversion circuit 1 and then the redundant memory 2 is controlled under the control of the write controller 5. The voice data corresponding to the line is sequentially written to the address corresponding to the line number on one side of the, but when the data is written to all of the one side, the dual memory side switching is performed, and the line corresponding to the line corresponding address on the other side is sequentially turned on again. Voice data is written.

That is, since the write controller 5 has a write address counter (not shown) inside and specifies the write address corresponding to the voice data of the line, when it is judged from the counter value that one side has been fully written. Sends a surface switching signal to the memory bank controller 4. Therefore, the memory bank controller 4 performs surface switching of the dual memory and switching between the write address and the read address.

Next, since the writing of the redundant memory is completed and the signal is read from the surface on which the voice data has already been written, the phase-locked oscillator 7 synchronizes with W-CLK and the transmission speed of the satellite system line is increased. A corresponding read clock (hereinafter abbreviated as R-CLK) is generated.

This is the oscillation of the phase-locked oscillator 7 so that the R-CLK output from the phase-locked oscillator 7 is synchronized with the reference signal (frame synchronization signal) a of about 8 KHz obtained by dividing the R-CLK by the read controller 6. Obtained by controlling the frequency.

In this case, the frequency division ratio between the reference signal b and R-CLK is fixed. That is, the signal transmission rate of the terrestrial system is only converted to the signal transmission rate determined by the satellite system, regardless of the number of lines used.

On the other hand, of the 24 lines (CH) shown in Fig. 6 from the outside,
For example, when the line setting information indicating that CH1, CH5, CH9 ... Is in use is input to the read controller 6, the voice data of each line is sequentially written in the address position of the memory corresponding to the line number.

The controller 6 reads the voice data corresponding to the line number written in the address corresponding to the line number from the written side of the duplicated memory and outputs it as serial data via the parallel / serial converter 3.

Therefore, only the serial data of the line number designated by the line setting information is continuously extracted.

[Problems to be solved by the invention]

However, since the phase-locked oscillator 7 is designed to synchronize with a single frequency, R
-It is impossible to change the frequency of CLK. Therefore, there is a problem that the effective use of the band is not sufficiently performed.

[Means for solving problems]

According to the present invention, the above problems include a terrestrial transmission line for transmitting a signal including a plurality of lines in one frame as shown in FIG. 1 and the same number of lines in a frame of the same width, which is different from the transmission speed. Data is written using a write clock that corresponds to the transmission speed of the terrestrial transmission path, and is read between the satellite transmission path that transmits signals and the read clock that corresponds to the transmission speed of the satellite transmission path. In the speed conversion circuit for converting the transmission speed such as having the memory 8, the speed changes according to the line setting information indicating the number of lines in use of the terrestrial transmission line, and the read clock synchronized with the write clock is generated. The read clock generating means 9 for reading data from the memory in which the data from the terrestrial transmission line is written is read from the read clock generating means. It is solved by the speed converting circuit, characterized in that sending to the satellite system transmission line and read by a clock.

[Action]

According to the present invention, the audio data is sequentially written in the memory means 8 by using the write clock, and the audio data of the line in use from the unwritten portion of the memory means is generated by the read clock generation means 9 having a variable speed. In addition, the read clock whose speed changes according to the number of lines used is used. That is, in the speed conversion circuit, the read clock of the audio data from the memory is changed according to the number of lines used, so the transmission speed of the audio data read at such a clock becomes small, and therefore the used frequency band is reduced. The width of the frequency band becomes small, and the frequency band can be efficiently used.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 4 is a block diagram of the variable frequency phase locked oscillator and speed setting controller in the figure, and FIG. 4 is an operation explanatory diagram of FIG. still,
The same reference numerals denote the same objects throughout the drawings.

Further, the serial / parallel converter 81, the duplicated memory 82, the parallel / serial converter 83, the memory bank controller 84, the write controller 85 and the read controller 86 are components of the memory means 8 and the speed setting controller. 91 and the variable frequency phase locked oscillator 92 are components of the variable speed read clock generating means 9.

The number of lines in use is 12, and the operation of FIG. 2 will be described below with reference to FIGS.

First, the audio data of terrestrial signals shown in FIG.
After being parallelized by the parallel converter 81, under the control of the write controller 85, the memory is continuously written to the address position corresponding to the line number on one side of the duplicated memory 82, and when the data is written to one side fully, the memory The bank controller 84 switches the surfaces of the duplicated memory, and the data is subsequently written to another surface.

On the other hand, the line setting information indicating the number of lines used is added to the speed setting controller 91 and the read controller 86 in order to read the voice data. The former operation will be described with reference to FIG.

That is, the speed setting controller 91 indicates that the number of used lines n = 12 by the line setting information from the outside, so the buffer register 91
We store that value in 1, but the value of n may change at any time.

Then, the (8n + 1) frequency divider (for example, composed of a counter) 912 to which n = 12 is added operates as a 97 frequency divider, but it is started by the start signal and the line setting information is set in the read controller. R- generated based on
The frequency of CLK is divided, and the signal b is output as the divided output.

A part of the signal b is also used as a load signal of the (8n + 1) frequency divider and is used for setting the frequency division number.

The variable frequency phase-locked oscillator 92 performs the same operation as the conventional phase-locked oscillator, and the phase comparator 921 is arranged so that the signal b is synchronized with the reference signal a (for example, 8 KHz) corresponding to the frame signal of the terrestrial system signal. Then, the oscillation frequency of the variable frequency oscillator 923 is controlled using the loop filter 922. As a result, an R-CLK of 776 KHz synchronized with W-CLK can be obtained.

Therefore, a counter (not shown) in the read controller 86 counts this R-CLK, and when the address corresponding to this count value coincides with the address of the 12 lines in use, the R-CLK is controlled by the memory bank. Add to dual memory via device 84.

Therefore, as shown in the satellite system signal in Fig. 4, the line in use from one side where the dual memory is not written is used.
The data of CH1, CH5, ... Is read continuously, converted in series by the parallel / serial converter 83, and output.

 Therefore, the transmission frequency band is effectively used.

〔The invention's effect〕

As described in detail above, according to the present invention, the speed conversion circuit changes the read clock of the audio data from the memory means in accordance with the number of used lines, so that the number of used lines becomes small. Since the number of read clocks is also small, the transmission speed of the audio data read and sent at such clocks is slowed down, and the used frequency bandwidth is narrowed, so that the frequency band can be efficiently used.

[Brief description of drawings]

1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of a speed setting controller and a variable frequency phase locked oscillator in FIG. 2, and FIG. Is an operation explanatory view of FIG. 2, FIG. 5 is a block diagram of a conventional example, and FIG. 6 shows an example of a format for ground system detection. In the figure, 8 is a memory means, and 9 is a variable speed read clock generating means.

Claims (1)

(57) [Claims] 1. A terrestrial transmission line for transmitting a signal including a plurality of lines in one frame, and a satellite type transmission line for transmitting a signal including the same number of lines in a frame of the same width, which is different from the transmission speed. In between, there is a transmission rate conversion such as a memory 8 having a memory 8 for writing data using a write clock corresponding to the transmission rate of the terrestrial transmission line and for reading data using a read clock corresponding to the transmission rate of the satellite transmission line. In the speed conversion circuit for, the speed is changed corresponding to the line setting information indicating the number of lines in use in the terrestrial transmission line, and the read clock generation means 9 for generating a read clock synchronized with the write clock is provided, The data from the memory in which the data from the terrestrial transmission line has been written is read by the read clock from the read clock generation means. Speed conversion circuit, characterized in that sending the star system transmission line.