JP2538866B2 - Digital phase-locked oscillator - Google Patents

Description

The present invention relates to a digital phase locked oscillator applied to a network synchronizer for supplying a reference clock for establishing network synchronization in a digital communication network, for example. Is.

"Prior Art" In a digital synchronous network, it is necessary to supply a reference clock in the network to each device and perform communication with the reference clock.
The reference clock is supplied by a network synchronizer installed in each station, and frequency synchronization between the network synchronizers is established by an independent synchronization system, a mutual synchronization system or a slave synchronization system.
In the slave synchronization system which is usually used at present, the reference clock is distributed in the network, and after the network synchronizer synchronizes the phase with the reference clock, the network synchronizer supplies the reference clock to each device in the station. In the early network synchronizers, an output synchronized with the reference clock input by the analog phase synchronization circuit was obtained. After that, even if the input reference clock is interrupted, a digital phase lock circuit is used so that the value immediately before the output frequency of the phase lock circuit is stopped can be held.

Here, the phase variation characteristic of the phase locked loop will be obtained by focusing on the power spectrum density. The power spectrum density of the input reference clock is S _i (f) (f: detuning frequency), and the power spectrum density of the output when the phase locked loop is not synchronized is S _s (f),
Transfer function of transfer synchronization circuit is H (p) (p: Laplace variable)
Then, the power spectrum density S _o (f) of the phase locked loop output during synchronization is S _o (f) = S _i (f) | H (p) | ² + S _s (f) | 1-H (p )
| ² (1) (Reference [1] Kihara, Makino, Clock phase characteristics in stationary state of weakly coupled subsynchronous networks, IEICE, Vol.
J68-B, No.1., 1985). In formula (1), | 1-H (p) |
^{Since 2} shows a high-pass characteristic, the low-pass component of S _s (f) is suppressed. The bending frequency ω _c of the high-pass characteristic is determined by the loop gain k in the case of the transfer function of the primary loop in the digital phase lock circuit.

In the digital phase locked loop circuit as shown in FIG. 3, the input reference clock 11 and the digitally controlled oscillator 12 are used.
The output 13 of is compared in phase with a digital phase comparator 14,
The phase comparison result is supplied to the control circuit 15, and the control circuit 15
Provides the oscillator 12 with control data 16 whose output 13 is synchronized with the input reference clock 11.

In the case of such a digital type phase locked loop circuit, the loop gain k is obtained from the characteristics of the digital phase comparator 14, the control circuit 15 and the digitally controlled oscillator 12. Loop gain k is However, y _c : frequency control step [Hz] of digitally controlled oscillator 12 / center frequency [Hz] T _p [sec]: phase difference detection accuracy of digital phase comparator 14 (references [2] and [3]).

[2] M. Makino, et.al .: “Network Synchronization
System ", Rev. of ECL, Vol.31, No.1,1983 [3] EAMunter:" Synchronized Clock for DMS-1 "
00 Family ", IEEE Trans Comm., Vol.con-28, No.8,1980 Normally y _c = 5 × 10 ^-11 , T _p = 0.25 μs is set and k
Is 2 × 10 ^-4 [1 / sec]. Here, when the digitally controlled oscillator 12 is in the power spectral density when it is not synchronized, it is almost a day cycle. Consider the frequency change due to the frequency-temperature characteristic of the oscillator 12 of FIG. In the case of ω _c = 7.3 × 10 ^-5 , this value is almost equal to k (= 2 × 10 ^-4 ) obtained from the equation (2), and S _s (f) due to the high-pass characteristic at the time of synchronization (at the time of asynchronous) Suppression of output power spectral density) cannot be expected. Therefore, there is a drawback that the frequency change due to the frequency temperature characteristic of the oscillator 12 appears in the output of the phase locked loop even during the synchronization.

Also, by increasing the loop gain k, the oscillator 12
Although it is possible to suppress the frequency change due to the frequency temperature characteristic of, the frequency control step / center frequency y _c is increased because there is a limit to lowering the phase difference detection accuracy T _p in the equation (2). When y _c is increased, the control of the oscillator 12 becomes rough, and when the input reference clock is cut off and the self-running state occurs, the initial frequency deviation becomes large as shown in FIG.

In Japanese Patent Laid-Open No. 59-39126 "Phase synchronization circuit", V
By constructing an oscillator with a free-running counter instead of CO, digitally counting the phase difference, taking the time average, and feeding back the time average of the phase difference to the count value of the free-running counter. , The oscillation frequency of the free-running counter is changed to change the phase to perform the phase synchronization, and the average period is short during the synchronization pull-in operation (synchronization area), and the number is rapidly increased to n (4 in the specific example). Synchronous pull-in is performed, and the average period is long except for the synchronous pull-in operation.
(16 pieces), which slowly responds and stabilizes is proposed.

This publication does not describe the case where the input becomes abnormal, for example, the synchronization pattern is disconnected, but even if such an abnormal state occurs, the synchronization control is continued,
The oscillation state of the oscillator is greatly deviated.

An object of the present invention is to coarsen the frequency control step of a digitally controlled oscillator in order to increase the loop gain of a phase locked loop, but a digital phase locked loop having a small initial frequency deviation in a free-running state which occurs when an input reference clock error (disconnection) occurs. It is to provide an oscillator.

"Means for Solving Problems" This invention applies when the input reference clock is normal (at the time of synchronization).
By switching the frequency control step for the digitally controlled oscillator in the phase locked loop circuit depending on the abnormal situation (asynchronous, free running), the output frequency control step is coarsely set at the time of synchronization to increase the loop gain. , Output frequency control step is reduced to the limit at the time of asynchronous self-running,
The main feature is to minimize the initial frequency deviation immediately after self-running.

The present invention differs from the prior art in that the initial frequency deviation immediately after free running does not depend on the output frequency control step at the time of synchronization and can be freely set.

For this reason, in the present invention, first and second control data setting means are provided, and the output phase difference data of the digital phase comparator are input to these first and second control data setting means, respectively, and the phase difference data is output according to the phase difference data. The first control data setting means outputs control data that changes at an integer multiple of the minimum frequency control step, and the second control data setting means outputs control data that changes at the minimum frequency control step according to the phase difference data. When the abnormality of the input reference clock is detected by the abnormality detection circuit, the control data for the oscillator is set to the first value.
The output control data of the control data setting means is switched to the output control data of the second control data setting means, and at least the updating of the output control data of the second control data setting means is stopped.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. In the present invention, the control step for the oscillator 12 is switched depending on whether the input reference clock is abnormal or normal. Therefore, the input reference clock 11 is also supplied to the abnormality detection circuit 18. Digital phase comparator 14
Is supplied to the control circuit 15 through the input stop switch 19. The comparison result of the digital phase comparator 14 input through the input stop switch 19 is supplied to the phase difference data averaging circuits 21 and 22 in the control circuit 15. The outputs of these averaging circuits 21 and 22 are control data setting circuit 23 and
Supplied to 24. Each control data from the control data setting circuits 23, 24 is switched by the changeover switch 25, and one of them is supplied to the digitally controlled oscillator 12 as control data. Input stop switch 19 by the output of the abnormality detection circuit 18
And the switching switch 25 is controlled.

In this configuration, when the input reference clock 11 is normal, the output of the digital phase comparator 14 is averaged by the phase difference data averaging circuit 21, and the oscillator control data setting circuit is responsive to the processed output. 23 provides control data to the digitally controlled oscillator 12.

The phase difference detection accuracy T _p of the digital phase comparator 14 is set to 250 ηs.
If the frequency control step (minimum control step) y _c of ec and the digitally controlled oscillator 12 is 5 × 10 ^-11 , the loop gain k is 2 × 10 ^-4 . The following equation is used to determine how much the frequency change due to the temperature change in the digitally controlled oscillator 12 is suppressed during synchronization (see reference [2]).

However, y _o : Frequency change during synchronization [Hz] / Center frequency of digitally controlled oscillator [Hz] y _a : Frequency change during asynchronous [Hz] / Center frequency of digitally controlled oscillator [Hz] ω _c : Temperature change Angular frequency [rad / sec] that corresponds to the cycle of temperature change cycle is 1 day, the frequency change at the time of non-synchronization is 5 × 10 ^-10, and the frequency change at the time of synchronization is 5 × 10 ^-11
In order to suppress to below, it is necessary to set the loop gain k to 7.3 × 10 ⁻⁴ or more. A loop gain k = 7.3 × 10 ^-4 can be realized by setting the frequency control step y _c of the digitally controlled oscillator 12 to 1.8 × 10 ^-10 .

Therefore, the oscillator control data setting circuit 23 sets the digitally controlled oscillator 12 to the minimum control step. In reality, the control amount is an integral multiple of the minimum control step, so the control is performed with a roughness of four times.

At the same time, the phase difference data averaged by the averaging circuit 22 is input to the oscillator control data setting circuit 24, and a control value corresponding to the minimum control step of the digitally controlled oscillator 12 is obtained.

When the input reference clock 11 is determined to be abnormal by the abnormality detection circuit 18, the input stop switch 19 is turned off by the determination output, the control data of the control circuit 15 is not updated, and the oscillator control data setting is made. It is held by the circuit 24, and the switching switch 25 is controlled to switch to the oscillator control data setting circuit 24. The output of the switching switch 25 causes the digitally controlled oscillator 12 to self-run with a frequency deviation corresponding to the minimum control step. FIG. 2 shows the characteristic of the frequency deviation when shifting from the synchronous state to the free-running state.

The coarse step-like step shown by the thick line 31 is the minimum control step in the synchronous amount, and the fine step shown by the thin line 32 is the asynchronous step. The oscillator 12 is controlled by the averaging circuit 21 and the control data setting circuit 23 during synchronization, but at the same time, the averaging circuit 22 and the control data setting circuit 24 also process the signal from the phase comparator 14 and hold this level. (The level corresponding to the reference clock input frequency in FIG. 2) is set, and when an abnormality occurs, the vehicle runs at the step frequency closest to this level. When this circuit returns to the normal state, when the abnormality detection circuit 18 detects that the circuit is normal, the switch 19 is turned on, and the switching switch 25 is both controlled to be controlled by the coarse step (thick line 31). .

As described above, in the present invention, unlike the conventional configuration, the frequency control step at the time of synchronization can be freely set without being influenced by the frequency control step at the time of synchronization.

[Advantages of the Invention] As described above, according to the present invention, the frequency control step at the time of synchronization and the frequency control step at the time of self-propelling can be set so as to be suitable for each. The frequency control step determined from the optimum value during self-running has the advantage that it can be set to the minimum step because it reduces the frequency deviation immediately after self-running.

When the synchronizing circuit of the present invention is used for reproducing the reference clock in the digital synchronizing network, it operates as a high-precision phase-locked oscillator with high loop gain during synchronization, and when the input reference clock is abnormal and self-running. , It operates as a highly stable fixed oscillator with little frequency deviation, and can stably supply the reference clock in the digital synchronous network.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a digital phase-locked oscillator according to the present invention, FIG. 2 is a diagram showing an example of changes in the output frequency deviation of the phase-locked oscillator according to the present invention, and FIG. 3 is a diagram of a conventional phase-locked oscillator. FIG. 4 is a block diagram showing the configuration, and FIG. 4 is a diagram showing a variation example of the output frequency deviation of the conventional phase locked oscillator. 11: Input reference clock, 12: Digitally controlled oscillator, 1
3: Oscillator output, 14: Digital phase comparator, 15: Control circuit, 16: Control data, 18: Input reference clock input abnormality detection circuit, 19: Input stop switch, 21, 22: Phase difference data averaging circuit , 23, 24: oscillator control data setting circuit, 25: oscillator control data switching switch.

Claims (1)

(57) [Claims] 1. A digitally controlled oscillator, a digital phase comparator for detecting a phase difference between an oscillation output of the digitally controlled oscillator and an input reference clock, and output phase difference data of the digital phase comparator are inputted. First control data setting means for outputting control data which changes according to the phase difference data at a frequency control step N times (N is a natural number of 2 or more) the minimum frequency control step of the digitally controlled oscillator; The output phase difference data of the phase comparator is input, the second control data setting means for outputting the control data that changes in the minimum frequency control step according to the phase difference data, and the input reference clock are input, and an abnormality thereof is input. And an abnormality detection circuit for detecting the error, and the abnormality detection output of the abnormality detection circuit controls the second control data setting means. Means for stopping the updating of the data, and control data for the digital control type oscillator from the output control data of the first control data setting means to the output control data of the second control data setting means by the abnormality detection output of the abnormality detecting circuit. A digital phase-locked oscillator comprising switching means for switching to.