JP2540201B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and a semiconductor memory device capable of surely relieving even if there is a defective portion extending between blocks of word lines / bit lines to improve data reliability. For the purpose of providing, there are N (N
Is a natural number), and a memory cell array having a matrix configuration composed of a set of lines, and a spare cell capable of replacing the defective row or column when at least one of the rows or columns of the memory cell array is defective, A defective address storage unit that stores an address of a set to which a defective row or column line belongs, an operation unit that calculates an address of a set adjacent to the defective line to the set that belongs to the defective line, and an external address And an address comparison circuit for comparing the defective address and the address from the arithmetic unit, respectively.

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that employs a redundant configuration for memory cells.

As the density and capacity of memory LSIs increase, it is becoming increasingly difficult to expect that the entire chip is defect-free. Therefore, even in semiconductor memories, for example, SRAMs, elements using a redundancy configuration (redundancy) incorporating a defect repair circuit from 16 Kbits have begun to appear. The adoption of redundant configurations is becoming more common in SRAMs of 64K bits or more.

That is, it becomes difficult to keep the production yield of the memory chip at a practical level or higher as the storage capacity increases.
In order to relieve the defective memory cell, which is the main cause of the decrease in yield, a method of arranging a spare memory cell capable of replacing the defective memory cell in a circuit in advance in a chip is used. Such a memory configuration is called a redundant configuration. Recently, not only SRAM but also DRAM, EPROM, mask ROM are required to have memory cell redundancy.

[Conventional technology]

A semiconductor memory that adopts a conventional redundant configuration, such as SRAM
As such, the one shown in FIG. 4 is known. In the figure, reference numeral 1 is a memory cell, and a large number of cells are arranged at intersections of word lines and bit lines. Two spare cells 2 and 3 are provided on the side of the memory cell 1 along the direction of the word line and the bit line, and the unit for repairing the defective cell of the memory cell 1 is one row along the word line and the bit line. , One line (memory cell cell array)
In order to replace this, the spare cells 2 and 3 are normally
Several spare lines are available. The replacement of a line (hereinafter referred to as a defective line) 1x including a defective cell F with a spare line is usually performed by registering the defective address (defective address) of the memory cell 1 in the defective address storage unit 4 that selects the spare line. Done.

Both the word line of the memory cell 1 and the word line of the spare cell 2 are connected to the same row decoder 5, and similarly for the bit line, the memory cell 1 and the spare cell 3 are connected to the same column decoder 6. When an address signal is input to the address buffer 7 from the outside, this address signal is also sent to the address comparison circuit 8, and the address comparison circuit 8 compares the external address with a defective address stored (registered) in advance. When the two match, a match signal is output to the control circuit 9. Based on this coincidence signal, the control circuit 9 outputs a decode signal for exchanging the defective line 1x with the line of the spare cell 2 or the spare cell 3 to the row decoder 5 and the column decoder 6. As a result, the defective word line or bit line of the memory cell 1 is replaced with the line of the spare cells 2 and 3, and the data of the replaced line is output to the outside via the input / output amplifier 10. If there is no defective portion (defective cell F), the external address is decoded as usual to read the data in the memory cell 1.

[Problems to be Solved by the Invention]

However, in such a conventional semiconductor memory device, the defective address stored in the defective address storage unit 4 designates a word line or a bit line in block units (specifically, a pair), and therefore the fifth address is used. As shown in the figure, since the least significant bit of the address configuration bits is not stored, if the defective portion extends over two blocks, the defect cannot be relieved and the reliability of the data decreases. There was a problem.

That is, as shown in FIG. 6, when there are word lines WD0 to WD3 ... Of the memory cell 1, there is a defective portion F on the word lines WD0 and WD1 forming one block BLi (for example, due to adhesion of dust or the like). If there is a short circuit), since it is a single block BLi, it can be repaired with a defective address that does not include the least significant bit stored in the defective address storage unit 4, but FIG. As shown in the figure, when the defective portion F extends over two blocks BL _i and BL _{i + 1} , a defective address in block units (see FIG. 7A).
A defective address that does not include the least significant bit as shown in (1) cannot be relieved. Further, as shown in FIG. 8A, the defective address stored in the defective address storage unit 4 does not include the lowest 2 bits, and as shown in FIG. Similarly, even when the defective portion F extends over two blocks BL _i and BL _{i + 1} in the case where it is designated as “one set” (one block), it cannot be relieved.

Conventionally, it has been desired that the repair by the redundant configuration of the memory chip be performed on a block-by-block basis to maintain a practical level to some extent. However, recently, a high manufacturing yield level is required. Therefore, it is necessary to remedy defects between blocks.
Note that the above-mentioned problem is exactly the same for the bit line.

On the other hand, as shown in FIG. 9, for example, as a measure for repairing defects extending between blocks, there has been considered. In FIG. 9, a second defective address storage unit 21 for storing the least significant bit of the defective address is provided in addition to the defective address storage unit 4, and the subsequent information based on the storage information of the second defective address storage unit 21 is provided. Redundant processing is performed. Therefore, all the bits including the least significant bit are stored in the defective address as shown in FIG. 10, and the word line or bit line in the memory cell 1 can be specified one by one. Bad address storage unit 4 and second
The output of the defective address storage unit 21 is input to the address comparison circuit 22, and the address comparison circuit 22 outputs a match signal to the control circuit 23 when all bits of the external address and the defective address match. The control circuit 23 sets the defective line 1x to the spare cell 2 or the spare cell 3 independently based on the coincidence signal.
A decode signal for exchanging one line is output to the row decoder 5 and the column decoder 6.

In the above structure, as shown in FIG. 11, the defective portion F is formed so as to extend over the word lines WD1 and W2 of the memory cell 1.
If there is, two addresses of WD1 and WD2 are stored in the defective address storage unit 4 and the second defective address storage unit 21 including all bits. Then, when the address comparison circuit 22 detects that the external address matches the address of these word lines WD1 and WD2, the match signal outputs the match signal.
The lines of the word lines WD1 and WD2 output to 23 are replaced with the spare cells 2 to rescue the data.

Here, in the configuration example of FIG. 4, when the defective portion F spans two blocks BL _i and BL _{i + 1} as shown in FIG. 7, since the least significant bit of the defective address is not stored, Although it cannot be relieved, in the configuration example of FIG. 9, all bits of the defective address are stored even if there is a short circuit across the two blocks BL _i and BL _{i + 1} as shown in FIG. Therefore, the word lines WD1 and WD2 are specified one by one and replaced with the line of the spare cell 2.

However, in the configuration of FIG. 9, BL _i and BL _{i + 1}
A defective portion F extending over two blocks (that is, two sets) can be repaired by designating word lines WD1 and WD2. However, as shown in FIG. 12, BL _i , BL _{i + 1} and BL _{i + 2} , BL _{i + 3} , it is not possible to remedy a defective portion F that spans four sets of blocks. To repair such a defective portion, it is necessary to specify all four pairs of blocks BL _{i to} BL _{i + 3} , which is difficult and has not been solved. there were.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of surely relieving even if there is a defective portion extending between blocks of word lines / bit lines and improving the reliability of data.

[Means for solving the problem]

The semiconductor memory device according to the present invention achieves the above object,
There are N (N) lines forming a plurality of row lines or column lines.
Is a natural number), and a memory cell array having a matrix configuration composed of a set of lines, and a spare cell capable of replacing the defective row or column when at least one of the rows or columns of the memory cell array is defective, A defective address storage unit that stores an address of a set to which a defective row or column line belongs, an operation unit that calculates an address of a set adjacent to the defective line to the set that belongs to the defective line, and an external address And an address comparison circuit for comparing the defective address and the address from the arithmetic unit, respectively.

[Action]

In the present invention, when there is a defect in two adjacent sets of lines, another set of defective lines is repaired based on one set of defective address information.

Therefore, even if there is a defective portion extending over a plurality of blocks in a row or a column of the memory cell, a specific defective line of the memory cell is surely specified and the defective portion is surely relieved.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 3 are diagrams showing a first embodiment of a semiconductor memory device according to the present invention, and particularly an example in which the present invention is applied to an SRAM. FIG. 1 is an overall configuration diagram of the SRAM, and in describing the present embodiment, the same components as those in the conventional example shown in FIG.

In FIG. 1, the present embodiment is different from the conventional example in that an adder 31 is provided in addition to the defective address storage unit 4 similar to the conventional one, and the adder 31 stores the address stored in the defective address storage unit 4. + [1] and output to the address comparison circuit 22.
Therefore, when either the address of the defective address storage unit 4 or the address + [1] by the adder 31 coincides with the external address, a control signal is generated and the defective line 1x becomes the spare cell 2 or 3. Will be exchanged. Here, the configuration of the adder 31 corresponds to a calculation unit.

In the above configuration, the defective address storage unit 4 stores all the bits of the defective address as shown in FIG. 2 (a), thereby designating one bit as one set (block), and the blocks BL _i and BL _i are designated. _When repairing the defective portion F extending over ₊₁ , the block BL _i stored in the defective address storage unit 4 is stored.
And the address of the adjacent block BL _{i + 1} which is + [1] by the adder 31 are compared with the external address in the address comparison circuit 22, and when the addresses match, a control signal is generated from the control circuit 23. Then, the defective line of the memory cell is replaced with the corresponding line of the spare cell 2 or 3. In this manner, by adding + [1] to the address stored in the defective address storage unit 4 by the adder 31, it is possible to relieve the defect extending over two adjacent blocks. Further, as shown in FIG. 2B, the defective address storage unit 4 stores the defective addresses by excluding the least significant bit, thereby designating two lines as one set (one block). a) Similarly, the address of the block BL _i stored in the defective address storage unit 4 and the adder 31 add +
[1] Both of the addresses of the adjacent blocks BL _{i + 1} which have been [1] are compared with the external address, the corresponding line of the spare cell 2 or 3 is replaced, and two sets of blocks BL _i and BL _{i + 1} are replaced.
It is possible to relieve the defective portion F extending over the Further, as shown in FIG. 2 (c), in the defective address storage unit 4, four bits are designated as one set (one block) by storing the defective address except for the least significant two bits.
Similar to FIGS. (A) and (b), two sets of blocks BL _i and BL _{i + 1}
It is possible to relieve the defective portion F extending over the That is, by designating one set of one to a plurality of sets in the defective address storage unit 4 and designating another set by the adder 31, not only the defect in the block but also the defect between the blocks is recognized. I can rescue you. The addition of the adder 31 is not + [1], but +
It may be [n] (n is an integer).

On the other hand, in order to remedy the case shown in FIG. 12 mentioned as a problem of the conventional example, as shown in FIG. 3, the defective address storage unit 4 and the adder 31 form a set of four, and this is set to + If two sets of combinations obtained by adding only [1] are designated, defect relief can be performed. For convenience of explanation, the addresses of each set are separately shown in the storage unit 1 and the storage unit 2 (corresponding to the internal configuration of the defective address storage unit 4) and the adder attached to each.

As described above, in the present embodiment, when one block is designated, the other blocks can be automatically designated, and in particular, even a defect extending over four blocks can be reliably repaired.

In the above embodiment, the defect repair of the word line is taken as an example, but it goes without saying that the same effect can be obtained even when the bit line is replaced with a spare cell.

Further, the application of the present invention is not limited to SRAM, but can be applied to other semiconductor memories, such as DRAM, EPROM, and mask ROM, which have a redundant configuration. However, for the mask ROM and the like, it is necessary to separate the spare cell from the memory cell for decoding.

〔The invention's effect〕

According to the present invention, even if there is a defective portion extending between blocks of a word line / bit line of a memory cell, it can be replaced with a spare cell without fail, and the reliability of data can be improved. it can.

[Brief description of drawings]

1 to 3 are diagrams showing an embodiment of a semiconductor memory device according to the present invention. FIG. 1 is a configuration diagram thereof, FIG. 2 is a diagram for explaining defective relief of the word line, and FIG. FIG. 4 is a diagram for explaining another defect relief of the word line, FIGS. 4 to 8 are diagrams showing a conventional SRAM, FIG. 4 is a configuration diagram thereof, and FIG. 5 is a diagram showing memory bits of the defective address, FIG. 6 is a diagram for explaining a defective portion of a word line in the one block, FIG. 7 is a diagram for explaining a defective portion of the word line, and FIG. 8 is a diagram for explaining another defective portion of the word line. 9 to 12 are diagrams showing another conventional SRAM, FIG. 9 is a configuration diagram thereof, FIG. 10 is a diagram showing storage bits of a defective address thereof, and FIG. 11 is a diagram showing the two blocks thereof. FIG. 12 is a diagram for explaining a defective portion of the word line, and FIG. 12 shows another portion of the word line extending over the two blocks. It is a figure explaining a defective part. 1 ... Memory cell, 2,3 ... Spare cell, 4 ... Defective address storage section, 5 ... Row decoder, 6 ... Column decoder, 7 ... Address buffer, 8 ... Address comparison circuit, 10 ... ON Output amplifier, 21 ... Second defective address storage unit, 22 ... Address comparison circuit, 23 ... Control circuit, 31 ... Adder.

Claims (1)

(57) [Claims] 1. A memory cell array having a matrix structure in which a line forming a plurality of row lines or column lines is composed of a set of N lines (N is a natural number), and among the rows or columns of the memory cell array. A spare cell that can be replaced with a defective row or column when at least one is defective, a defective address storage unit that stores an address of a set to which the defective row or column line belongs, and based on the defective address, A semiconductor having an operation unit for operating an address of a set adjacent to a set to which the defective line belongs, an external address, and an address comparison circuit for respectively comparing the defective address and the address from the operation unit. Storage device.