JP2540912B2 - Bipolar transistor and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a method for manufacturing the bipolar transistor, and more particularly to an emitter region and a base formed in a self-aligned manner using a polycrystalline silicon film. A bipolar transistor having a region and a method for manufacturing the bipolar transistor.

[Conventional technology]

In order to realize a high-speed transistor by reducing the base resistance and its junction capacitance, a method of forming a graft base in a self-aligned manner using a polycrystalline silicon film of a base electrode as a diffusion source has been conventionally known.

FIG. 7 is a sectional view of a semiconductor chip for explaining a conventional method of manufacturing a bipolar transistor of this type.

In this conventional example, first, an insulating region 5 made of SiO _{2 of} a semiconductor substrate having an n-type epitaxial layer 3 ′ deposited on a p-type semiconductor base plate 1 ′ made of silicon having an n ⁺ type buried layer 2 ′ on the surface thereof. An insulating film 5 ″, a polycrystalline silicon film 6 ′ containing a p-type impurity, and an insulating film 18 are sequentially formed in the element formation region isolated by ′, and then a window is opened in the insulating film 18.
Then, using the insulating film 18 as a mask, the polycrystalline silicon film 6'and the insulating film 5 "are etched to open a wider window. Next, the polycrystalline silicon film 6'a containing a p-type impurity is etched.
Is formed under the eaves of the insulating film 18 to form a polycrystalline silicon film 6 '.
A graft base region 11 'is formed on the surface of the epitaxial layer 3'in a self-aligning manner using a as a diffusion source. Subsequently, an insulating film 17 'for separating the emitter / base electrode is formed, and p-type impurities are introduced into the surface of the opening of the epitaxial layer 3'by ion implantation or the like to form a base region 14'.
Then, polycrystalline silicon 15 'is grown and an n-type impurity is introduced by an ion implantation method to form an emitter region 16'.

[Problems to be Solved by the Invention] In the conventional bipolar transistor manufacturing method described above, the base resistance and the collector junction capacitance can be reduced by forming the graft base region in a self-aligned manner. Since the polycrystalline silicon film 6'a for forming the base region 11 'in a self-aligned manner is formed outside the opening provided in the insulating film 18 for etching, the area of the base region including the graft base is formed by lithography. Since it is wider than the smallest hole that is technically possible, there is a limit in forming a base region having a smaller base resistance to reduce the junction capacitance and improve the high frequency characteristics such as the cutoff frequency.

Further, when removing the polycrystalline silicon grown on the bottom of the window where the emitter is to be formed, it is necessary to control the selectivity with respect to the underlying epitaxial layer.

[Means for solving the problem]

According to a first aspect of the present invention, there is provided a method of manufacturing a bipolar transistor, which comprises a first insulating film and a second conductive type impurity on a first conductive type semiconductor layer on a surface of an element formation region which is insulated from the surroundings. 1 polycrystalline silicon film, oxidation resistant second
Sequentially depositing an insulating film and a third insulating film, and exposing the surface of the first conductivity type semiconductor layer on the surface of the element forming region by opening a first window by anisotropic etching. A step of forming a first side wall made of an insulating film made of the same material as the second insulating film on a side surface of the first window; and a bottom surface of the first window is oxidized to form a fourth insulating film. A step of selectively removing the first sidewall and the second insulating film in the vicinity thereof to form an eroded portion in the second insulating film, and a step of containing a second conductivity type impurity. No. 2 polycrystalline silicon film is formed, the eroded portion is backfilled, the first conductive type semiconductor layer is contacted with the first side wall trace, and then the second conductive type impurity is introduced from the contact part to graft base. Forming a region, and forming a second polysilicon film on the side surface of the first window. A step of forming a second side wall made of a fifth insulating film, a step of etching an exposed surface of the second polycrystalline silicon film to form a recess on the outside of the second side wall, and a sixth step The method is characterized by including a step of filling the recess with an insulating film and a step of introducing a second conductivity type impurity from the bottom of the first window to form a base region.

A bipolar transistor according to a second aspect of the present invention is a bipolar transistor having a base region of an emitter region formed in a self-aligned manner, one end of which is terminated by a polycrystalline silicon extraction electrode and the other end of which is formed. Both ends of which have a base region terminating in an element isolation region of the insulating film, and one end of which is terminated at a constant distance from the base extraction electrode by an insulating film provided on a part of the surface of the base extraction electrode, The other end has an emission region which ends in an element isolation region.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (i) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of a method for manufacturing a bipolar transistor according to the first invention of the present invention.

First, as shown in FIG. 1 (a), p made of silicon is used.
⁺ Type buried layer 2 on the semiconductor type semiconductor substrate 1 and 0.5 to 1.0 on it
A semiconductor substrate having an n-type epitaxial layer 3 deposited by μm is insulated and separated by an insulating region 5a made of SiO ₂ and a pn junction to partition an element formation region, and further a first insulating film 5 made of SiO ₂ and p The first polycrystalline silicon film 6 containing a type impurity is sequentially deposited, and the polycrystalline silicon film 6 is selectively removed so as to remain in a predetermined region including the element formation region. next,
A silicon nitride film, which is an oxidation resistant film, is deposited as the second insulating film 7 and a silicon oxide film is sequentially deposited as the third insulating film 8. The third insulating film 8 in the emitter formation region, the second insulating film 7, The first polycrystalline silicon 6 and the first insulating film 5 are sequentially and selectively anisotropically etched to open the first window 9.

Next, as shown in FIG. 1B, the same film as the second insulating film 7, that is, a silicon nitride film is deposited to a thickness of 1500 to 3000 Å, and reactive ion etching (hereinafter referred to as RIE)
The first side wall 9a is formed by etching except the vertical side wall. Such RIE technology is known,
For example, it is disclosed in US Pat. No. 4,234,362.

Next, as shown in FIG. 1C, the exposed surface of the n-type epitaxial layer 3 is oxidized by 1000 to 2000 Å. At this time, the side surface of the first window 9 in the emitter formation region is protected by the first side wall 9a, and the first polycrystalline silicon film 6 inside is protected.
It serves to prevent the oxidation of. Then, the silicon nitride film is etched with hot phosphoric acid to remove the first side wall 9a. At this time, the second insulating film 7 in the vicinity is 2000 to 3000 Å
Side etching is performed to form the eroded portion 11.

Next, as shown in FIG. 1D, the second polycrystalline silicon film 12 is grown to a thickness of 2000 to 4000 Å thicker than the first side wall 9a. Although it is more preferable for forming the graft base that the second polycrystalline silicon film 12 is added with a p-type impurity, it is not always an essential requirement. First
P-type impurities are present in the polycrystalline silicon layer of
Via the second polycrystalline silicon film 12, the graft base region
It is possible to form 13 by heat treatment at 900 ° C.

Next, as shown in FIG. 1 (e), an insulating film, preferably a silicon nitride film or an alumina film, which is an oxidation resistant film, is grown by 1000 to 2000Å, and the sidewall leaving technique of RIE is used to Second side wall on the side surface of the opening of the emitter formation region
Forming 14

Next, as shown in FIG. 1F, the exposed second polycrystalline silicon film 12 is etched using RIE. The etching amount is 30% to 100% overetching, but the second polycrystalline silicon film 12 outside the second side wall 14 has a depth of 2000 to 5000 Å with respect to the second side wall 14. Allow it to be scooped to form a depression. Then, a recess 15 is formed on the exposed surface of the second polycrystalline silicon film 12 at a temperature of 900 ° C. by growing a silicon oxide film of about 500 Å.

After that, the active base region 16 is formed by ion implantation.

Next, as shown in FIG. 1 (g), an insulating film, in particular, a sixth insulating film 17 made of the same silicon nitride film or alumina film as the second sidewall 14 is formed by the low pressure CVD method with good step coverage. grow up. At this time, the thickness of the second polycrystalline silicon film 12 is at least ½ of 2000 to 4000 Å, and the recess 15 is backfilled.

Next, as shown in FIG. 1 (h), the sixth insulating film 17 is RI
Anisotropically etched by E, and subsequently the fourth insulating film 10
Similarly anisotropically etch to expose active base region 16.

Next, as shown in FIG. 1 (i), a third polycrystalline silicon film 19 is grown, and, for example, arsenic ion implantation and 900.degree.
A heat treatment at 950 ° C diffuses arsenic to form an emitter. Then, the third polycrystalline silicon film 19 is selectively etched to form a collector contact opening 20 and a base contact opening 21.

Although not shown in the following steps, normal electrode formation such as electrode wiring formation using an aluminum film or the like is performed.

In FIG. 1 (d), after the second polycrystalline silicon film 12 is grown, heat treatment is performed to form the graft base 13 instead of forming the second polycrystalline silicon film 12. By doping boron by ion implantation or diffusion, the resistance of the graft base 13 is reduced, and a second polycrystalline silicon film serving as a base extraction electrode is formed.
You may make it 12 low resistance.

FIG. 2 is a plan view of a bipolar transistor using the first invention of the present invention. 1 (a) to 1 (i) described above are sectional views taken along the line AA 'in FIG. In addition,
The BB 'section of FIG. 2 has the same structure as the AA' section. Bipolar obtained by using the first invention
The structure of the transistor has a collector junction surface under the emitter region 220, the insulating film 223 for separating the emitter / base electrode and the region of the base contact portion 213 of FIG. The collector junction capacitance is very small.

On the other hand, the overlapping region 221 of the first insulating film 5 and the first polycrystalline silicon film substantially forms a parasitic MOS capacitor. That is, as shown in FIG. 1 (i), there is a first gap between the n-type epitaxial layer 3 and the first polycrystalline silicon film 6.
The first insulating film 5 is composed of a relatively thin silicon oxide film having a thickness of about 1000 to 2000 Å. Therefore, until the first insulating film 5 contacts a thick insulating film for element isolation,
It forms a fairly large parasitic MOS capacitance.

The structure of the bipolar transistor obtained by using the above-described first invention suppresses the collector junction capacitance to a very small value, while the n-type epitaxial layer 3 described above is used.
A parasitic MOS capacitance exists between the (collector region) and the first polycrystalline silicon film 6 (base extraction electrode).
In particular, as shown in FIG. 2, the overlapping region of the first insulating film and the first polycrystalline silicon film surrounding the collector junction (that is, the parasitic MOS capacitance region of the base extraction electrode and the collector region). The parasitic MOS capacitance in the case of having at least is about the same size as the junction capacitance, although it depends on the size of the element. In particular, as the size of the device is reduced and the collector junction capacitance is reduced, this parasitic
It is clear that the proportion occupied by MOS capacity will increase, which is a major obstacle to speeding up and reducing power consumption.

Next, a second invention of the present invention will be described with reference to the drawings. FIG. 3 is a plan view of the second bipolar transistor of the present invention. 4 (a) and 4 (b)
3A is a sectional view taken along the line AA ′ and FIG. 3B ′ of FIG. 3, respectively.

The bipolar transistor of the second invention of the present invention comprises:
It is composed of a minimum necessary collector region and a minimum necessary base region so that the parasitic MOS capacitances of the collector region and the base extraction electrode can be significantly reduced. That is, A- in the plan view of FIG.
The A'section has the same structure as that obtained from the first invention, but the BB 'section has both the emitter-base junction and the collector-base junction as shown in FIG. 4 (b). It terminates on the side surface of the thick insulating film 45a. As a result, the area difference between the emitter and the base is suppressed to the size of the electrode part (graft / base region) for extracting the base, and the extracting part is limited to one direction. The margin between the lead-out portion of the base and the element isolation region is suppressed, and the limit is limited to one direction.

Therefore, the electrode lead-out structure and the emitter-base lead-out electrode relationship are different from those of the semiconductor device of the first embodiment having the base lead-out electrode around the emitter and the collector region around the base.

5 (a) to 5 (i) are views for explaining a method of manufacturing the bipolar transistor according to the second aspect of the invention.
FIG. 6 is a cross-sectional view of a semiconductor chip in which the cross section BB ′ in the drawing is arranged in the order of steps.

First, as shown in FIG. 5 (a), an n ⁺ type indentation layer 52 is formed on a p-type semiconductor base plate 51 made of silicon, and 0.5 n is formed thereon.
A semiconductor base plate having an n-type epitaxial layer 53 deposited to 1.0 μm is insulated and separated from an insulating region 55a made of SiO _{2 by a} pn junction to partition an element formation region, and further a first insulating film 55 made of SiO ₂ And a first polycrystalline silicon film 56 containing p-type impurities are sequentially deposited, a silicon nitride film which is an oxidation resistant film is formed as the second insulating film 57, and a silicon oxide film is formed as the third insulating film 58. The third insulating film 58, the second insulating film 57, the first polycrystalline silicon film 56, and the first insulating film 55 in the emitter formation region are sequentially sequentially anisotropically etched to form a first insulating film. Open the window 59 of. The n-type epitaxial layer 53 and the insulating region 55a surrounding it are both exposed at the bottom of the opening.

Next, as shown in FIG. 5B, the same film as the second insulating film 57, that is, a silicon nitride film is deposited to a thickness of 1500 to 3000 Å, and is vertically etched by reactive ion etching (hereinafter referred to as RIE). First by etching except the side wall
To form a side wall 59a.

Next, as shown in FIG. 5 (c), the exposed surface of the n-type epitaxial layer 53 is oxidized by 1000 to 2000 liters. At this time, the side surface of the first window 59 in the emitter formation region is protected by the first side wall 59a, and the first polycrystalline silicon film 5 inside is protected.
6 serves to prevent oxidation. Then, the silicon nitride film is etched with hot phosphoric acid to remove the first side wall 59a. At this time, the second insulating film 57 in the vicinity thereof is 2000 to 3000.
Å It is better to form the eroded portion 511 by side etching.

Next, as shown in FIG. 5D, a second polycrystalline silicon film 512 is grown to a thickness of 2000 to 4000 Å thicker than the first side wall 59a.

Next, as shown in FIG. 5 (e), an insulating film, preferably a silicon nitride film which is an oxidation resistant film, an alumina film, or the like is grown to 1000 to 2000 Å, and the aforementioned RIE sidewall leaving technique is used. Then, the second side wall 514 is formed on the side surface of the emitter type region opening.

Next, as shown in FIG. 5F, the exposed second polycrystalline silicon film 512 is etched by using RIE. The etching amount is 30% to 100% overetching, but the second polycrystalline silicon film 512 outside the second side wall 514 is dug into the second side wall 514 to a depth of 2000 to 5000Å. So that a recess is formed. After that, the surface of the exposed second polycrystalline silicon film 512 is formed into a recess 515 at a temperature of 900 ° C. by forming a SiO ₂ film of about 500 Å. After that, an active base region 516 is formed by ion implantation.

Next, as shown in FIG. 5 (g), an insulating film, in particular, a sixth insulating film 517 made of the same silicon nitride film or alumina film as the second sidewall 514 is formed by the low pressure CVD method with good step coverage. grow up. The film thickness at this time is the second polycrystalline silicon film 51.
The thickness of at least 1/2 of the film thickness 2000 to 4000Å of 2 is grown to fill back the recess 515.

Next, as shown in FIG. 5 (h), the sixth insulating film 517 is
Anisotropically etched by IE, and subsequently the fourth insulating film 51.
Similarly, 0 is anisotropically etched to expose the active base region 516.

Next, as shown in FIG. 5 (i), a third polycrystalline silicon film 519 is grown, and, for example, arsenic ion implantation and 900.degree.
Arsenic is diffused by heat treatment at 950 ° C. to form the emitter 520. After that, the third polycrystalline silicon film 519 is selectively etched.

The subsequent steps are contact opening and electrode formation, but they are not shown because they can be formed by a normal method.

FIGS. 6 (a) to 6 (h) are sectional views of a semiconductor chip in which the section taken along the line BB 'in FIG. 3 is arranged in the order of steps for explaining another embodiment of the second invention of the present invention. is there. In particular, the difference in the manufacturing method will be described in detail. Incidentally, FIG. 6 (i) is a sectional view corresponding to FIG. 6 (b) of the AA 'section in FIG. First, as shown in FIG.
After the nitride film of the insulating film 64 is grown to 1000 to 2000 Å, polycrystalline silicon (especially one to which p-type impurities are added) is grown. After that, leaving the polycrystalline silicon and the nitride film in the element region, the trenches in the element isolation region and the oxide film are backfilled and planarized to expose the polycrystalline silicon surface, and the surface is thin (100 ~ After forming a 200Å) oxide film (not shown), a polycrystalline silicon 66, a nitride film 67, and an oxide film 68 are sequentially grown.

After that, the respective films 66, 67, 68 are sequentially anisotropically removed by RIE to expose a part of the polycrystalline silicon again. The selectivity between the first polycrystalline silicon 66 and the lower polycrystalline silicon is not a problem because there is a thin oxide film on the polycrystalline silicon film.
Next, with this polycrystalline silicon film as a mask, the insulating region 65a is formed.
Is etched by RIE. Then, the exposed polycrystalline silicon is anisotropically etched to open the first window 69. Next, using the silicon nitride film 64, which is the seventh insulating film, as a mask, the SiO ₂ 65, which is the first insulating film in the first window, is removed by 1000 to 20.
Etching is performed to expose a part of the periphery of the n-type epitaxial layer 63 which is a device forming region. Next, using the silicon nitride film 64 as a mask, P-type impurities are introduced into the exposed portion of the n-type epitaxial layer 63 by diffusion, and the p-type compensation base 624.
To form.

Next, as shown in FIG. 6C, the same film as the second insulating film 67 and the seventh insulating film 64, that is, a silicon nitride film is deposited to a thickness of 1500 to 3000 Å and the above-mentioned using RIE. So first
To form the side wall 69a. At this time, the seventh insulating film 64 is not left on the element formation region.

The following is realized by performing exactly the same steps as in the first embodiment. Here, since the cross-sectional shape is slightly different, a cross-sectional view of each step is shown, but the description is omitted. According to this embodiment, in the sectional view after the formation of the emitter shown in FIG. 6 (h), the compensating base 624 is formed around the emitter region 620 in contact with the element isolation insulating film 65a to prevent the emitter-collector short circuit. This serves to significantly improve the yield of transistors.

〔The invention's effect〕

As described above, according to the present invention, both the base region and the emitter region can be formed in a self-aligned manner with the first window by forming the side wall inside the first window opened by the lithography technique. The areas of the base region and the emitter region can be made smaller than those limited by the lithography technique, and the junction capacitance and the base resistance of the bipolar transistor can be reduced and the high frequency characteristics such as the cutoff frequency can be improved.

In addition, by significantly reducing the parasitic MOS capacitance between the collector region and the base extraction electrode, the collector-base capacitance can be suppressed to a minimum, thus making it possible to speed up the transistor and reduce power consumption. It was For example, in the case where transistors having the same emitter region 20 are formed by using the same design rule, the area difference between the overlapping regions of the first insulating film and the first polycrystalline silicon film that should form the parasitic MOS capacitance Focusing on, the area is reduced to about 1/3. In other words, the parasitic MOS capacitance can be reduced to almost 1/3.

Also, parasitic MOS capacitance and junction (collector base)
Since the capacity ratio of is about 1 to 1, the total collector-base capacity can be reduced to about 2/3.

Furthermore, adding a compensating base has the effect of reducing the base resistance as well as greatly improving the yield of the transistor, and as a result, the capacitance between the collector and the base is reduced without increasing the base resistance. It was possible to achieve a significant reduction.

[Brief description of drawings]

1 (a) to 1 (i) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the first invention of the present invention, and FIG. 2 is a sectional view of the first embodiment of the present invention. FIG. 3 is a plan view of a bipolar transistor manufactured by using the invention, FIG. 3 is a plan view of a bipolar transistor of the second invention of the present invention, and FIGS. 4 (a) and 4 (b) are respectively a third view. A in the figure
A ′ cross section, BB ′ cross section, and FIGS. 5 (a) to 5 (i) are shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention. 6 (a) to 6 (h) are cross-sectional views of the semiconductor chip, which are cross-sectional views of the semiconductor chip in the order of steps for explaining a manufacturing method of another embodiment of the second aspect of the present invention. FIG. 6 (i) is FIG. 6 (b).
And FIG. 7 is a sectional view of a semiconductor chip for explaining a conventional example. 1,1 ′, 51 …… p type semiconductor substrate, 2,2 ′, 52 …… n ⁺ type buried layer, 3,3 ′, 53 …… n type epitaxial layer, 5,45 …… first
Insulation film, 5 ', 5a, 55a, 65a ... Insulation area, 5' ...
Insulating film, 6,56,66 ... First polycrystalline silicon film, 6 '...
… Polycrystalline silicon film, 7,57,67 …… Second insulating film, 8,58,
68 ... third insulating film, 9,59,69 ... first window, 9a, 59a ...
... first side wall, 10,510 ... fourth insulating film, 11,511 ... eroded portion, 11 '... graft base region, 12,512 ... second polycrystalline silicon insulating film, 13 ... graft base region, 1
4,514 …… Second side wall, 14 ′ …… Base region, 15,515…
… Dent, 16,516 …… Base region, 16 ′ …… Emitter region, 17,517 …… Sixth insulating film, 17 ′, 18 …… Insulating film, 19,
419,519 …… Third polycrystalline silicon film, 20 …… Collector contact opening, 21 …… Base contact opening, 64…
… Seventh insulating film, 220,320,420,520 …… Emitter region, 2
13,313,413 ... Base contact portion (graft base region), 221,321 ... Overlap region of first insulating film and first polycrystalline silicon film, 222,322 ... Overlap region of insulating region and first polycrystalline silicon film, 223,323 ...... Emitter film for separating the emitter base electrode, 614 …… P-type compensation base.

Claims (3)

(57) [Claims] 1. A bipolar transistor having a self-aligned emitter region and base region, one end of which is terminated by a polycrystalline silicon extraction electrode and the other end of which is an element isolation region of an insulating film. An insulating film having a terminating base region, one end of which is separated from the base lead electrode by a certain distance by an insulating film provided on a part of the surface of the base lead electrode, and the other end of which is the element. A bipolar transistor having an emitter region terminating in an isolation region. 2. A first insulating film, a first polycrystalline silicon film containing a second conductivity type impurity on a first conductivity type semiconductor layer on the surface of an element formation region which is insulated from the surroundings, and an oxidation resistance. Sequentially depositing the second insulating film and the third insulating film,
A step of exposing a surface of the element formation region by opening a first window by anisotropic etching; and a first insulating film formed on the side surface of the first window and made of the same material as the second insulating film. A step of forming a side wall, a step of oxidizing the bottom surface of the first window to form a fourth insulating film, and a step of selectively removing the first side wall and the second insulating film in the vicinity thereof. The second
Forming an erosion part in the insulating film, and forming a second polycrystalline silicon film containing a second conductivity type impurity to backfill the erosion part with the first conductivity type semiconductor layer and the first sidewall. A step of forming a graft base region by introducing a second conductivity type impurity from the contact portion after making contact with the trace, and a step of forming a graft base region on the side surface of the first window through the second polycrystalline silicon film. Forming a second sidewall of the second insulating film, a step of etching the exposed surface of the second polycrystalline silicon film to form a recess on the outside of the second sidewall, and a sixth insulating film 2. A method for manufacturing a bipolar transistor, comprising the steps of: filling back the recess and forming a base region by introducing a second conductivity type impurity from the bottom of the first window. 3. A substrate containing a second conductivity type impurity on a substrate having a first insulation film having oxidation resistance only on the first conductivity type semiconductor layer on the surface of an element formation region isolated from the surroundings. 1
Polycrystalline silicon film, oxidation-resistant second insulating film and third
Sequentially depositing the insulating film, exposing the first insulating film on the element forming region by opening the first window by anisotropic etching, and the first window on the insulating isolation region. A part of the side surface of the element formation region by exposing a part of the side surface of the element formation region to a part of the side surface of the element formation region through the The method of manufacturing a bipolar transistor according to claim 2, further comprising the step of introducing an impurity of the second conductivity type into the exposed portion.