JP2542734B2 - Demodulating device and demodulating method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is one of element technologies in the field of wireless communication systems.
The present invention relates to an improved differential detection demodulation device, and more particularly to an improvement of the differential detection demodulation device using the technique of error correction code.

[Conventional technology]

A conventional differential detection / demodulation device using error correction code technology is disclosed in, for example, the document “Delayed detection error correction method / theoretical consideration” (Samejima and Enomoto, Proc. , pp. 8-283 to 8-284). The conventional technique will be described below with reference to the drawings.

FIG. 8 is a configuration diagram showing a configuration of a conventional differential detection demodulation device. In the figure, (100) is a differential 4-phase phase shift keying (hereinafter abbreviated as PSK; Phase Shift Keyin
g) a received signal that is a signal, (111) a delay element whose delay time is equal to the symbol interval time T (> 0) of the received signal (100), (112) a delay element whose delay time is equal to 2T, ( 113) is a delay element whose delay time is equal to 3T, (114)
Is a delay element having a delay time equal to 4T, (101) is a reception signal delayed by 1 symbol, (102) is a reception signal delayed by 2 symbols, (103) is a reception signal delayed by 3 symbols, and (104) is Received signal delayed by 4 symbols, (12
1), (122), (123), (124) are phase comparators, (13
1) is the first phase difference data, (132) is the second phase difference data, (133) is the third phase difference data, (134) is the fourth phase difference data, (141), (142). , (143), (144) are θ
If you enter a value of (0 ≦ θ <2π), [(θπ / 4)
/ (Π / 2)] (the addition is modulo 2π, and [a] means the maximum integer not exceeding a)
(150) is a received symbol, (151) is a first coded symbol, (152) is a second coded symbol, (153) is a third coded symbol, and (160) is Syndrome generation circuit, (161) is the first syndrome, (16
2) is the second syndrome, (163) is the third syndrome, (164) is the error pattern detection circuit, (165) is the error symbol, (166) is the subtracter modulo 4, and (167) is the demodulator. It is a demodulation symbol that is data. Also, the ninth
The figure is a block diagram showing the configuration of the syndrome generation circuit (160). In the figure, (200) is a convolutional encoder, and (20)
1), (202) and (203) are delay elements whose delay time is equal to T, (211), (212) and (213) are adders modulo 4, and (221) is the first re-encoding Symbol, (222) is the second
Are re-encoded symbols, (223) is a third re-encoded symbol, and (231), (232) and (233) are subtractors modulo 4.

 Next, the operation will be described.

In FIG. 8, the received signal (100), which is a differential 4-phase PSK signal, is delayed by a delay element (111) whose delay time is equal to the symbol interval time T of the received signal (100),
The received signal (101) is delayed by one symbol. Similarly, the received signal (100) has delay times of 2T, 3T, and 4 respectively.
Delayed by delay elements (112), (113), and (114) equal to T, delayed by 2 symbols, received signal (102), delayed by 3 symbols (103), and delayed by 4 symbols, respectively. It becomes the received signal (104). Next, the phases of the reception signal (101) delayed by one symbol and the reception signal (100) are compared by a phase comparator (121), and the phase difference between the two is output as first phase difference data (131). Similarly, the received signal delayed by 2 symbols (10
2) The phases of the received signal (103) delayed by 3 symbols and the received signal (104) delayed by 4 symbols and the received signal (100) are phase comparators (122), (123), and (124), respectively. ), The second phase difference data (132),
The third phase difference data (133) and the fourth phase difference data (134) are output. Further, the first phase difference data (131) is input to the determiner (141), and the received symbol (150) is output. Similarly, the second phase difference data (132) and the third phase difference data (132) are supplied to the decision units (142), (143), and (144), respectively.
Phase difference data (133) and fourth phase difference data (13
4) is input, and the first coded symbol (151), the second coded symbol (152), and the third coded symbol (1
53) is output. As described in the above-mentioned document, the received symbol (150), the first coded symbol (1
51), the second coded symbol (152) and the third coded symbol (153) are coded data of a quaternary convolutional code, which is a systematic code with a constraint length of 4 and a coding rate of 1/4. Are configured. Here, the first coded symbol (151), the second
Of the coded symbols (152) and the third coded symbols (153) of G ₁ (D) and G
Letting ₂ (D) and G ₃ (D), G ₁ (D) = 1 + D G ₂ (D) = 1 + D + D ² G ₃ (D) = 1 + D + D ² + D ³ . The received symbol (150) is the demodulated data itself of a general differential detection demodulator that does not use the error correction code technology.

The received symbol (150), the first coded symbol (151), the second coded symbol (152), and the third coded symbol that compose the convolutionally coded data thus obtained (153) to the syndrome generation circuit (16
By entering in 0), the first syndrome (16
1), the second syndrome (162), and the third syndrome (163) are generated.

The syndrome generation circuit (160) will be described below with reference to FIG.
The operation of will be described.

In FIG. 9, a delay element (20
1), (202), and (203) and adder modulo 4 (21
The received symbol (150) is input to the convolutional encoder (200) configured by 1), (212), and (213), and the first recoded symbol (221) and the second recoded symbol are input. (2
22) and the third re-encoded symbol (223) are output respectively. Here, the first re-encoded symbol (22
The generator polynomials of 1), the second re-encoding symbol (222), and the third re-encoding symbol (223) are respectively the first encoding symbol (151) and the second encoding symbol (15).
2) and the generator polynomial of the third coded symbol (153). Then, the first syndrome (161) is obtained by subtracting the first coded symbol (151) from the first re-coded symbol (221) by a modulo 4 subtractor (231). Similarly, subtractor modulo 4 (2
32), and the second re-encoded symbol (2
22), and from the third re-encoding symbol (223) to the second encoding symbol (152) and the third encoding symbol (1
By subtracting 53) respectively, the second syndrome (162) and the third syndrome (163) are obtained.

 The operation will be described below again with reference to FIG.

The first syndrome (161), the second syndrome (162), and the third syndrome (163) output from the syndrome generation circuit (160) are input to the error pattern detection circuit (164). The error pattern detection circuit (164) stores the syndrome patterns caused by various errors, and receives the input first syndrome (161), second syndrome (162), and third syndrome (1
When the syndrome pattern according to (63) matches any of the stored syndrome patterns, the error that causes the matched syndrome pattern is output as an error symbol (165). If they do not match, “0” is output as the error symbol (165). Next, the subtractor (166) modulo 4 subtracts the error symbol (165) from the received symbol (150) to obtain a demodulated symbol (167) in which the error of the received symbol (150) is corrected. That is, the demodulation symbol (167) is composed of the received symbol (150), the first coded symbol (151), the second coded symbol (152), and the third coded symbol (153). It is nothing but the result of the syndrome decoding of the convolutionally encoded data of. The demodulated symbols (16
By outputting (7) as demodulated data, it is possible to realize a better bit error rate characteristic than a general differential detection demodulator that does not use the error correction code technology.

[Problems to be Solved by the Invention]

Since the conventional differential detection demodulator is configured as described above, it requires a plurality of phase comparators to obtain convolutionally encoded data, and if the characteristics of these phase comparators do not match, the demodulated data The bit error rate characteristics deteriorate. However, the phase comparator generally has an analog circuit as its constituent element, and it is difficult to completely match the characteristics of the plurality of phase comparators due to the error inherent in the analog circuit. Further, even when the characteristics are aligned within an error range that does not pose a problem in practical use, it is necessary to spend a lot of time for adjusting each phase comparator. That is, the conventional differential detection demodulator has a problem that it takes a lot of time for adjustment in order to realize a good bit error rate characteristic. Further, the conventional apparatus has a problem in that the convolutionally encoded data is subjected to the syndrome decoding, and the Viterbi decoding, which is the best decoding method for the convolutionally encoded data, is not performed.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a demodulation device and a demodulation method that are easy to adjust and that perform Viterbi decoding of convolutionally encoded data.

[Means for solving the problem]

A demodulator according to the invention of claim 1 inputs a differentially coded signal, detects the differentially encoded signal by delay detection, and convolutionally encodes the signal delay-detected by the detection means. And a decoding means for decoding the signal coded by the coding means and outputting the decoded signal.

A demodulator according to the invention of claim 2 receives a signal having an arbitrary symbol interval time T (> 0), and demodulates the received signal using phase difference data between the received signals separated by the time T. The apparatus is provided with an encoding means for convolutionally encoding the phase difference data, and a decoding means for decoding the convolutionally encoded data output from the encoding means and outputting demodulated data. .

A demodulator according to the invention of claim 3 inputs a differentially encoded signal and delay-detects the differentially encoded signal, and a received symbol based on the signal delay-detected by the detector. Determination means for making a determination, quantizing means for quantizing the delay-detected signal and outputting a quantized detection signal, and calculating based on the delay-detected signal and the quantized detection signal, First calculation means for outputting the calculation result, coding means for convolutionally coding the calculation result by the first calculation means, and a coded signal output from the coding means is decoded to obtain a decoded signal. A second means for performing an operation on the basis of the decoding means for outputting and the decoded signal output from the decoding means and the received symbol output from the determining means, and outputting the operation result as demodulated data.
Calculation means.

A demodulator according to a fourth aspect of the present invention is the demodulator according to any one of the first to third aspects, wherein the decoding means is a Viterbi decoder.

A demodulator according to a fifth aspect of the present invention uses the Viterbi demodulator according to the fourth aspect, in which only three values {0,1, M-1 (M is an integer of 2 or more)} are used as internal states in the Viterbi algorithm. In addition to providing a combined state, the value of the decoded symbol to be output is only the above-mentioned three values, and the signal encoded by the encoding means is decoded and the decoded signal is output.

According to a sixth aspect of the demodulation method of the present invention, the differential coding input is subjected to delay detection by the detection means, the differentially detected signal is convolutionally coded by the coding means, and then the decoded signal is demodulated by the demodulation means. Is output.

[Action]

In the demodulator according to the first aspect of the present invention, if the differentially encoded signal is subjected to delay detection by the detection means, the differentially detected signal is input to the encoding means to generate convolutionally encoded data. For example, the decoding means performs decoding and outputs it as demodulated data.

In the demodulator according to the invention of claim 2, if the phase difference data of the received signals separated by the symbol interval time T (> 0) is input to the encoding means to generate the convolutional encoded data,
Decoding is performed by the decoding means and output as demodulated data.

In the demodulation device according to the third aspect of the present invention, if the differentially encoded signal is subjected to delay detection by the detection means and then the delay detected signal is quantized to generate a quantized detection signal, the delay detection is performed. Based on the signal and the quantized detection signal, convolutional coded data is generated and output, and further, the convolutional coded data is decoded and output as demodulated data.

In the demodulator according to the invention of claim 4, the Viterbi decoder decodes the convolutionally encoded data and outputs a decoded symbol as the demodulated data.

A demodulator according to the invention of claim 5 is a state in which only three values of {0,1, M-1} are combined as an internal state of a Viterbi decoder which inputs convolutionally encoded data from an encoding means and performs decoding. Should be provided.

In the demodulation method according to the invention of claim 6, when the differentially encoded signal is subjected to delay detection by the detection means, the differentially detected signal is input to the encoding means to generate convolutionally encoded data. For example, the decoding means performs decoding and outputs it as demodulated data.

〔Example〕

An embodiment of the first invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration of a differential detection demodulator according to an embodiment of the first invention, in which (131a) is phase difference data, (300) is a convolutional encoder, and (301) is 1
, The (302) is the second coded symbol,
(303) is a third coded symbol, (304) is a fourth coded symbol, (310) is a Viterbi decoder for decoding convolutional coded data, and (311) is decoding for demodulated data. It is a symbol. Further, FIG. 2 shows a convolutional encoder (30
(0) is a block diagram showing an embodiment, in which (40
1), (402), (403) are delay elements whose delay time is equal to the symbol interval time T of the received signal (100), (411), (41)
2) and (413) are adders modulo 2π, (421) and (42
For values 2), (423), and (424), enter a value of θ [(θ
π / 4) / (π / 2)] is output.
Incidentally, the judging devices (421) to (424) are not always necessary. Therefore, the convolutional encoder (300) operates even if the decision units (421) to (424) are not provided.

 Next, the operation will be described.

In FIG. 1, the received signal (100), which is a differential 4-phase PSK signal, is delayed by a delay element (111) whose delay time is equal to the symbol interval time T of the received signal (100),
The received signal (101) is delayed by one symbol. Next, the phases of the reception signal (101) delayed by one symbol and the reception signal (100) are compared by the phase comparator (121), and the phase difference between the two is output as phase difference data (131a).
The phase difference data (131a) is input to the convolutional encoder (300) and subjected to convolutional coding, and the first coded symbol (301) and the second code that form the convolutional coded data Coded symbol (302), third coded symbol (303),
And the fourth coded symbol (304) is output.

Here, as shown in FIG. 2, the convolutional encoder (300) includes delay elements (401) and (40) having the same delay time T.
2) and (403) and adders (411) and (4 modulo 2π
12), and (413), and the judgment devices (421), (422),
It is assumed that the encoder is a quaternary systematic code having a constraint length of 4 and a coding rate of 1/4 and configured by (423) and (424).
At this time, the second coded symbol (302), the third coded symbol (303), and the fourth coded symbol (304)
The generator polynomials of G ₂ (D), G ₃ (D), and G _{4 respectively}
Assuming that (D), G ₂ (D) = 1 + D G ₃ (D) = 1 + D + D ² G ₄ (D) = 1 + D + D ² + D ³ . The first coded symbol (301) is the demodulated data itself of a general differential detection demodulator that does not use the error correction code technique.

 Hereinafter, the operation will be described again with reference to FIG.

A first coded symbol (30 that forms the convolutional coded data output from the convolutional encoder (300)
1), the second coded symbol (302), the third coded symbol (303), and the fourth coded symbol (304) are input to the Viterbi decoder (310). A Viterbi decoder (310) decodes the convolutionally encoded data by the Viterbi decoding method.
For a description of the Viterbi decoding method and Viterbi decoder (310), see
For example, the document “Code Theory” (Imai, IEICE,
Since it was disclosed in 1990), its explanation is omitted here. The Viterbi decoder (310) outputs a decoded symbol (311) which is the result of decoding. By outputting the decoded symbol (311) thus obtained as demodulated data, it is possible to realize a better bit error rate characteristic than a general differential detection demodulator which does not use the error correction code technique.

This is specifically shown by using the result of computer simulation. FIG. 3 is a characteristic diagram showing a simulation value of the bit error rate of the embodiment of the first invention. However,
As a condition of the simulation, it is assumed that only additive white Gaussian noise exists in the signal transmission line. In the figure, the horizontal axis represents the ratio of energy per bit of the received signal to the power spectral density of noise (hereinafter abbreviated as E _b / N _o ) in decibels, and the vertical axis represents the bit error rate on a logarithmic scale. it's shown. Also, the broken line in the figure shows the theoretical value of the bit error rate of a general differential detection demodulator which does not utilize the error correction code technique, and the solid line shows the bit error rate of the apparatus of the first embodiment of the invention. It is a combination of simulation values of. As shown in FIG. 3, the device of the first embodiment of the invention has the same bit error rate with a smaller E _b / N _o as compared with a general differential detection demodulator which does not use the error correction code technique. Can be realized. For example, comparing the values of E _b / N _o required to obtain a bit error rate of 10 ^-5 , the difference is about 1.6 dB.

As described above, the device of the first embodiment of the present invention can realize a better bit error rate characteristic than a general differential detection demodulation device that does not use the error correction code technique. Further, the apparatus of the first embodiment requires only one phase comparator, and therefore the adjustment of the phase comparator is extremely easy.

Although the case where the received signal is a differential 4-phase PSK signal has been shown in the embodiment of the first invention, other operating multi-phase PSK signals may be used.
SK signal (for example, 8-phase PSK signal or π / 4-shift 4-phase PSK signal)
It may be. Also, as the convolutional encoder (300),
Convolutional coding with a constraint length of 4 and a coding rate of 1/4 is shown, but other constraint lengths and coding rates (eg constraint length 3, coding rate 1/3 or constraint Long 2 and coding rate 1/2).

Next, an embodiment of the second invention will be described with reference to the drawings. FIG. 4 is a block diagram showing a configuration of a differential detection demodulator according to an embodiment of the second invention, in which (300a) is a convolutional encoder, (310a) is a Viterbi decoder, and (500) is A quantizer that outputs a value of [(θπ / 4) / (π / 2)] π / 2 when a value of θ is input, (501) is quantized phase difference data,
(510) is a subtractor modulo 2π, (520) is error data, (521) is the first coded symbol, (522) is the second coded symbol, and (523) is the third coded symbol. Symbol, (5
24) is the fourth coded symbol, (531) is the decoded symbol, and (540) is the value of θ [(θπ / 4) /
(541) is a received symbol, (541) is a received symbol, (550) is a delay element whose delay time is equal to the decoding delay time of the Viterbi decoder (310a), and (551) is delayed. Received symbol, (560) is an adder modulo 4, (570)
Is a demodulation symbol that is demodulation data.

 Next, the operation will be described.

In FIG. 4, the received signal (100), which is a differential 4-phase PSK signal, is delayed by a delay element (111) whose delay time is equal to the symbol interval time T of the received signal (100),
The received signal (101) is delayed by one symbol. Next, the phases of the reception signal (101) delayed by one symbol and the reception signal (100) are compared by the phase comparator (121), and the phase difference between the two is output as phase difference data (131a).
The phase difference data (131a) is input to the quantizer (500),
It becomes the quantized phase difference data (501). Further, the subtractor (510) modulo 2π subtracts the quantized phase difference data (501) from the phase difference data (131a) to obtain error data (520). The error data (520) is input to a convolutional encoder (300a) to be convolutionally encoded, and the first encoded symbol (521) and the second encoded symbol that form the convolutional encoded data. The symbol (522), the third coded symbol (523), and the fourth coded symbol (524) are output. Where convolutional encoder (300a)
Is a constraint length 4 having the same configuration as the convolutional encoder (300) in the apparatus of the first embodiment shown in FIG.
It is assumed to be an encoder of / 4 quaternary systematic code. Therefore,
The generator polynomials of the second coded symbol (522), the third coded symbol (523), and the fourth coded symbol (524) are G ₂ (D), G ₃ (D), and G, respectively. _{Assuming that 4} (D), G ₂ (D) = 1 + D G ₃ (D) = 1 + D + D ² G ₄ (D) = 1 + D + D ² + D ³ . The first coded symbol (521) and the second coded symbol (52
2), the third coded symbol (523), and the fourth coded symbol (524) are input to the Viterbi decoder (310a). The Viterbi decoder (310a) outputs a decoded symbol (531) which is the result of decoding.

On the other hand, the phase difference data (131a) is also input to the determiner (540) and the reception data (541) is output. The received data (541) is the demodulated data itself in a general differential detection demodulator that does not use the error correction code technology. Next, the reception data (541) becomes delayed reception data (551) by the delay element (550) whose delay time is equal to the decoding delay time of the Viterbi decoder (310a). Finally, an adder (560) modulo 4 delays the received data (55
The decoded symbol (531) is added to 1) to obtain the demodulated symbol (570). By outputting the obtained demodulation symbol (570) as demodulation data, good bit error rate characteristics equivalent to those of the device of the first embodiment can be realized. Also,
Since the second embodiment device of the second invention also requires only one phase comparator, the adjustment of the phase comparator is as easy as the first embodiment device of the first invention.

By the way, since the received signal (100) is a differential 4-phase PSK signal, the decoded symbol (311) corresponding to the output of the Viterbi decoder (310) in the device of the first embodiment of the invention is correspondingly. Can take four values {0,1,2,3} (differential M
In the case of a phase PSK signal, it is {0, 1, ..., M-1} M value).
Actually, in the device of the first embodiment of the present invention, since the phase difference data (131a) having a value of 0 or more and less than 2π is convolutionally encoded,
The decoded symbol (311) takes all values of {0,1,2,3}.

Similarly, the decoded symbol (531) which is the output of the Viterbi decoder (310a) in the device of the second invention.
Originally, the possible values of should be four values of {0,1,2,3}. However, the error data (520) is convolutionally encoded in the apparatus of the second embodiment of the present invention. However, the second
According to the configuration of the apparatus of the embodiment of the invention, the error data (52
The range of values that 0) can take is −π / 4 or more and less than π / 4 (when the received signal (100) is a differential M-phase PSK signal, −π / M or more and less than π / M). Therefore, the possible values of the decoded symbol (531) are only {0,1,3}) ({0,1, M-1} if the received signal (100) is a differential M-phase PSK signal). Limited to

As described above, in the device of the second embodiment of the present invention, since the value taken by the decoded symbol (531) is limited to three values, the Viterbi decoder (310a) has a simplified configuration by reducing the number of internal states. A decoder can be used. That is, the decoded symbol (311) is {0,
Since the constraint length of the convolutional code is 4, the number of internal states that the Viterbi decoder (310) should have is 64 (= 4 ³ ) It is a state. FIG. 5 shows a basic state transition in the trellis diagram in this case. On the other hand, in the device of the second embodiment of the present invention, the value taken by the decoded symbol (531) is three values {0, 1, 3}, so the number of internal states that the Viterbi decoder (310a) should have is 27.
(= 3 ³ ) State is reduced. FIG. 6 shows the basic state transition in the trellis diagram in this case. Reduction of the number of internal states of the Viterbi decoder means reduction of circuits and memories provided in the Viterbi decoder, and therefore simplification of the configuration.

As is clear from the above, since the device of the second invention is configured to convolutionally code the error data (520), the configuration of the Viterbi decoder (310a) is the device of the first invention. It has the effect that it can be made simpler than the Viterbi decoder (310), and therefore can be made smaller and consume less power than the device of the first embodiment of the invention. Generally, if the received signal (100) is a differential M-phase PSK signal and the constraint length of the convolutional code is K (≧ 2), the first
The internal state to be provided for the Viterbi decoder (310) of the embodiment of the invention is M ^K-1 . On the other hand, the number of internal states that the Viterbi decoder (310a) of the device of the second invention should have is 3 ^K-1 regardless of the multi-level number M of the received signal (100). Therefore, the larger the multi-valued number M of the received signal, the greater the effect of simplifying the configuration of the Viterbi decoder by reducing the number of internal states in the device of the second embodiment.

As described above, the Viterbi decoder having a simplified configuration can be used in the device of the second invention, but even when the Viterbi decoder having the simplified configuration is used, An equivalent good bit error rate characteristic can be realized.
This is specifically shown by using the result of computer simulation. FIG. 7 is a characteristic diagram showing the simulation value of the bit error rate of the device of the second invention. However, as a condition of the simulation, the Viterbi decoder (31
0a) has a simplified structure, and it is assumed that only additive white Gaussian noise exists in the signal transmission line.

Comparing FIG. 7 and FIG. 3, even when a Viterbi decoder with a simplified configuration is used as the Viterbi decoder (310a) of the apparatus of the second invention, the apparatus of the first invention is used. It is obvious that a bit error rate characteristic equivalent to can be realized.

Although the case where the received signal is a differential 4-phase PSK signal is shown in the embodiment of the second invention, other differential multi-phase PSK signals may be used.
It may be an SK signal (for example, an 8-phase PSK signal or a π / 4-shift 4-phase PSK signal). Further, as the convolutional encoder (300a), the one that performs the convolutional coding with the constraint length of 4 and the coding rate of 1/4 is shown, but other constraint lengths and coding rates (for example, constraint length 3, The coding rate is 1/3, the constraint length is 2, the coding rate is 1/2, etc.).

〔The invention's effect〕

According to the invention of claim 1, a detection means for inputting the differentially encoded signal and delaying and detecting the differentially encoded signal,
Since the encoding means for convolutionally encoding the signal delay-detected by the detection means and the decoding means for decoding the signal encoded by this encoding means and outputting the decoded signal are provided, the phase comparator is provided. 1 is sufficient, and therefore, the time required for adjusting the phase comparator can be significantly shortened as compared with the conventional device.

According to the invention of claim 2, an arbitrary symbol interval time T
In a demodulation device that receives a signal having (> 0) and demodulates the received signal using the phase difference data between the received signals separated by time T, an encoding means for convolutionally encoding the phase difference data. , A decoding means for decoding the convolutional coded data output from the decoding means and outputting demodulated data, wherein a good bit can be obtained by decoding the convolutional coded signal by the decoding means. There is an effect that the error rate characteristic can be realized.

A demodulator according to the invention of claim 3 inputs a differentially encoded signal and delay-detects the differentially encoded signal, and a received symbol based on the signal delay-detected by this detecting means. Determination means for making a determination, a quantizing means for quantizing the delay-detected signal and outputting a quantized detection signal, and an operation based on the delayed-detected signal and the quantized detection signal Then, the first arithmetic means for outputting the arithmetic result, the encoding means for convolutionally encoding the arithmetic result by the first arithmetic means, and the encoded signal output by the encoding means are decoded. A decoding means for outputting a decoded signal, an operation based on the decoded signal output from the decoding means and the received symbol output from the determining means, and the operation result output as demodulated data 2 calculation means Because with a, since the phase comparator requires only one, there is an effect that the adjustment of the phase comparator becomes easy.

According to the invention of claim 4, since the decoding means in the demodulator according to any one of claims 1 to 3 is constituted by the Viterbi decoder which is the most excellent decoding means of the convolutional code, good bits can be obtained. There is an effect that the error rate characteristic can be realized.

According to the invention of claim 5, the Viterbi decoder according to claim 4 combines only three values of {0, 1, M-1 (M is an integer of 2 or more)} as internal states in the Viterbi algorithm. In addition to the state, the value of the decoded symbol to be output is limited to the above three values, and the signal encoded by the encoding means is decoded and the decoded signal is output, so that the internal state that the Viterbi decoder should have is provided. Since the number can be reduced, there is an effect that the circuits and memories included in the Viterbi decoder can be reduced and the configuration of the device can be simplified.

According to the invention of claim 6, after the input differential encoding is differentially detected by the detecting means, the differentially detected signal is convolutionally encoded by the encoding means and then output as the decoded signal by the demodulating means. Since this is done, there is an effect that the time required for adjusting the phase comparator can be significantly shortened as compared with the conventional device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a differential detection demodulator according to an embodiment of the first invention, and FIG. 2 is a configuration diagram showing an embodiment of a convolutional encoder (300) shown in FIG. FIG. 3 is a characteristic diagram showing a computer simulation value of a bit error rate of the device of the first invention, and FIG. 4 is a configuration diagram showing a structure of a differential detection demodulator according to an embodiment of the second invention. FIG. 5 is a state transition diagram showing basic state transitions in a trellis diagram of a Viterbi decoder that does not reduce the number of internal states, and FIG. 6 is a basic state transition diagram of a trellis diagram of a Viterbi decoder in which the number of internal states is reduced. The state transition diagram showing the state transition, FIG. 7 is the second
FIG. 8 is a characteristic diagram showing a computer simulation value of a bit error rate of the embodiment of the invention, FIG. 8 is a configuration diagram showing a configuration of a conventional differential detection demodulator, and FIG. 9 is a syndrome generation circuit shown in FIG. It is a block diagram which shows the structure of (160). In the figure, (100) is the received signal, (101) is the received signal delayed by one symbol, and (111) is the received time (1).
A delay element equal to the symbol interval time T of (00), (121)
Is a phase comparator, (131a) is phase difference data, (300) is a convolutional encoder, (300a) is a convolutional encoder, and (301) is the first
, The (302) is the second coded symbol,
(303) is a third coded symbol, (304) is a fourth coded symbol, (310) is a Viterbi decoder, (310a) is a Viterbi decoder, and (311) is a decoded symbol which is demodulated data. , (500) is a quantizer, (501) is quantized phase difference data, (510) is a subtractor modulo 2π, (520) is error data, (521) is the first coded symbol, ( 522) is the second coded symbol, (523) is the third coded symbol, (524) is the fourth coded symbol, (531) is the decoded symbol, (540) is the decision unit, and (541) is Received symbol,
(560) is an adder modulo 4, and (570) is a demodulation symbol which is demodulation data. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (6)

(57) [Claims] 1. A detection means for inputting a differentially encoded signal and differentially detecting the differentially encoded signal, and an encoding means for convolutionally encoding the signal differentially detected by the detection means. A demodulating device comprising: a decoding means for decoding the signal coded by the coding means and outputting the decoded signal. 2. A demodulator for receiving a signal having an arbitrary symbol interval time T (> 0) and demodulating the received signal using phase difference data between the received signals separated by time T,
Demodulation, comprising: encoding means for convolutionally encoding the phase difference data; and decoding means for decoding the convolutionally encoded data output from the encoding means and outputting demodulated data. apparatus. 3. A detection means for inputting a differentially encoded signal and differentially detecting the differentially encoded signal, and a determination means for determining a received symbol based on the signal differentially detected by the detection means. A quantizing means for quantizing the delay-detected signal and outputting a quantized detection signal; and a calculation based on the delay-detected signal and the quantized detection signal, and outputting the calculation result. First computing means, coding means for convolutionally coding the computation result by the first computing means, and decoding means for decoding the coded signal output from the coding means and outputting the decoded signal. And a second arithmetic means for performing arithmetic operation on the basis of the decoded signal output from the decoding means and the received symbol output from the determining means, and outputting the operation result as demodulated data. Characterized by Demodulation device. 4. The demodulator according to claim 1, wherein the decoding means is a Viterbi decoder. 5. The Viterbi demodulator has a state in which only three values of {0, 1, M-1 (M is an integer of 2 or more)} are combined as an internal state in the Viterbi algorithm, and
5. The demodulation device according to claim 4, wherein the value of the decoded symbol that is output is only the three values, the signal encoded by the encoding means is decoded, and the decoded signal is output. 6. A differential detecting means for differentially detecting the input differential encoding, the convolutional coding of the differentially detected signal by the coding means, and the outputting of the signal as a decoded signal by the decoding means. Characteristic demodulation method.