JP2544886B2 - Data transfer system and data transfer method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system and method, and more particularly to speeding up the transfer speed thereof.

[0002]

2. Description of the Related Art FIG. 10 shows the configuration of a conventional data transfer system. A data bus 4 and an address bus 6 are connected to the CPU 2. Further, the read signal line IOR for outputting the read signal IOR0 and the write signal line IOW for outputting the write signal IOW0 are connected. Now, the first-in first-out (FIF) of the first circuit 10
O) The data of the memory 16 is transferred to the FIFO of the second circuit 20.
It shall be transferred to the memory 26.

In this case, the CPU 2 outputs an address signal indicating the first circuit 10 to the address bus 6 (FIG. 11).
(See α1). In accordance with this, the read signal line IO
The read signal IOR0 is output to R (see β in FIG. 11). The address decoder 12 of the first circuit 10 detects that the address signal for itself is applied and outputs the address coincidence signal CS1 (see γ in FIG. 11).
The OR circuit 14 takes the logical sum of the address match signal CS1 and the read signal IOR0 and outputs the read enable signal RES (see δ in FIG. 11). This read enable signal RES
Are applied to the read permission input RE of the FIFO memory 16. When the read enable signal RES is applied, the FIFO memory 16 outputs the stored data to the data bus 4 (see D1 in FIG. 11). At this time, the CPU 2 takes in the data from the data bus 4 and stores it in the internal register.

In the next cycle, the CPU 2 outputs an address signal indicating the second circuit 20 to the address bus 6 (see α2 in FIG. 11). At the same time, the write signal IOW0 is output to the write signal line IOW (see ζ in FIG. 11). Further, the data stored in the register is output to the data bus 4 (see D2 in FIG. 11). The address decoder 22 of the second circuit 20 detects that the address signal for itself is applied, and outputs the address match signal CS2. The OR circuit 24 takes the logical sum of the address coincidence signal CS2 and the write signal IOW0 and outputs the write enable signal WES (see η in FIG. 11). The write enable signal WES is applied to the write enable input WE of the FIFO memory 26. When the write enable signal WES is given, the FIFO memory 26 takes in and stores the data from the data bus 4.

Data can be transferred from the first circuit 10 to the second circuit 20 as described above. When a large number of data are continuously transferred, the above operation may be repeated.

[0006]

However, the above-mentioned prior art has the following problems. There is a problem that two cycles are required to transfer data from the first circuit to the second circuit, and the transfer speed is slow.
Especially, when a standardized low-speed bus (expansion bus of a personal computer or the like) is used as the data bus or the address bus, it is even more so.

In view of the above problems, it is an object of the present invention to provide a system and method capable of high speed data transfer.

[0008]

According to a first aspect of the present invention, there is provided a data transfer method comprising: a first circuit connected to a data bus and an address bus of a CPU; and a second circuit connected to the data bus and the address bus. A method of transferring data, wherein a first circuit comprises a first memory circuit and a first control circuit, and a second circuit comprises a second memory circuit and a second control circuit. , The CPU outputs a read signal to the first control circuit and also outputs an address signal designating the first circuit to the address bus, and the first control circuit outputs the read signal and the address signal. Based on the read permission signal, the first storage circuit outputs the stored data to the data bus based on the read permission signal, and the second control circuit outputs the read signal and the address signal. Basis There generates a write enable signal, the second
The storage circuit is characterized by taking in and storing the data on the data bus based on the write enable signal.

In the data transfer method of claim 2, the CPU is
The read signal is output to the first control circuit, and the address signal designating the first circuit is output to the address bus. The first control circuit, based on the read signal and the address signal, A series of a plurality of read permission signals are generated in a unit cycle, the first memory circuit sequentially outputs the stored data to the data bus based on the plurality of read permission signals, and the second control circuit Generates a series of a plurality of write permission signals corresponding to the plurality of read permission signals based on the read signal and the address signal, and the second memory circuit is configured to generate a plurality of write permission signals. It is characterized in that the data on the data bus is sequentially fetched and stored on the basis of the above.

The data transfer method according to claim 3 is characterized in that the second control circuit outputs a wait signal to the CPU so that the data transfer can be completed during the unit cycle.

A data transfer method according to claim 4 and claim 1
In the first data transfer system, the second control circuit generates the division signal, divides the write permission signal into the first write permission signal and the second write permission signal based on the division signal, and The control circuit is characterized in that the read permission signal is divided into a first read permission signal and a second read permission signal based on the division signal from the second control circuit.

A data transfer method according to claim 5 and claim 1
In the data transfer system of No. 2, the first control circuit generates a division signal, divides the read permission signal into a first read permission signal and a second read permission signal based on the division signal, The control circuit is characterized in that the write permission signal is divided into a first write permission signal and a second write permission signal based on the division signal from the first control circuit.

A data transfer method according to claim 6 and claim 1
The data transfer system of No. 3 is characterized in that the first or second storage circuit is a first-in first-out memory.

A data transfer method according to claim 7 and claim 1
In the data transfer system of No. 4, the first or second memory circuit is a memory by addressing, the address signal specifies a higher address, and a lower address is specified for the memory by the addressing. It is characterized in that a lower address signal to be designated is given.

According to another aspect of the data transfer system of the present invention, the first circuit outputs the first address coincidence signal when the address signal on the address bus coincides with its own address.
Address decoder, read signal from CPU and first
A read enable signal generation circuit that generates a read enable signal based on the address match signal, and a read enable signal,
A first memory circuit for outputting the stored data to a data bus, and the second circuit outputs a second address match signal when the address signal of the address bus matches its own address. A second address decoder that makes its own address the same as the address of the first circuit, and a write enable signal based on a read signal and a second address match signal from the CPU. A write enable signal generating circuit for generating a write enable signal and a second circuit for receiving the write enable signal and storing the data on the data bus
And a memory circuit of.

According to another aspect of the data transfer system of the present invention, the first circuit outputs the first address coincidence signal when the address signal on the address bus coincides with its own address.
Address decoder, read signal from CPU and first
A read enable signal generation circuit that generates a series of read enable signals in a unit cycle based on the address match signal, and a plurality of read enable signals that receive the stored read data and sequentially output the stored data to a data bus. The second circuit is a second address decoder which outputs a second address match signal when the address signal of the address bus matches its own address. A second address decoder whose address is the same as the address of the first circuit, and a series of write enable signals corresponding to the read enable signal based on the read signal and the second address match signal from the CPU. A write enable signal generation circuit for generating and a second memory circuit for receiving a plurality of write enable signals and sequentially storing the data on the data bus are provided. It is characterized by a door.

A data transfer system according to a tenth aspect of the present invention comprises a wait signal generation circuit for outputting a wait signal to the CPU so that the second circuit can finish the data transfer during the unit cycle. It is characterized by that.

[0018]

In the data transfer method and system according to claims 1 and 8, the addresses of the first circuit and the second circuit are made the same, the signal is read from the first circuit by a read signal from the CPU, and at the same time the second circuit is read. I try to write to the circuit. Therefore, the transfer can be completed in one cycle, and the transfer speed is improved.

In the data transfer method / system according to claims 2 and 9, a plurality of read permission signals and write permission signals are further generated in response to one read signal from the CPU. Therefore, a plurality of data can be transferred in one cycle, and the transfer speed is further improved.

In the data transfer method and system according to claims 3 and 10, a wait signal is given to the CPU so that the data transfer can be completed in a unit cycle. Therefore, the data transfer can be reliably performed.

In the data transfer method and system according to claims 4 and 11, the second read enable signal is generated by the division signal from the second circuit. Therefore, the transfer speed can be improved while surely and accurately transferring the data. In the data transfer method and system according to claims 5 and 12, the second write enable signal is generated by the division signal from the first circuit. Therefore, the transfer speed can be improved while surely and accurately transferring the data.

[0022]

1 shows the structure of a data transfer system according to an embodiment of the present invention. The first memory circuit corresponds to the FIFO memory 16, and the second memory circuit corresponds to the FIFO memory 26. The first control circuit corresponds to the address decoder 12A and the OR circuit 1
4, and the address decoder 12B and the OR circuit 24 correspond to the second control circuit.

In this embodiment, the address assigned to the first circuit 10 and the address assigned to the second circuit 20 are the same. That is, the address decoder 12A and the address decoder 12B are configured to output the address match signal to the same address. The second circuit 20 also writes the write enable signal WES based on the read signal IOR0 from the CPU 2.
I am trying to generate.

FIG. 2 is a timing chart showing the operation of this system. Now the FIFO of the first circuit 10
The data in the memory 16 will be described as being transferred to the FIFO memory 26 of the second circuit 20. In this case, CP
U2 outputs an address signal indicating the first circuit 10 to the address bus 6 (see α in FIG. 2). The address decoder 12A detects that an address for itself is given and outputs an address match signal CS1. further,
The CPU 2 sends the read signal IO to the read signal line IOR.
R0 is output (see β in FIG. 2).

In response to this, the OR circuit 14 of the first circuit 10 causes the address match signal CS1 and the read signal IOR0.
And the read permission signal RES is output (see δ in FIG. 2). This read enable signal RES is FI
It is given to the read permission input RE of the FO memory 16. F
When the read enable signal RES is applied, the IFO memory 16 outputs the stored data to the data bus 4 (see D in FIG. 2).

On the other hand, since the same address as that of the first circuit 10 is assigned also to the second circuit 20, the address decoder 12B of the second circuit 20 causes the address decoder 12B of the first circuit 10 to receive the address match signal of the first circuit 10. The address coincidence signal CS2 is output at the same timing as CS1. In addition, the second circuit 2
The OR circuit 24 of 0 takes the logical sum of the address coincidence signal CS2 and the read signal IOR0 to obtain the write enable signal W
ES is generated (see η in FIG. 2). Therefore, the write enable signal WES is output at substantially the same timing as the read enable signal RES. This write enable signal WES is
It is given to the write permission input WE of the FIFO memory 26. The FIFO memory 26 receives and stores the data on the data bus 4 when the write enable signal WES is applied. At this time, since the data from the first circuit 10 is being output onto the data bus 4, the data will be transferred from the first circuit 10 to the second circuit 20.

When one unit of data is transferred as described above, the CPU 2 similarly outputs the read signal IOR and the address signal in the next cycle to transfer the next data.

As described above, since the reading and writing are performed in one cycle, the transfer speed is greatly improved as compared with the conventional method. In particular, when the processing speed is set low to ensure compatibility, such as the expansion bus line of a personal computer, the transfer speed can be doubled by adopting the system according to this embodiment. Can
Highly useful.

Another embodiment is shown in FIG. Also in this embodiment, the addresses assigned to the first circuit 10 and the second circuit 20 are the same, and the second circuit 20 generates the write enable signal based on the read signal IOR. Is the same as the embodiment of FIG. In this example,
The read enable signal RES is divided by the read pulse generation circuit 13 so that four read enable signals RES1 to RES4 are obtained in one cycle (RE in FIG. 4).
S1 to RES4). In this embodiment, the OR circuit 14, the read pulse generating circuit 13, and the address decoder 12A constitute a first control circuit. Further, the OR circuit 24, the write pulse generating circuit 23, the wait signal generating circuit 25, and the address decoder 12B constitute a second control circuit.

The read permission signals RES1 to RES4 divided as shown in FIG. 4 are applied to the read permission input RE of the FIFO memory 16. The FIFO memory 16 receives the read enable signals RES1 to RES4,
The stored data is sequentially output to the data bus 4 (see D1 to D4 in FIG. 4). That is, in response to the read enable signal RES1, the stored first data D1 is output to the data bus 4, and then the read enable signal RES2.
Then, the next data D2 stored therein is transferred to the data bus 4
The data is sequentially output.

On the other hand, the second circuit 20 is provided with a write pulse generating circuit 23 for dividing the write enable signal WES. The write pulse generating circuit 23 may have the same configuration as the read pulse generating circuit 13. The write pulse generation circuit 23 uses the read enable signals RES1 to R
The output is configured to be output at the same timing as ES4 (see WES1 to WES4 in FIG. 4). Therefore, the data D1 to D4 output from the first circuit 10 to the data bus 4 can be sequentially captured and stored.

A wait signal generating circuit 25 is provided in the second circuit 20. This circuit receives the write enable signal WES and outputs a wait signal IORDY1 as shown by θ in FIG. The weight signal IORDY1 is given to the CPU 2 through the weight signal line IORDY. As a result, the CPU2
Does not change the read signal IOR0 output to the read signal line IOR while the wait signal IORDY1 is being output (during the period of L). Therefore, the wait signal IORDY1 is transmitted to the fourth data D4 in the FIFO.
By outputting the data until it is read into the memory 26, it is possible to reliably transfer the data. That is, when there is a possibility that the standard one cycle time is exceeded to transfer four data, the wait signal I as in this embodiment is used.
It is preferable to use ORDY1 from the viewpoint of improving reliability.

If the four data can be reliably transferred within the standard one cycle time, the wait signal IO
Higher-speed transfer can be performed without using RDY1.

Details of the write pulse generation circuit 23 and the wait signal generation circuit 25 used in this embodiment will be described with reference to the state transition diagram of FIG. In the figure, WE represents the output of the write pulse generation circuit 23, and WT represents the output of the wait signal generation circuit 25. While the input is "H", that is, while the signal WES is "H",
The state 0 (WE = “H”, WT = “H”) is held. Next, when the signal WES becomes “L”, the state 1 (WE
= “L”, WE = “L”). After that, each time the clock φ (see FIG. 3) is applied, the state transitions to state 2, state 3, and so on. As a result, write enable signals WES1 to WES4 and wait signal IORDY1 as shown in FIG. 4 can be generated.

The read pulse generation circuit 13 also generates the read permission signals RES1 to RES4 in the same manner as described above. However, no weight signal is generated. In this embodiment, the system clock φ of the CPU 2 (or a divided or multiplied version thereof) is used for both the read pulse generation circuit 13 and the write pulse generation circuit 23. Therefore, the operations of both circuits are synchronized, and reliable data transfer can be performed. If there is a clock signal that keeps the same frequency within an allowable error range, it may be used.

The circuit for performing the operation shown in FIG. 5 can be easily configured by a programmable logic or the like, and can also be easily configured by a logic circuit.

In this embodiment, since the read enable signal and the write enable signal are divided into four, it is possible to transfer four unit data in one cycle. That is, data can be transferred at high speed.

In the above embodiment, the read permission signal,
Although the write permission signal is divided into four, the number of divisions can be arbitrarily selected.

FIG. 6 shows a data transfer system according to another embodiment. Also in this embodiment, the addresses assigned to the first circuit 10 and the second circuit 20 are the same, and the second circuit 20 generates the write enable signal based on the read signal IOR. Is the same as the embodiment of FIGS. 1 and 3. In this embodiment, the first read enable signal RES1 and the second read enable signal RES2 are obtained within one cycle (RES1, R in FIG. 7).
See ES2). This embodiment is different from the embodiment of FIG. 3 in that the first circuit 1 receives a signal from the second circuit 20.
0 is to generate the second read enable signal RES2. As a result, the reliability of data transfer can be improved. In this embodiment, the address decoder 1
2A, OR circuit 14, delay circuit 15, NOT circuit 17,
The AND circuit 19 constitutes a first control circuit. The address decoder 12B, the OR circuit 24, the delay circuit 27A, the NOT circuit 29, the AND circuit 31, the buffer 21, the delay circuit 27B, the NOT circuit 33, the AND circuit 35, and the OR circuit 37 form a second control circuit. There is.

The CPU 2 outputs the address signal indicating the first circuit 10 to the address bus 6 and also outputs the read signal IOR0 to the read signal line IOR. In response to this, the address decoder 12A of the first circuit 10
Outputs an address match signal CS1. Furthermore, OR
The circuit 14 generates the first read signal RES1 (see FIG. 7) based on the address match signal CS1 and the read signal IOR0. This first read signal RES1
Is supplied to the FIFO memory 16, and the data D1 is output to the bus line 4.

On the other hand, the address decoder 12B of the second circuit 20 outputs the address coincidence signal CS2. Further, the OR circuit 24 generates the signal (C) of FIG. 7 based on the address match signal CS2 and the read signal IOR0. The signal (C) is supplied to the FIFO memory 26 as the first write signal WES1 (see FIG. 7) via the OR circuit 37.
Given to. Upon receiving this first write signal, the FIF
The O memory 26 takes in and stores the data D1 of the bus line 4. As a result, the data D1 is transferred.

The signal (C) of the second circuit 20 is the delay circuit 2
7A, the NOT circuit 29, and the OR circuit 31 convert to the divided signal (E). This divided signal (E) is sent to the wait signal line IORD via the three-state buffer 21.
It is output to Y and transmitted to the first circuit 10. The first circuit 10 receives the divided signal (E) and receives the delay circuit 15,
The signal of FIG. 7 is output by the NOT circuit 17 and the AND circuit 19.
Generate (B). Since this signal (B) is given to the OR circuit 14, the output of the OR circuit 14 is divided into the first read enable signal RES1 and the second read enable signal RES2, as shown in FIG. This second read enable signal RES2 causes the next data D from the FIFO memory 16 to be read.
2 is output to the bus line 4 (see D2 in FIG. 7).

On the other hand, also in the second circuit 20, the delay circuit 27B, the NOT circuit 33, and the AND circuit 35 generate the signal (I) based on the generated divided signal (E). Since this signal (I) is given to the OR circuit 37, the output of the OR circuit 37 is the first write enable signal WES1 and the second write enable signal WES as shown in FIG.
It is divided into two. By the second write enable signal WES2, the next data D2 is fetched from the bus line 4 and stored in the FIFO memory 26.

In the above embodiment, the second circuit 20 to the first circuit
The divided signal (E) is sent to the circuit 10. However, the first circuit 10 is configured like the second circuit 20 of FIG. 6 so that the first circuit 10 generates the divided signal, and the divided signal is supplied to the second circuit 20. Good.

Although the weight signal line IORDY is used to transmit the divided signal (E) in the above embodiment, another line may be used.

In each of the above embodiments, the address decoder is provided in both the first circuit 10 and the second circuit 20. However, the address decoder may be provided only in one of the first circuit 10 and the second circuit 20, and the address match signal may be sent from the side provided with the address decoder to the side not provided. In this case, the address match signal may be sent via the control line (usable line in the bus line or the like).

In each of the above-described embodiments, the circuit configuration is such that only the transfer method of the present invention can be implemented. However, as in the second circuit 20 shown in FIG. The transfer method (referred to as high speed mode) may be switched. The address decoder 12B has a first
When the address of the circuit 10 is applied to the address bus 6, the address match signal S3 is output, and when the address of the second circuit 20 is applied to the address bus 6, the address match signal S2 is output. When the inverted output QB of the D flip-flop 40 is at high level (H),
The address coincidence signal S2 is given to the FIFO memory 26, and the normal mode (equivalent to FIG. 10) is set. Further, when the inverted output QB of the D flip-flop 40 is at low level (L), the address match signal S3 is given to the FIFO memory 26, and the high speed mode (equivalent to FIG. 1) is set.

The switching between the two modes is performed by the D flip-flop 40. When power is turned on, RESET
Since the reset signal RESET0 for the line is "L", the inverted output QB becomes "H" and the normal mode is set.
In order to change this, the mode switching address is output to the address bus 6. The address decoder 12B is
Address match signal S for the mode switching address
Outputs 1. As a result, the clock is applied to the clock input CLK of the D flip-flop 40. This time,
"H" to D input by any line of data bus 4
(That is, when the CPU 2 outputs "H" to the line connected to the D input of the data bus 4), the inverted output QB becomes "L", and the high speed mode is set. Further, when switching to the normal mode, similarly, "L" is applied to the D input and the inverted output QB is set to "H".

Note that such switching can be applied to the embodiments shown in FIGS. 3 and 6.

Further, in each of the above-described embodiments, the data transfer from the FIFO memory to the FIFO memory is shown as an example, but either one or both of them may be a memory having a normal address designation. An example where both are addressed memory is shown in FIG. In this example, the first circuit 10
In the above, the upper address of the memory 86 is given to the address decoder 12A, and the lower address is given to the memory 86. For example, assuming that the memory 86 is allocated from the address "00000000" to the address "00001111",
The upper 4 bits are input to the address decoder 12A,
The lower 4 bits are input to the memory 86. The second
The same applies to the circuit 20 of FIG.
2B has the same upper address as the address decoder 12A, and is configured to output an address match signal. C
PU2 transfers data one by one by changing a lower address one by one.

In the above embodiment, a memory is used as an example of the memory circuit, but the "memory circuit" in the present application is not limited to what is called a memory, and any memory can be used as long as it can hold data. Such a circuit (for example, a register or the like) may be used.

[0052]

According to the data transfer method and system of the present invention, the addresses of the first circuit and the second circuit are made identical, and the first circuit and the second circuit are read at the same time by the read signal from the CPU. I am trying to write to the second circuit. Therefore, the transfer can be completed in one cycle, and the transfer speed is improved.

In the data transfer method and system according to claims 2 and 9, a plurality of read enable signals and write enable signals are further generated corresponding to one read signal from the CPU. Therefore, a plurality of data can be transferred in one cycle, and the transfer speed is further improved.

In the data transfer method and system according to claims 3 and 10, a wait signal is given to the CPU so that the data transfer can be completed in a unit cycle. Therefore, the data transfer can be reliably performed.

In the data transfer method and system according to the fourth and eleventh aspects, the second read enable signal is generated by the division signal from the second circuit. Therefore, the transfer speed can be improved while surely and accurately transferring the data. In the data transfer method and system according to claims 5 and 12, the second write enable signal is generated by the division signal from the first circuit. Therefore, the transfer speed can be improved while surely and accurately transferring the data. That is,
According to the present invention, highly reliable and high-speed data transfer can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a data transfer system according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the data transfer system of FIG.

FIG. 3 is a diagram showing a data transfer system according to another embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the data transfer system of FIG.

FIG. 5 is a state transition diagram showing an operation of the write pulse generation circuit 23.

FIG. 6 is a diagram showing a data transfer system according to another embodiment of the present invention.

7 is a time chart showing the operation of the data transfer system of FIG.

FIG. 8 is a diagram showing a circuit that realizes switching of operation modes.

FIG. 9 is a diagram showing a data transfer system according to another embodiment.

FIG. 10 is a diagram showing a conventional data transfer system.

11 is a time chart showing the operation of the data transfer system of FIG.

[Explanation of symbols]

 2 ... CPU 4 ... Data bus 6 ... Address bus 12A, 12B ... Address decoder 16, 26 ... FIFO memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-56-116138 (JP, A) JP-A-58-64534 (JP, A) JP-A-63-204352 (JP, A)

Claims (12)

(57) [Claims] 1. A method for transferring data from a first circuit connected to a data bus and an address bus of a CPU to a second circuit connected to the data bus and an address bus, the first circuit comprising: Includes a first memory circuit and a first control circuit, the second circuit includes a second memory circuit and a second control circuit, and the CPU reads data from the first control circuit. A signal is output and an address signal designating the first circuit is output to the address bus. The first control circuit, based on the read signal and the address signal, outputs a series of a plurality of signals in a unit cycle. The read enable signal is generated, the first storage circuit sequentially outputs the stored data based on the plurality of read enable signals to the data bus, and the second control circuit outputs the read signal and the address signal. On the basis of the plurality of read enable signals, a series of a plurality of write enable signals are generated, and the second memory circuit sequentially takes in the data on the data bus based on the plurality of write enable signals. A data transfer method characterized by storing in. 2. The data transfer method according to claim 1, wherein the second control circuit outputs a wait signal to the CPU so that the data transfer can be completed during the unit cycle. Data transfer method. 3. A method of transferring data from a first circuit connected to a data bus and an address bus of a CPU to a second circuit connected to the data bus and an address bus, the first circuit Includes a first memory circuit and a first control circuit, the second circuit includes a second memory circuit and a second control circuit, and the CPU reads data from the first control circuit. A signal is output and an address signal designating the first circuit is output to the address bus, and the first control circuit generates a first read enable signal based on the read signal and the address signal, The first memory circuit outputs the stored data to the data bus based on the first read enable signal, and the second control circuit outputs the first write enable based on the read signal and the address signal. Signal And the divided signal is generated based on the first write enable signal and the delayed read signal obtained by delaying the read signal from the CPU for a predetermined time, and the second memory circuit is configured to generate the divided signal based on the first write enable signal. The data on the data bus is fetched and stored, and the first control circuit outputs the second read enable signal separated from the first read enable signal based on the division signal of the second control circuit during a unit cycle. The first storage circuit outputs the next data stored based on the second read enable signal to the data bus, and the second control circuit writes the first data based on the division signal. Data characterized in that a second write enable signal separated from the enable signal is generated, and the second memory circuit fetches and stores the next data on the data bus based on the second write enable signal. Transfer method. 4. A method for transferring data from a first circuit connected to a data bus and an address bus of a CPU to a second circuit connected to the data bus and an address bus, the first circuit Includes a first memory circuit and a first control circuit, the second circuit includes a second memory circuit and a second control circuit, and the CPU reads data from the first control circuit. A signal is output and an address signal designating the first circuit is output to the address bus, and the first control circuit generates a first read enable signal based on the read signal and the address signal. , The divided signal is generated based on the first read permission signal and the delayed read signal obtained by delaying the read signal from the CPU for a predetermined time, and the first memory circuit stores the divided signal based on the first read permission signal. The second control circuit generates the first write enable signal based on the read signal and the address signal, and the second storage circuit outputs the first write enable signal. Based on the divided signal, the first control circuit generates a second read permission signal separated from the first read permission signal based on the division signal, and the first control circuit generates the first read permission signal. The circuit outputs the next data stored based on the second read enable signal to the data bus, and the second control circuit outputs the first write enable based on the division signal of the first control circuit. A second write enable signal separated from the signal is generated in a unit cycle, and the second memory circuit captures and stores the next data on the data bus based on the second write enable signal. Characteristic data transfer method. 5. The data transfer method according to claim 1, 2, 3 or 4, wherein the first or second memory circuit is a first-in first-out memory. 6. The data transfer method according to claim 1, 2, 3 or 4, wherein the first or second memory circuit is a memory by addressing, and the address signal specifies a higher address. A data transfer method characterized in that a lower address signal for designating a lower address is given to the memory designated by the address. 7. A system for transferring data from a first circuit connected to a data bus and an address bus of a CPU to a second circuit connected to the data bus and an address bus, the first circuit Is based on the first address decoder that outputs the first address match signal when the address signal on the address bus matches its own address, and the read signal from the CPU and the first address match signal during the unit cycle. A read enable signal generation circuit that generates a series of read enable signals; and a first storage circuit that receives the read enable signals and sequentially outputs the stored data to a data bus, The second circuit is a second address decoder that outputs a second address match signal when the address signal on the address bus matches its own address. A second address decoder that makes its own address the same as the address of the first circuit, and a series of plural addresses corresponding to the read enable signal based on the read signal and the second address match signal from the CPU. And a second memory circuit for receiving a plurality of write enable signals and sequentially storing the data on the data bus, the data transfer comprising: system. 8. The data transfer system according to claim 7, wherein the second circuit includes a wait signal generation circuit that outputs a wait signal to the CPU so that the data transfer can be completed during the unit cycle. A data transfer system characterized in that 9. A system for transferring data from a first circuit connected to a data bus and an address bus of a CPU to a second circuit connected to the data bus and an address bus, the first circuit Is a first address decoder that outputs a first address match signal when the address signal of the address bus matches its own address, a read signal from the CPU, a first address match signal, and a second address match signal.
A read permission signal generation circuit that generates a series of first read permission signal and second read permission signal in a unit cycle based on the divided signal from the circuit of FIG. A first memory circuit that sequentially outputs the stored data to the data bus is provided, and the second circuit outputs a second address match signal when the address signal of the address bus matches its own address. A second address decoder which outputs the second address decoder which makes its own address the same as the address of the first circuit, and a division based on a read signal from the CPU and a second address coincidence signal. A write enable signal generation circuit for generating a signal and a series of first write enable signal and second set-in enable signal, and first and second write enable signals Receiving, the data transfer system, characterized in that it comprises a second memory circuit for sequentially storing the data on the data bus, the. 10. A system for transferring data from a first circuit connected to a data bus and an address bus of a CPU to a second circuit connected to the data bus and an address bus, the first circuit Is a first address decoder that outputs a first address match signal when the address signal on the address bus matches its own address, and a division signal is generated based on the read signal from the CPU and the first address match signal. At the same time, the read enable signal generation circuit for generating a series of first read enable signal and second read enable signal and the first and second read enable signals are received, and the stored data is sequentially output to the data bus. The first memory circuit and the second memory circuit are provided. When the address signal of the address bus matches its own address, the second circuit A second address decoder which outputs a coincidence signal, the second address decoder having its own address the same as the address of the first circuit, a read signal from the CPU, a second address coincidence signal and a second address coincidence signal 1
A write enable signal generating circuit that generates a series of first write enable signal and second write enable signal in a unit cycle based on the divided signal from the circuit of FIG. A second memory circuit that receives and sequentially stores the data on the data bus, and a data transfer system. 11. The data transfer system according to claim 7, 8, 9 or 10, wherein the first or second memory circuit is a first-in first-out memory. 12. The data transfer system according to claim 7, 8, 9 or 10, wherein the first or second memory circuit is a memory by addressing, and the address signal is for designating an upper address. A data transfer system characterized in that a low-order address signal designating a low-order address is given to the memory specified by the address.