JP2545461B2 - Complementary MOS circuit - Google Patents

Description

DETAILED DESCRIPTION [Overview] A complementary MOS circuit in which outputs of a plurality of tri-state circuits are wired-OR connected to each other, and instantaneous current is prevented from occurring, current consumption is reduced, and power line noise is prevented from occurring. And a first and a second inverter having a complementary MOS structure for the purpose of providing a complementary MOS circuit for
Complementary MO with the outputs of the first and second tri-state circuits consisting of the transmission gate of
In the S circuit, the drains of the P-channel MOS transistor and the N-channel MOS transistor of the first and second inverters are the same as those of the first and second transmission gates in the first and second tri-state circuits. Channel MOS
The drains of the P-channel MOS transistor and the N-channel MOS transistor of the first and second inverters are connected to the source or the drain of the transistor, respectively, and the first and second transmission gates have positive phase. The control signal line and the control signal line of the opposite phase delayed from the control signal line are commonly connected.

[Industrial applications]

The present invention relates to a complementary MOS circuit, and more particularly to a complementary MOS circuit in which outputs of a plurality of tri-state circuits are connected by wired OR.

Conventionally, a CMOS latch circuit or the like has been known as a complementary MOS (CMOS) circuit in which outputs of a plurality of tri-state circuits are wired or connected.

[Conventional technology]

FIG. 5 shows a circuit diagram of an example of a conventional CMOS latch circuit.

In the figure, the signal input to the terminal 10 is inverted by an inverter 11 which is composed of a P-channel MOS transistor QP1 and an N-channel MOS transistor QN1 (hereinafter, P-channel MOS transistor is referred to as QP and N-channel MOS transistor is referred to as QN). After that, the MOS transistors QP2, Q pass through the transmission gate 12 formed by the MOS transistors QP5, QN5.
It is supplied to the inverter 13 composed of N2, inverted here and output from the terminal 14.

The output of the inverter 13 is inverted by the inverter 15 composed of MOS transistors QP3, QN3 having large conduction resistance, and then fed back to the input of the inverter 13 through the transmission gate 16 composed of MOS transistors QP6, QN6. It constitutes a latch loop.

The clock φ shown in FIG. 6A is supplied from the terminal 17 to the MOS transistors QP5 and QN6 of the transmission gates 12 and 16, respectively. The inverted clock shown in FIG. 6B which is inverted by the inverter 18 is supplied.

When the clock φ is L level, the transmission gate 12 is conductive, the transmission gate 16 is cut off and the input signal IN is output as it is as the output signal OUT, and when the clock φ is H level, the transmission gate 12 is cut off and the transmission gate 16 is conductive. Then, the signal held in the latch loop composed of the inverters 13 and 16 and the transmission gate 16 is output as the output signal OUT. 6C and 6D show the input signal IN and the output signal OUT, respectively.

[Problems to be Solved by the Invention]

The inverted clock is slightly delayed with respect to the clock φ shown in FIG. 6 (A) due to the operation delay of the inverter 18, as shown in FIG. 6 (B). Therefore, after the clock φ falls, both the transmission gates 12 and 16 are transiently turned on in the period t shown in FIG. 5 until the inverted clock rises.

Here, when the clock φ is at the H level and the output signal OUT is at the L level, the input signal is at the H level, and during the period t when the clock φ shifts to the L level, the conductive MOS transistors QP3, QP6, QP5, A current path is formed in the path of QN1, and a large current flows instantaneously.

This instantaneous current has a problem that not only the consumption current increases but also noise is generated in the power supply line, which may cause malfunction of the device.

The present invention has been made in view of the above points, and an object of the present invention is to provide a complementary MOS circuit that prevents generation of an instantaneous current, reduces current consumption, and prevents generation of noise in a power supply line.

[Means for solving the problem]

The complementary MOS circuit of the present invention comprises a first and second inverter and a first and second inverter having a complementary MOS structure.
Complementary MO with the outputs of the first and second tri-state circuits consisting of the transmission gate of
In the S circuit, the drains of the P-channel MOS transistor and the N-channel MOS transistor of each of the first and second inverters are connected to the same channel of each of the first and second transmission gates in the first and second tri-state circuits. Connect to the source or drain of the MOS transistor, open the drains of the P-channel MOS transistor and the N-channel MOS transistor of the first and second inverters, and control the positive phase of the first and second transmission gates. It is commonly connected to the signal line and the control signal line of the opposite phase delayed from the signal line.

[Action]

In the circuit of the present invention, the P channel MOS of the inverter
Since the drains of the transistor and the N-channel MOS transistor are open, even if the MOS transistors of different channels are simultaneously turned on by a plurality of wired-OR connected transmission gates, a current path is not formed and the occurrence of an instantaneous current can be prevented. .

〔Example〕

FIG. 1 shows a circuit diagram of a first embodiment of the circuit of the present invention. 5, the same parts as those in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted.

In Fig. 1, terminal 10 input signal IN is MOS transistor QP1, Q
After being inverted by the first inverter 21 formed by N1, it is supplied to the inverter 13 through the first transmission gate 22 formed by the MOS transistors QP5 and QN5. The output of the inverter 13 is inverted by the inverter 25 composed of the MOS transistors QP3 and QN3, and then supplied to the inverter 13 through the output of the transmission gate 22 composed of the MOS transistors QN6 and QP6 and the transmission gate 26 connected to the wired OR. .

The drains of the MOS transistors QP1 and QN1 are not short-circuited in the inverter 21 and the transmission gate 22, and the drain of the P-channel MOS transistor QP1 is connected only to the source (or drain) of the same P-channel MOS transistor QP5, and the N-channel MOS transistor QN1. Is connected only to the sources (or drains) of the same P-channel MOS transistor QN5, and the drains (or sources) of the MOS transistors QP5 and QN5 are short-circuited.

Similarly, the drains of the MOS transistors QP3 and QN3 are not short-circuited by the second inverter 25 and the second transmission gate 26, and the drain of the P-channel MOS transistor QP3 is only connected to the source (or drain) of the same P-channel MOS transistor QP6. The drains of the N-channel MOS transistors QN3 are connected only to the sources (or drains) of the same P-channel MOS transistor QN6, and the drains (or sources) of the MOS transistors QP6 and QN6 are short-circuited.

Here, when the clock φ is at the H level and, for example, the output signal OUT is at the L level, the input signal becomes the H level, and during the period t when the clock φ shifts to the L level, the MOS
Each of the transistors QP3, QP6, QP5, QN1 becomes conductive, but since the MOS transistors QP5, QN1 are not connected, no current path is formed and generation of an instantaneous current is prevented.

Further, when the clock φ is at the H level and, for example, the output signal OUT is at the H level, the input signal becomes the L level, and during the period t when the clock φ shifts to the L level, the MOS
Each of the transistors QP1, QP5, QP6, QN3 becomes conductive, but since the MOS transistors QP6, QN3 are not connected, no current path is formed and generation of an instantaneous current is prevented.

As described above, since the instantaneous current is prevented, the current consumption is reduced and the noise of the power supply line can be prevented.

The semiconductor pattern layout of the circuit of FIG. 1 is shown in FIG. In the figure, after the gate electrodes 30 to 36 are formed of polysilicon or the like, a P type diffusion layer 37 and an N type diffusion layer 38 are formed, and the gate electrodes 30a, 31a, 32a, 33a, 34a, 35a are respectively formed of MOS.
The gates of the transistors QP4, QP1, QP5, QP6, QP3, QP2 are respectively gate electrodes 30b, 31b, 36b, 32b, 34b, 35b are the gates of the MOS transistors QN4, QN1, QN5, QN6, QN3, QN2. is there. The power supply wirings 40 and 41 and the signal wirings 42 to 47 shown in satin are connected to the gate electrode and the diffusion layer by the contact portions shown by hatching.

Here, the semiconductor pattern layout of the conventional circuit of FIG. 4 is shown in FIG. In FIG. 3, the MOS transistor Q
A signal wire 50 is provided to connect the drains of P1 and QN1, and a signal wire 51 is provided to connect the drains of the MOS transistors QN6 and QP6.

As described above, in the circuit of the present invention shown in FIG. 2, since the signal wirings 50 and 51 in the conventional circuit are unnecessary, the pattern area can be reduced.

FIG. 4 shows a circuit diagram of a second embodiment of the circuit of the present invention. This circuit is an output selection circuit.

In the figure, the input signal IN1 of the terminal 60 is the MOS transistor QP1.
After being inverted by the inverter 61 constituted by 1, QN11, it is supplied to the inverter 63 constituted by the MOS transistors QP15, QN15 through the transmission gate 62 constituted by the MOS transistors QP12, QN12. The input signal IN2 at terminal 64 is MOS
After being inverted by the inverter 65 formed by the transistors QP13 and QN13, it is supplied to the inverter 63 through the output of the transmission gate 62 formed by the MOS transistors QN14 and QP14 and the transmission gate 66 connected by wired OR.

The select signals S from the terminal 67 are supplied to the MOS transistors QP12 and QN14 of the transmission gates 62 and 66, respectively, and the inverters in which the select signals S are supplied to the MOS transistors QN12 and QP16 respectively.
The inverted select signal inverted in 68 is supplied.

When the select signal S is L level, the transmission gate 62 is conductive, the transmission gate 66 is cut off, the input signal IN1 is selected and output from the terminal 69 as the output signal OUT, and when the select signal S is H level, the transmission gate 62 is cut off. , Transmission gate 66
Are conducted and the input signal IN2 is selected and output as the output signal OUT.

Again, inverter 61, transmission gate 6
In 2, the drains of the MOS transistors QP11 and QN12 are not short-circuited, the drain of the P-channel MOS transistor QP11 is connected only to the source (or drain) of the same P-channel MOS transistor QP12, and the drain of the N-channel MOS transistor QN11 is the same P. Only connected to the source (or drain) of the channel MOS transistor QN12,
The drains (or sources) of the transistors QP12 and QN12 are short-circuited.

Similarly in the inverter 65 and the transmission gate 66, the drains of the MOS transistors QP13 and QN13 are not short-circuited.

Also here, when the select signal S falls from the H level, a current path is not formed even if the MOS transistors QP12 and QP14 are transiently turned on. Similarly, when the select signal S rises from the L level, the MOS is transiently changed. Even if the transistors QN12 and QN14 are turned on, no current path is formed and no instantaneous current is generated.

〔The invention's effect〕

As described above, according to the complementary MOS circuit of the present invention, generation of an instantaneous current can be prevented, current consumption can be reduced, and noise generation in a power supply line can be prevented, which is extremely useful in practice.

[Brief description of drawings]

 FIG. 1 is a circuit diagram of a first embodiment of a circuit of the present invention, FIG. 2 is a pattern layout of the circuit of the present invention, FIG. 3 is a pattern layout of a conventional circuit, and FIG. 4 is a second embodiment of the circuit of the present invention. Circuit diagram, FIG. 5 is a circuit diagram of an example of a conventional circuit, and FIG. 6 is an operation waveform diagram of the conventional circuit. In the figure, 13,18,21,23,61,63,65,68 are inverters, 22,26,62,66 are transmission gates, QP1 to QP16 are P-channel MOS transistors, and QN1 to QN16 are N-channel MOS transistors. Show.

Claims (1)

(57) [Claims] 1. Complementary MOS structure first and second inverters (2
1,25) and the first and second transmission gates (22,2
In a complementary MOS circuit in which the outputs of the first and second tri-state circuits consisting of 6) are wired-OR connected, the P-channel M of each of the first and second inverters (21, 25)
The drains of the OS transistor and the N-channel MOS transistor are respectively connected to the first and second tristate circuits in the first and second tristate circuits.
A second transmission gate (22, 26) is connected to the sources or drains of the same-channel MOS transistors of each, and the P-channel MOS transistor and the N-channel MOS transistor of each of the first and second inverters (21, 25) are connected. The drains are opened, and the first and second transmission gates (22, 26) are commonly connected to a positive-phase control signal line and a negative-phase control signal line delayed therefrom. Complementary form
MOS circuit.