JP2545907B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method for manufacturing a field effect transistor having a tungsten gate, the method comprising: forming a tungsten nitride film on a surface of a tungsten film for the purpose of forming finely and with high quality; It is characterized in that a step of laminating a silicon oxide film on the tungsten nitride film and simultaneously patterning the silicon oxide film, the tungsten nitride film and the tungsten film to form a gate electrode is included.

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a field effect transistor having a tungsten gate.

A MOS transistor is a typical field effect transistor, and a semiconductor integrated circuit (MOSIC) including the MOS transistor is widely used in a logic circuit such as a memory or a calculation. Such MOSICs are being miniaturized more and more, and for that reason, use of electrode wiring materials having lower resistance to increase the resistance and lower the resistance is being promoted.

[Prior Art] FIGS. 2A and 2B have a tungsten gate.
A cross-sectional view of a MOS transistor is shown, 1 is a p-type silicon substrate,
2 is a gate insulating film, 3 is a gate electrode made of tungsten (W), 4 is a silicon nitride (Si ₃ N ₄ ) film, 5 is a silicon oxide (SiO ₂ ) film such as a field insulating film, and 6 is an n ⁺ type Source or drain region, 7 is phosphorus silicate glass (PSG) film, 8
Is the aluminum (Al) wiring derived from the drain region, 9
Is an aluminum (Al) wiring derived from the gate electrode.

2A is a sectional view of a general MOS transistor, and FIG. 2B is a sectional view showing a drain region and a gate electrode portion (a sectional view taken along a broken line). This is to explain the subsequent forming steps with the cross section of FIG. 2 (b). The Si ₃ N ₄ film 4 is the gate electrode 3
It also surrounds the perimeter of the side wall with Si ₃ N
_{This is because} the LDD structure formed of _four films is illustrated.

By the way, as is well known, the method of forming a MOS transistor is such that a gate insulating film and a gate electrode are first formed,
A method is adopted in which source / drain regions are formed by self-aligned (self-aligned) ion implantation using the gate electrode and the field insulating film as a mask.

Therefore, since the wirings 8 and 9 are formed in a relatively later process, it is possible to reduce the resistance by using aluminum having a low melting point, but the gate electrode 3 is formed in the initial process. In addition, it is difficult to use aluminum having a low melting point, and thus, in the past, a conductive polycrystalline silicon film was used as the gate electrode.

However, it is required to reduce the resistance of the gate electrode, and tungsten silicide (WSi ₂ ) or molybdenum silicide (MoSi ₂ ) is used instead of the conductive polycrystalline silicon film.
Refractory metal silicide films such as the above have come to be used, and this has the effect of temporarily lowering the resistance. However, recently, as ICs have become more highly integrated and miniaturized, it is desired that the gate electrode also have a lower resistance, and tungsten (W) itself has been used as the gate electrode.
This tungsten film is a material that can reduce the resistance value by about one digit as compared with the tungsten silicide film.

However, when tungsten is deposited as a gate electrode film, and a SiO ₂ film is deposited and covered thereon by a chemical vapor deposition (CVD) method, both are simultaneously patterned to form a gate electrode, There is a problem that the side etching of the gate electrode progresses, and instead of the SiO ₂ film, a Si ₃ N ₄ film is used as a C
It has been found that when the VD method is applied and coated, and at the same time patterned to form a gate electrode, side etching does not proceed and an undercut does not occur. FIGS. 3 (a) and 3 (b) are views showing the conventional problems, and FIG. 3 (a) shows the case where the SiO ₂ film 5 is coated, and FIG. ₃ (b) shows the Si ₃ N ₄ film.
When the film 4 is covered, 10 is a resist film mask, and symbols of other members are the same as those in FIG.

The reason why the SiO ₂ film 5 and the Si ₃ N ₄ film are coated on the tungsten gate electrode and patterned at the same time is to perform ion implantation for defining the source and drain regions after forming the gate electrode. The problem is that tungsten alone does not function as an ion implantation shielding film (mask) and the implanted ions are channeled (transmitted), so that the source and drain regions cannot be formed in a self-aligned manner.

[Problems to be Solved by the Invention] FIGS. 4A to 4D show a conventional method (I) for forming a MOS transistor having a tungsten gate in which such Si ₃ N ₄ films are stacked. The process will be described with reference to sectional views, and the problems thereof will be described at the same time.

FIG. 4 (a); First, a field insulating film made of a SiO ₂ film 5 is formed on the p-type silicon substrate 1 by a known manufacturing method, and the gate insulating film 2 and the tungsten gate electrode are formed.
3, Si ₃ N ₄ film 4 is deposited and patterned at the same time, and Si ₃ N ₄ becomes a side wall on the side surface of the gate electrode.
The film 4 is formed. Next, using these as a mask, arsenic ions are implanted to define the n ⁺ type source and drain regions 6, and the PSG film 7 (cover film) is further covered over the entire surface.

Although the MOS transistor element is completed as described above, next, the Al wiring derived from this element is formed.

4 (b); accordingly, the surface is covered with the resist film mask 11 exposing the connection wiring portion, and the PSG film 7 is subjected to vertical reactive ion etching (RIE) with a fluorine (F) -based gas. .

See FIG. 4 (c); then, with the mask as it is, Si is mixed with a mixed etching gas of F-based gas and oxygen (O ₂ ) gas.
The O ₂ film 5 is etched to finish the opening of the n ⁺ type drain region 6.

See FIG. 4 (d); however, since the Si ₃ N ₄ film 4 on the tungsten gate electrode 3 is difficult to be etched even if the drain region is opened, the etching is continued or the etching gas is changed. , The Si ₃ N ₄ film is etched with, for example, sulfur hexafluoride (SF ₆ ) to finish the opening of the window for connection with the gate electrode.

However, since the SiO ₂ film and the Si ₃ N ₄ film have different etching ratios with the same gas, the surface of the drain region may be over-etched, or, depending on the type of etching gas, the gate may be reversed. The electrodes may be over-etched.

Therefore, at present, the above-described photo process of opening two windows with one resist film mask at the same time is not used, but two photo processes of opening two windows by providing separate resist film masks are performed. The connection wiring is formed.

5 (a) and 5 (b) show sectional views in order of the steps of the forming method (II), and the formation of the MOS transistor element is the same as the method described in FIG. hand,
Only the method of forming the wiring will be described. Moreover, the same parts as those in FIG. 4 are designated by the same symbols.

See FIG. 5 (a); First, a resist film mask 12 is formed in which only the wiring portion connected to the drain region is exposed, and RI is formed.
Etch by the E method to open a window for the drain wiring part.

FIG. 5B; Next, a resist film mask 13 exposing the wiring portion connected to the tungsten gate electrode is formed and etched by the RIE method to open a window for the wiring portion connected to the gate electrode.

According to the forming method applying the two photo processes,
There is no need to worry about overetching the connection surface, and the connection surface can be opened smoothly and accurately. However, since the patterning is performed twice, it is necessary to consider the alignment error, and as a result, there is a drawback that the miniaturization of the IC is hindered and the processing man-hour is increased accordingly.

The present invention solves such a problem and finely forms a semiconductor device having a gate electrode made of tungsten,
In addition, it proposes a manufacturing method aiming at forming with high quality.

[Means for Solving the Problems] The purpose is to form a tungsten nitride film on the surface of a tungsten film, and then stack a silicon oxide film on the tungsten nitride film to form a silicon oxide film, a tungsten nitride film, and This is achieved by a manufacturing method including a step of simultaneously patterning the tungsten film to form a gate electrode.

[Operation] That is, according to the present invention, the tungsten nitride film is formed on the surface of the tungsten gate electrode, and the insulating film covering the tungsten gate electrode is replaced with the SiO ₂ film instead of the Si ₃ N ₄ film.

Then, since the tungsten nitride film is present,
The tungsten gate electrode can be formed without undercutting, and the electrode window is opened at the same time so that the window surface is formed flat without being over-etched.

[Examples] Hereinafter, examples will be described in detail with reference to the drawings.

1 (a) to 1 (e) show sectional views in order of steps of a forming method according to the present invention, which will be described in order.

See FIG. 1 (a); the gate insulating film 2 is formed on the p-type silicon substrate 1 provided with the field insulating film made of the SiO ₂ film 5.
Tungsten film 3 (film thickness 2000-
3000 Å) is deposited by the sputtering method.

See FIG. 1 (b); then, heat treatment is performed in ammonia (NH ₃ ) gas at 700 to 800 ° C. to transform the surface of the tungsten film 3 into a tungsten nitride film 23, and the SiO ₂ film 24 is formed thereon.
Deposition (film thickness of about 500Å) by chemical vapor deposition (CVD) method. The tungsten nitride film 23 is an extremely thin film having a film thickness of 100 Å or less.

1 (c); then, the SiO ₂ film 24, the tungsten nitride film 23 and the tungsten film 3 are simultaneously etched by a photo process using the resist film mask 14,
A tungsten gate electrode 3 portion is formed. At this time, since the tungsten nitride film 23 exists on the tungsten film 3, side etching does not occur even if etching is performed with the SiO ₂ film 24 being covered.

See FIG. 1 (d); next, a SiO ₂ film 24 serving as a sidewall is also formed on the side surface of the gate electrode, and these SiO ₂ films are formed.
5, 24 and the gate electrode 3 are used as a mask to implant arsenic ions to define the n ⁺ type source and drain regions 6, and
The entire surface is covered with the PSG film 7 (cover film). At this time, due to the heat treatment for defining the source / drain regions, the SiO ₂ film 25 having a film thickness of about 500 Å is formed on the source / drain regions, and the same film as the SiO ₂ film 24 on the gate electrode is formed. Become thick. Note that the source region 6 is not shown in the figure for the sake of cross section.

See FIG. 1 (e); then, the connection wiring portions of both the gate electrode and the drain region are covered with the exposed resist film mask 15, and the PSG film 7 and the SiO ₂ films 24 and 25 are vertically formed.
Etching by RIE method. At this time, the etching gas is F
A mixed gas of a system gas and an O ₂ gas is used. Then, the SiO ₂ film 25 on the drain region and the SiO ₂ film 24 on the gate electrode have almost the same film thickness, and the PSG film 7 also has the same film thickness. The connection wiring portion of the drain region is also opened at the same time, and the connection surface is not over-etched.

After that, a wiring connecting to the gate electrode and the drain region is formed to complete the shape similar to that shown in FIG. In this case, although tungsten nitride is interposed in the tungsten gate electrode, this tungsten nitride has a lower resistance than tungsten silicide, and since the film thickness is extremely thin, there is no fear of increasing wiring resistance. .

The above is the outline of the forming method according to the present invention. According to such a forming method, the connection wiring of the gate electrode and the connection wiring of the drain region are simultaneously opened in one photo process, and the connection is made. Since the surface is not over-etched, there is no problem of hindering the miniaturization of IC, the quality is improved, and the processing man-hour can be reduced.

[Effects of the Invention] As is clear from the above description, according to the forming method of the present invention, in a MOSIC including a MOS transistor having a tungsten gate, it contributes to miniaturization and high quality, and its cost It is also useful for reducing.

[Brief description of drawings]

1 (a) to 1 (e) are sectional views in order of the steps of the forming method according to the present invention, and FIGS. 2 (a) and 2 (b) are MOs having a tungsten gate.
Sectional view of the S-transistor, FIG. 3 is a view showing a conventional problem, FIGS. 4 (a) to 4 (d) are cross-sectional views in order of steps of the conventional forming method (I), FIG. 5 (a), (B) is a process order sectional view of the conventional forming method (II). In the figure, 1 is a p-type silicon substrate, 2 is a gate insulating film, 3 is a tungsten gate electrode or a tungsten film, and 4 is Si ₃ N.
₄ films, 5, 24, 25 are SiO ₂ films, 6 are n ⁺ type source and drain regions, 7 are PSG films, 8 and 9 are aluminum (Al) wiring, 10 and 1
1, 12, 13, 14, and 15 are resist film masks, and 23 is a tungsten nitride film.

Claims (1)

(57) [Claims] 1. A tungsten nitride film is formed on a surface of a tungsten film, a silicon oxide film is laminated on the tungsten nitride film, and the silicon oxide film, the tungsten nitride film and the tungsten film are simultaneously patterned. A method of manufacturing a semiconductor device, comprising the step of forming a gate electrode.