JP2545993B2 - Transposed transversal equalizer - Google Patents

Description

The present invention relates to a correlator that constitutes a transposed transversal equalizer.

Since digital radio lines tend to be multivalued, a transversal equalizer in a demodulator is indispensable.

On the other hand, in order to improve the performance of the transversal equalizer, it is necessary to have a transversal equalizer capable of high-speed processing. When processing the input signal as a suitable one, tap the adder The transposed transversal equalizer inserted between the two has come into practical use.

As the digital radio line has become multi-valued and the number of opportunities to use this transposed transversal equalizer has increased, a more compact and simple correlator has been required.

[Conventional technology]

FIG. 5 is a diagram illustrating a usage example of a transversal equalizer, FIG. 6 is a diagram illustrating a processing state of a received signal in digital wireless communication, and FIG. 7 is a conventional example of a transversal equalizer. FIG. 8 and FIG. 8 are views for explaining a conventional example of a correlator for transversal equalizer.

FIG. 5 shows a receiver (hereinafter referred to as RX) 1 for receiving and processing digital wireless communication signals, and an analog / digital converter (hereinafter referred to as A / D converter) 21 for demodulating a signal received by RX1. And a demodulation device 2 having a transversal equalizer 22 and a switching device 3 for switching and transmitting a reception signal to a plurality of transmission lines.

The radio signal received by RX1 is an analog signal, and the A / D converter 21 in the demodulator 2 converts this to a digital signal.

FIG. 6 shows the situation when the digital signal is converted by the A / D converter 21, and FIG. 6 (A) shows that the digital signal at the time of transmission is “high” (the binary level of the signal is “low”). Is displayed at, and indicates a level higher than "low") (6th
The analog signal of (the digital signal at that time is shown in FIG. 6B) is shown by a solid line, and then the analog signal in the case where the "high" of the digital signal continues as shown by the dotted line of FIG. Shows.

The vertical line in FIG. 6A indicates the reception level, and the horizontal line indicates the time t. Then, when the first analog waveform represented by the solid line is at the peak level, the next analog waveform represented by the dotted line becomes zero level, and the first analog waveform is shown as an ideal state in which there is no influence from the next analog waveform.

The point at t = 0 (when the waveform is at the peak level) shown in FIG. 6 (A) is the sampling point when the analog signal is digitized, and the solid line waveform is at the maximum level (b) at the reference level (a). ) (Becomes a threshold level) and the waveform of the dotted line is at a zero level (corresponding to the reference level (a)), the above-mentioned ideal state is obtained.

However, there is usually no ideal state, so the A / D converter 21 determined according to the following procedure converts an analog signal into a digital signal. That is, in the two waveforms shown in FIG. 6 (C), the high point side is deviated from the normal reference level (a) to the low point side as shown in FIG. 6 (D), and at t = 0 point at this time. If the digitized signal is deviated to the high point side, "1", "low"("L" in the figure) on the "high" side (shown as "H" in the figure and the same below)
, And the same applies hereinafter) is converted to "0".

This bit is called the most significant bit (hereinafter referred to as MSB), and this is the data signal x _i when inputting to the correlator.
In this example, the case where m = 1 is taken as an example.

Next, the deviation determination level is set to, for example, the threshold level (b), and whether the high point side or the low point side is determined in the same manner as above, "1" or "0" is displayed, and the threshold value is further displayed. The level (c), which is half the level (b), is set as the determination level, and the same processing as above is performed.

The number of times n of this judgment is performed depending on how the digital signal of the A / D converter 21 is converted with high accuracy.

That is, when the data input signal input to the transversal equalizer 22 is m = 3 to 4 bits, the digital signal output bit n of the A / D converter 21 is an output with accuracy higher than 3 to 4 bits. Become. That is, n> m.

Further, as shown in FIG. 6 (D), when m = 1, the bits below the MSB are set as the error signal ε _i , and the transversal equalizer is used.
The data input signal input to 22 is the data signal x _i (m
Bits) and error signal ε _i (n−m) bits.

Next, FIG. 7 shows a conventional example of the transversal equalizer 22, showing a case where the number of taps is 5, and the data input signal is an n-bit shift register 221a indicated by a Z ^-1 mark for each tap.
(1) to 221a (4) shift the timing.

Then, the n-bit shift registers a221 (1) to 221a
Correlator corresponding to each data input signal shifted in (4)
Control signals C _{0 to} C ₄ output from the 22c and ○ respectively
Is multiplied by the multipliers 222a (1) to 222a (5) indicated by x, and the result of the multiplication is added by the adder 223a as a data output signal. A discriminator 22b that discriminates how much error there is (corresponding to a sampling point), and an error discriminated by the discriminator 22b are provided to an m-bit shift register, a multiplier, an integrator, etc. together with the data signal x _i. And a correlator 22c for calculating control signals C _{0 to} C ₄ used for weighting in the data calculation unit 22a.

FIG. 8 is a diagram showing the structure of the correlator 22c described above, particularly the structure of the correlator 22c used in the transposed transversal equalizer 22. The structure is such that the data signal x _i is shifted by one bit and delayed. Let m
The bit shift registers 221c (1) to 221c (4) and the error signal ε _i are similarly delayed by 2 bits for timing (nm) bit shift registers 222c (1), 2
22c (2) and multipliers 223c (1) to 22c for multiplying the error signal ε _i by the data signal x _i delayed for each tap and timed.
3c (5) and the outputs of the multipliers 223c (1) to 223c (5)
Shift registers 224c (1) to 22c that perform the same bit shift as the number of bits of the control signal in order to adjust the timings so as to match the respective bit timings of 22a.
4c (4), 225c (1) to 225c (3), 226c (1), 226c
(2) and 227c (1) and integrators 228C (1) to 228c (5) indicated by the symbols surrounding S in a rectangle for integrating the outputs whose timings have been adjusted.
Is provided.

Shift registers 224c (1) to 224c (4), 225c (1)
The timing adjustment by 225c (3), 226c (1), 226c (2), 227c (1) is performed in order to add all the control signals C _{0 to} C ₄ at the same timing by the adder 223a in the data calculation unit 22a. Is adjusted, and when the transversal equalizer 5 is a tap as shown in FIG. 7,
As shown in FIG. 8, the timing is adjusted by using a shift register that shifts by the number of bits of the control signal.

[Problems to be Solved by the Invention]

The timing adjustment shift register used in the above correlator 22c is installed according to the number of bits of the control signal.

Normally, the number of bits of the control signal is 8 to 10 bits, and accordingly, 80 to 100 shift registers for timing adjustment are required in the case of 5 taps.

However, if the number of bits of the control signal increases, the number of timing adjustment shift registers will increase accordingly.

On the other hand, the transversal equalizer 22 is desired to have a high processing speed, and therefore a transposed transversal equalizer has been put into practical use. The correlator 22c requires many shift registers for timing adjustment. Moreover, if the number of shift registers for timing adjustment increases, the configuration becomes large in scale, and it becomes difficult to reduce the size.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a transposed transversal equalizer which has a short processing time and a small structure.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a correlator of a transposed transversal equalizer with first delay means for sequentially delaying the error signal by a constant time, and the data. A second delay means for delaying the signal by an integer multiple of the fixed time according to the number of taps, a plurality of data signals obtained by branching the output from the second delay means, and a first delay means. A correlating unit that correlates each of a plurality of error signals having different delay times, and an integrating unit that integrates the respective correlation results by the correlating unit and outputs the result as a control signal of each tap of the computing unit. The control signals are input to the taps of the arithmetic unit according to the delay time of the error signal used for correlation.

[Operation] With the configuration of the above means, the error signal side is sequentially delayed for a predetermined time, and thus a plurality of error signals having different delay times are obtained. Further, the data signal is delayed by a predetermined time according to the number of taps, these are correlated by the correlating means, and further integrated by the integrating means. Therefore, by sequentially delaying the error signal side, it is possible to reduce the size of the apparatus and shorten the processing time without requiring many shift registers as in the conventional case. Further, the correlation itself can maintain the same calculation as the conventional one.

[Embodiment] FIG. 1 is a view for explaining an embodiment of a correlator for transposed transversal equalizer of the present invention.

The correlator 225 for transposed transversal equalizer of the present invention shown in FIG. 1 has two m-bit shift registers 222f (1) and 222f (2) for timing the data signal x _i and an error signal ε _i Is delayed by 1 bit in accordance with the number of taps of the transposed transversal equalizer (l-1) (nm) bit shift registers 22f (1) to 221f (l
−1) and the multipliers 22 installed for the number of taps of the transversal equalizer for multiplying the data signal x _i and the error signal ε _i.
3f (1) to 223f (l) and integrators 224f (1) to 224f (l) for integrating the outputs of the multipliers 223f (1) to 223f (l), and a transposed transversal equalizer The control signal C _L-1 used for the tap having the longest delay of the data input signal among the control signals C _{0 to} C _L-1 used in the data calculation unit 22d of the error signal ε _i without timing adjustment and the data signal x. multiplying the _i, be configured to multiply the most error signal delayed by one bit in accordance with the process proceeds to a small control signal C ₀ side is tap delay epsilon _i and the data signal x _i of the data input signal Therefore, it is a means for solving this problem.

The data operation unit of the transposed transversal equalizer 22
22d puts the data input signal into the multiplier at the same timing, and outputs the control signals C ₀ to C from the correlator 22f of the present invention.
_It is configured to multiply by _L-1 and delay this by 1 bit from C _L-1 to extract the output signal.

Control signal C output from correlator 225 of the present invention
_The error signal ε _i is delayed by 1 bit in the same manner as the data operation unit 22d so that _{0 to} C _L-1 adjusts the output at the optimum timing for use in the operation of the data operation unit of the transpose transversal equalizer. By doing so, the number of shift registers can be minimized and the correlation operation can be processed at high speed.

Hereinafter, the gist of the present invention will be specifically described with reference to the embodiments shown in FIGS.

FIG. 2 is a diagram for explaining an embodiment for a transposed transversal equalizer of the present invention, and FIG. 3 is an integrator input and time when correlation is taken in the correlator for transposed transversal equalizer of the present invention. 4 and FIG. 4 are diagrams for explaining the relationship of the above, and FIG. 4 is a diagram for explaining the integration result in the correlator for transposed transversal equalizer of the present invention. The same reference numerals denote the same objects throughout the drawings.

The transposed transversal equalizer of the present invention shown in FIG.
22 is composed of a data calculation unit 22d, a correlator 22f, and a judging device 22e having the same structure as described in FIG. 7, and the judging device 22e performs the same operation as described in FIG. It is something to do.

The transposed transversal equalizer 22 described above has 5 taps as described in FIG. In addition, a data operation unit constituting the transposed transversal equalizer 22 of the present invention
22d includes five multipliers 221d (1) to 221d (5), five adders 222d (1) to 222d (5), and four (nm) shift registers 223d (1) to 223d
(4) and the above-mentioned correlator 22f is the same as the correlator 22f described in FIG.
It is an example when it was set to 5.

Data operation unit 22d of transposed transversal equalizer 22
N-bit data input signal to be input to
(Corresponding to the output of the D converter 21) is input to each of the multipliers 221d (1) to 221d (5) at the same timing.

Each multiplier 221d (5) ~221d (1) multiplies the respective control signals C ₄ -C ₀ from the correlator 22f and the data input signal.

That is, the output obtained by multiplying the uppermost control signal C ₄ and the data input signal by the multiplier 221d (5) is added by the adder 222d.
In addition to (5), the result of this addition is the next shift register 223d.
The output obtained by delaying at (4) and multiplying the output by the control signal C ₃ and the data input signal by the multiplier 221d (4)
The addition is performed by the adder 222d (4).

An output obtained by sequentially processing the control signal C ₀ and the data input signal by the multiplier 221d (1),
A result obtained by adding the above addition result by the adder 222d (1) is output as a data output signal.

The control signals C _{4 to} C ₀ described above are obtained by the correlator 22f, and the error signal ε _i at that time is the data output signal determined by the discriminator 22b.
Is a signal obtained by determining the deviation from the center level (referred to as the reference level (a)).

The deviation from the center level (referred to as the reference level (a)) is mainly due to fading occurring on the transmission path.

Therefore, the transposed transversal equalizer 22 is installed after the A / D converter 21, and the process of compensating for the signal shift due to this fading is performed by looking at the data output signal and using the control signal C ₄ ~ as the weighting for compensation. By multiplying C ₀ , compensation calculation is performed.

Correlator used in this transposed transversal equalizer 22
22f is a correlator 22 so that the control bits C _{4 to} C ₀ are output at the timings used by the above-mentioned data operation unit 22d.
Data signal x _i input to f is applied to each multiplier 2 at the same timing.
Put in 23f (5) -223f (1).

Then, the error signals are sequentially set to 1 from the component with the largest delay.
Bit-wise (nm) bit shift register 221f (4)
~ Delay at 221f (1).

Then, this error signal ε _i is multiplied by each of the multipliers 223f (5) to 22
It is placed in 3f (1) and multiplied by the data signal x _i, and the output is integrated by the corresponding integrators 224f (5) to 224f (1).

FIG. 3 is a diagram showing the time relationship between the data signal x _i and the error signal ε _i in the correlator 22f, and FIG. 4 is an integrator.
The output status of the control signals C _{4 to} C ₀ is shown as the result of integration at 224f (5) to 224f (1).

The control signals C _{4 to} C ₀ in FIG. ₄ have a time t = 0.
The control signal at ˜128 is represented by ε ₄ x ₀ to ε ₁₂₇ x _127, etc., and Σε _i x _i-4 obtained by integrating i = _{0 to 127} as an integrated value.
~ Σε _i x _i is output with a time difference of 1 bit at the time of t = 123 to 127 (a bar line under each ε _i x _i corresponding to the control signals C _{4 to} C _0). Represents it).

In this way, the control bits C _{4 to} C ₀
The error signal ε _i and the data signal x _i are output from the correlator 22f at 22d so as to be output at a timing corresponding to the timing of each tap.
It is possible to significantly reduce the number of shift registers by delaying the error signal ε _i by 1 bit and timing the signal by delaying the error signal ε _i .

〔The invention's effect〕

According to the present invention as described above, it is possible to provide a correlator for a transposed transversal equalizer, which has a simple configuration and can speed up the calculation processing time.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of a correlator for transposed transversal equalizer of the present invention, and FIG. 2 is a diagram for explaining an embodiment of a correlator for transposed transversal equalizer of the present invention. FIG. 4 is a diagram for explaining the relationship between the integrator input and time when correlation is taken in the correlator for transposed transversal equalizer of the present invention, and FIG. 4 is for the correlator for transposed transversal equalizer of the present invention. FIG. 5 is a diagram illustrating an integration result, FIG. 5 is a diagram illustrating a usage example of a transversal equalizer, FIG. 6 is a diagram illustrating a processing state of a received signal in digital wireless communication, and FIG. 7 is a transversal equalization. FIG. 8 shows a conventional example of a correlator, and FIG. 8 shows a conventional example of a correlator for transposed transversal equalizer. In the figure, 1 is RX, 2 is a demodulator, 3 is a switching device, 21 is an A / D converter, 22 is a transversal equalizer, 22a and 22d are data operation units, 22b and 22e are discriminators, 22c, 22f is a correlator, 221a (1) to 221a (4), 221c (1) to 221c (4), 221c
(1), 222c (2), 224c (1) to 224c (4), 225c
(1) ~ 225c (3), 226c (1), 226c (2), 227c
(1), 221f (1) to 221f (l-1), 222f (1), 222f
(2) is a shift register, 222a (1) to 222a (5), 223c (1) to 223c (5), 221d
(1) to 221d (5), 223f (1) to 223f (l) are multipliers, 223a, 222d (1) to 222d (5) are adders, 228c (1) to 228c (5), 224f (1) ) To 224f (l) are integrators, respectively.

Claims (1)

(57) [Claims] 1. A data arithmetic unit which is provided in a demodulation circuit for digital radio communication, has a plurality of taps, arithmetically processes a data input signal and outputs it as a data output signal, and a data signal which is the data output signal. And an error signal, a transversal transversal equalizer including a correlator that calculates a control signal used as weighting at each of a plurality of taps of the data calculation unit, wherein the correlator calculates the error signal First delay means for sequentially delaying by a constant time, second delay means for delaying the data signal by an integer multiple of the constant time according to the number of taps, and an output branched from the second delay means. Correlation means for respectively correlating a plurality of data signals and a plurality of error signals having different delay times output from the first delay means, and the correlation means And integrating means for integrating each of the correlation results and outputting as a control signal of each tap of the computing unit, wherein each control signal is dependent on the delay time of the error signal used for correlation. A transposed transversal equalizer, which is configured to be input to each tap of the arithmetic unit.