JP2546256B2 - Analog digital conversion circuit - Google Patents

Description

The present invention relates to an analog digital conversion circuit, for example, a video tape recorder (HDVT) for high definition television.
It is suitable for application to the time axis correction device of R).

B. SUMMARY OF THE INVENTION The present invention has a simple configuration in an analog digital conversion circuit by changing a reference voltage based on an error voltage between a DC voltage of an input signal and a divided voltage of a reference voltage used for analog digital conversion. Therefore, even if the DC voltage of the input signal fluctuates, the digital information of the signal level of the input signal can be obtained.

C Conventional Technology Conventionally, in HDVTR, color difference signals are respectively recorded on two recording tracks, and at the same time, the luminance signal is time-expanded and divided into two-channel luminance signals, which are respectively recorded on two recording tracks. There are things that have been made to do so.

As described above, in the signal processing circuit of the luminance signal divided into two channels, if the amplification factor of the signal processing circuit is different between the channels, the signal level of the luminance signal of the two channels obtained through the signal processing circuit. However, it is unavoidable that the DC voltage will be a value different from the initial value divided into two channels.

As a result, even if it is a luminance signal with the same signal level at the beginning,
The DC voltage of each channel becomes different, and when the luminance signal of the two channels is time-compressed and demodulated to the luminance signal of one channel, there is a problem that a correct luminance signal cannot be obtained.

Therefore, in this type of luminance signal divided into two channels, when dividing into two channels, a reference signal having a luminance level of 120 [%] is superimposed during the vertical blanking period, and Even if the DC voltage of the entire luminance signal fluctuates, it can be corrected by controlling the DC voltage to a predetermined value.

That is, in the HDVTR time axis correction device, the time axis fluctuation of the reproduction signal is corrected by sequentially converting the DC voltage of the reproduction signal obtained from each recording track into digital information and storing it in the temporary memory circuit.

Therefore, if the signal level of the reproduced 2-channel luminance signal fluctuates with respect to a predetermined DC voltage value, there is a problem that it becomes difficult to obtain digital information of a correct signal level.

Therefore, as shown in FIG. 2, in the analog digital conversion circuit used in the time axis correction device for HDVTR, an AGC (automatic gain control) circuit 1 is used,
The reference signal superimposed on the brightness signal SV is corrected to have a predetermined DC voltage value and then converted into digital information, so that even if the brightness signal SV with a changed DC voltage is input, the brightness signal SV The DC voltage value of is corrected to a predetermined value to obtain digital information of a correct value for the signal level of the luminance signal SV.

That is, the brightness signal SV divided into two channels is received by the AGC circuit 1, and the brightness signal SV1 output from the AGC circuit 1 is output to the analog digital conversion unit 2 and the clamp circuit 3.

The clamp circuit 3 clamps the DC voltage of the reference signal superimposed on the luminance signal SV1 at the timing of the clamp pulse CP and outputs it to the AGC circuit 1.

Based on the output of the clamp circuit 3, the AGC circuit 1 changes the gain so that the DC voltage value of the reference signal superimposed on the luminance signal SV1 becomes a predetermined value, and as a result, the DC voltage with respect to the signal level as a whole is changed. The brightness signal SV1 in which the fluctuation of the value is corrected to a predetermined DC voltage value is input to the analog digital conversion unit 2.

The analog digital conversion unit 2 converts the DC voltage value of the brightness signal SV1 into digital information DS at a timing synchronized with the brightness signal SV1 based on the reference voltage V _RB of the reference power supply 4 and a memory circuit (not shown). Output to.

Thus, since the DC voltage of the reference signal superimposed on the luminance signal SV is held at a predetermined value and then converted to digital information DS, even if the DC voltage of the input luminance signal SV fluctuates, the luminance signal SV It is possible to obtain the correct digital information DS for the signal level.

D The problem to be solved by the invention is that the DC voltage value of the reference signal thus set to the predetermined brightness level is detected and corrected so that the signal level of the brightness signal SV1 as a whole becomes the predetermined DC voltage value. In order to do so, in the AGC circuit 1, it is necessary to amplify a luminance signal having a wide frequency band without causing distortion, and to change the gain by following the output of the clamp circuit 3.

For this reason, in the AGC circuit 1, it is unavoidable that the configuration becomes complicated, and as a result, the configuration becomes complicated as a whole of the analog digital conversion circuit.

The present invention has been made in consideration of the above points, and even if a luminance signal whose DC voltage fluctuates with respect to the signal level is input, digital information having a correct value with respect to the signal level of the luminance signal is obtained. The present invention is intended to propose an analog digital conversion circuit with a simple structure that can be used.

E Means for Solving the Problems In order to solve the above problems, in the present invention, the reference voltage V _RB is _divided into voltage _dividing resistors R ₁ , R ₂ , R ₃ , R ₄ , R 5, ... R _k ,
R _{k + 1} , R _{k + 2} ... A plurality of reference _divided voltages V _RB1 , V _RB2 , V _RB3 , V _RB4 , ... V _RBk obtained by dividing by R ₂₅₅ and R ₂₅₆
V _{RBk + 1} ...... V _RB255 and V _RB256 are each a plurality of comparison circuits
COM ₁ , COM ₂ , COM ₃ , COM ₄ , ...... COM _k , COM _{k + 1} , ...... COM
₂₅₅ , COM ₂₅₆ , and a plurality of comparison circuits COM ₁ , COM ₂ , COM ₃ , COM ₄ , ...... COM _k , CO that receive the input signal SV on which the reference signal of a predetermined signal level is superimposed at a predetermined timing.
M _{k + 1} , ... COM ₂₅₅ , COM ₂₅₆ received, multiple comparison circuits CO
M ₁ , COM ₂ , COM ₃ , COM ₄ , ...... COM _k , COM _{k + 1} , ...... CO
Comparative output of M ₂₅₅ and COM ₂₅₆ DS ₁ , DS ₂ , DS ₃ , DS ₄ ...... DS _k , D
S _{k + 1} ...... In the analog digital conversion circuit 10 configured to convert the input signal SV into the digital information DS based on DS ₂₅₅ , DS ₂₅₆ , the predetermined reference _divided voltage V _RB3 and the reference signal DC voltage Error amplifier circuit 14 that detects the error voltage of
By changing the value of the reference voltage V _RB based on the output signal V _RB of the error amplification circuit 14, the signal level of the input signal SV is converted into digital information DS.

F action Detects an error voltage between the reference _divided voltage V _RB3 and the DC voltage of the reference signal of a predetermined signal level superimposed on the input signal SV, and changes the value of the reference voltage V _RB based on this detection result V _RB. By doing so, even when the input signal SV in which the DC voltage fluctuates with respect to the signal level is input, the predetermined comparison circuits COM ₁ , COM ₂ , COM ₃ , COM ₄ , ... COM _k , COM _{k + 1} , ...... CO
The M ₂₅₅ and COM ₂₅₆ are turned on, and thus digital information having a correct value for the signal level of the input signal SV can be obtained.

G Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 10 indicates an analog digital conversion circuit as a whole, and a 1-channel luminance signal SV is received by an analog digital conversion unit 12 via a clamp circuit 11 and also at inverting input terminals of error amplification circuits 13 and 14.

The analog digital conversion unit 12 includes 256 comparison circuits COM ₁ , COM ₂ , COM ₃ , COM ₄ , ... CO that operate in synchronization with the timing of the luminance signal SV1 output from the clamp circuit 11.
M _k , COM _{k + 1} , ... COM ₂₅₅ , COM ₂₅₆ , which is composed of a flash-type analog digital conversion circuit connected in parallel, and compares the luminance signal SV1 with each comparison circuit COM ₁ , COM ₂ , COM ₃ , CO
_{M 4, ...... COM k, COM} k + 1, subject to the inverting input terminal of the ...... COM _255, COM _256.

Further, the analog digital conversion unit 15 has 256 resistors, which are voltage dividing resistors connected in series and have the same resistance value.
R ₁ , R ₂ , R ₃ , R ₄ , R ₅ ...... R _k , R _{k + 1} , R _{k + 2} …… R ₂₅₅ , R ₂₅₆
And a reference voltage V composed of the output signal of the error amplification circuit 14
_RB is the resistance R ₁ , R ₂ , R ₃ , R ₄ , R ₅ ...... R _k , R _{k + 1} ......
By dividing by R ₂₅₅ and R ₂₅₆ , the resistance R ₁ ,
_{R 2, R 3, R 4} , R 5 ...... R k, R k + 1, R k + 2 ...... R 255, reference divided voltage of the reference voltage V _RB obtained from the connection point R ₂₅₆
V _RB1 , V _RB2 , V _RB3 , V _RB4 , ... V _RBk , V _{RBk + 1} ...
_Comparing V _RB255 and V _RB256 with each comparison circuit COM ₁ , COM ₂ , COM ₃ , COM ₄ ,
Supply to the non-inverting input terminal of COM _k , COM _{k + 1} , COM ₂₅₅ , COM ₂₅₆ .

Thus, accompanied to the change of the DC voltage of the luminance signal SV1 to the reference voltage V _RB connexion, serial comparison circuit COM ₁ at the timing of the luminance signal _{SV1, COM 2, COM 3,} COM 4, ...... COM k, CO
M _{k + 1} , ... COM ₂₅₅ , COM ₂₅₆ are turned on, and each comparison circuit CO
M ₁ , COM ₂ , COM ₃ , COM ₄ , ...... COM _k , COM _{k + 1} , ...... CO
256-bit digital information DS ₁ , DS ₂ , DS ₃ , DS ₄ ...... D whose logic level sequentially rises to logic "H" according to the DC voltage value of the brightness signal SV1 based on the comparison output of M ₂₅₅ and COM ₂₅₆
S _k , DS _{k + 1} ... DS ₂₅₅ , DS ₂₅₆ can be obtained.

The encoder circuit 15 uses the digital information DS ₁ , DS ₂ ,
_{DS 3, DS 4 ...... DS k} , receives a _{DS k + 1 ...... DS 255,} DS 256, and outputs this converted into digital information DS composed of a binary data of 8 bits.

The error amplifier circuit 13 receives the reference _divided voltage V _{RBk + 1} obtained from the connection midpoint of the resistors R _{k + 1} and R _{k + 2} at its non-inverting input terminal, and based on the timing of the sampling pulse SP, the clamp circuit. The pedestal-level DC voltage of the luminance signal SV1 and the error voltage VE of the reference _divided voltage V _{RBk + 1} are output as the clamp voltage to 11.

Therefore, through the clamp circuit 11, the DC voltage of the pedestal level can obtain the luminance signal SV1 clamped to the reference _divided voltage V _{RBk + 1} , and the DC voltage seems to have changed with respect to the signal level. Even if the luminance signal SV is input, the comparator circuit CO is used for the signal level of the pedestal level.
M _{k + 1} and the comparator circuit COM with a low reference divided voltage
Only ₂₅₅ and COM ₂₅₆ can be always on.

On the other hand, the error amplification circuit 14 receives the reference _divided voltage V _RB3 obtained from the connection midpoint of the resistors R ₃ and R ₄ at the non-inverting input terminal, and outputs the luminance signal SV1 based on the timing of the clamp pulse CP. The DC voltage of the superimposed reference signal and the error voltage of the reference voltage V _RB3 are detected. Further, the error amplification circuit 14 samples and holds the detection result, and the resistors R ₁ , R ₂ ,
Output as reference voltage V _RB of R ₃ , R ₄ , R ₅ ... R _k , R _{k + 1} , R _{k + 2} ... R ₂₅₅ , R ₂₅₆ .

Accordance connexion resistor R ₁ a reference voltage V _RB, as the value and is always equal to the DC voltage value and the reference divided voltage V _RB3 reference signal superimposed on the luminance _{signal, R 2, R 3, R} 4, R 5 ...... R _k , R _{k + 1} , R _{k + 2}
...... _R255 and _R256 can be supplied, and even if the luminance signal SV in which the DC voltage fluctuates with respect to the signal level is input, the comparator circuit CO
M ₃ and comparator circuit COM ₄ , whose reference divided voltage is lower than this, ......
Only COM _k , COM _{k + 1} , ... COM ₂₅₅ , COM ₂₅₆ can always be turned on.

Thus, the clamp circuit 11 and the error amplifier circuit 13 constitute a control circuit that corrects the DC voltage value of the pedestal level so that the predetermined digital information DS _{1 to} DS ₂₅₅ is always obtained for the pedestal level of the luminance signal SV1. On the other hand, the error amplifying circuit 14 always determines the predetermined digital information for the DC voltage value based on the DC voltage value of the reference signal.
A that controls the reference voltage V _RB so that DS _{1 to} DS ₂₅₅ can be obtained
Configure the GC circuit.

Thus, even when a luminance signal whose DC voltage fluctuates with respect to the signal level is input, it is possible to obtain digital information DS having a correct value with respect to the signal level of the luminance signal.

According to the above configuration, the luminance signal in which the DC level fluctuates with respect to the signal level is obtained by the simple configuration in which the error voltage between the DC voltage of the reference signal and the reference divided voltage of the predetermined resistance is simply detected. Even when input, digital information having a correct value for the signal level of the luminance signal can be obtained.

Therefore, in the HDVTR, it is possible to obtain digital information having no signal level difference between the channels with a simple structure as a whole.

In the above-described embodiment, the case where the desired reference divided voltage is obtained from the connection midpoint of the divided resistors has been described, but the present invention is not limited to this. It may be provided in parallel with and to obtain a desired reference divided voltage.

Further, in the above embodiment, the case where the reference voltage is controlled based on the error voltage between the DC voltage of the reference signal and the reference divided voltage superimposed on the luminance signal has been described, but the DC voltage of the luminance signal to be compared is The present invention is not limited to the signal level of the reference signal superimposed on the luminance signal, but can be widely applied to, for example, the DC voltage value of the reference signal of the pedestal level or sync tip level.

Further, in the above-described embodiment, the case has been described in which one of the luminance signals divided into two channels is received as an input signal and converted into digital information, but the present invention is not limited to this, and for example, a color difference signal is converted into digital information. It may be applied widely when converting.

Further, in the above-described embodiment, the case where the present invention is applied to the time axis correction device for HDVTR is described, but the present invention is not limited to this, and the time axis correction of the standard video signal used in a normal television receiver. The present invention can be widely applied not only to the apparatus and further to the time axis correction apparatus, but also to an analog digital conversion circuit for converting a video signal into digital information.

H As described above, according to the present invention, the error voltage between the DC voltage of the input signal and the reference divided voltage used for analog digital conversion is detected, and the standard voltage is controlled based on the detection result. Thus, even when an input signal whose DC voltage fluctuates with respect to the signal level is input, an analog digital conversion circuit with a simple structure can be obtained which can obtain digital information of a correct value for the signal level of the input signal. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an analog digital conversion circuit according to the present invention, and FIG. 2 is a block diagram showing a conventional analog digital conversion circuit. 1 ...... AGC circuits, 2,12 ...... analog-to-digital conversion unit, 3,11 ...... clamp circuit, 13 and 14 ...... error amplifier _{circuit, COM 1, COM 2, COM} 3, COM 4, ...... COM k, COM _{k + 1} , ……
COM ₂₅₅ , COM ₂₅₆ …… Comparison circuit, R ₁ , R ₂ , R ₃ , R ₄ , R ₅ ……
R _k , R _{k + 1} , R _{k + 2} ... R ₂₅₅ , R ₂₅₆ resistance.

Claims (1)

(57) [Claims] 1. A plurality of reference divided voltages obtained by dividing a reference voltage by a voltage dividing resistor are respectively received by a plurality of comparison circuits, and a reference signal of a predetermined signal level is superimposed at a predetermined timing. In the analog digital conversion circuit configured to receive the input signal input to the plurality of comparison circuits and convert the input signal into digital information based on the comparison output of the plurality of comparison circuits, the predetermined reference voltage division A control means for detecting a voltage difference between the voltage and the DC voltage of the reference signal and controlling the reference voltage based on the voltage difference, and a pedestal level of the input signal to another predetermined reference divided voltage. An analog digital conversion circuit characterized by comprising a clamping means for clamping.