JP2547106B2 - Sequence controller - Google Patents

Description

The present invention relates to a sequence control device, and more particularly to the output of its clock pulse.

[Prior Art] FIG. 5 shows a block diagram of a conventional sequence control device 1. The input terminal I ₁ ~I _8, the output of the sensor or the like is given. Loads to be controlled are connected to the output terminals 0 _{1 to} 0 ₈ . The display unit 2 is for displaying the operating state of the sequence control device, and includes an LED and the like. ROM
In 4, the operating system (OS) program is stored. The OS is stored in the non-rewritable ROM 4 because it is a basic program and is used without any change. Programs and data created by the user are stored in the RAM 6 and PROM 30. The CPU 8 controls each unit via the bus line 12 according to the OS of the ROM 4 and the program of the RAM 6. Note that CP
U8 operates according to the system clock supplied from the oscillation circuit 45.

The signals from the sensors input to the input terminals I _{1 to} I ₈ are supplied to the bus line 12 via the input circuit 10. The bus line 12 includes an address bus, a data bus, and a control line, but is omitted in the drawing. The CPU 8 takes in this signal from the bus line 12 and performs an operation according to the user program. Based on this calculation result, the output circuit 14 is controlled via the bus line 12 to set the output terminals 0 _{1 to} 0 ₈ to H or L. As a result, the loads connected to the output terminals 0 _{1 to} 0 ₈ operate or stop.

That is, as specified in the user program,
The operation of the load can be controlled according to the output of the sensor.

For the convenience of creating a user program, a timer (by hardware or software simulation) is provided in the sequence control device 1 so that start and stop can be commanded by the user program.

The program console 100 is used for creating and debugging a user program. Program console 100
Is RAM 106, ROM 104, CPU 108, display unit 102, memory card reader 140, instruction key 150, connection interface 11
Equipped with 6. A cable 200 connects the sequence control device 1 and the program console 100.

The user program is created using the instruction key 150. The instruction key 150 is provided with keys corresponding to various commands. The created user program is I / F1
It is sent out to the cable 200 via 16. The sequence control device 1 receives this and stores it in the RAM 6.

When an execution command is issued from the command key 150 of the program console 100, the execution of the user program in RAM6 starts.

By the way, in the conventional sequence control device, a circuit for outputting a clock pulse is not prepared, and its instruction is not prepared. Therefore, in order from the output terminal 0 _{1-0 8} derive clock pulses, it is necessary to create complex programs. An example of such a program is shown in the ladder diagram in FIG. 6A.

The first line describes that if the output of the timer TMR1 is off, the timer TMR0 starts the time counting operation. The time measured by this timer TMR0 is set to 0.1 Sec.

The second line describes that the timer TMR1 starts the time counting operation when the output of the timer TMR0 is on. The time measured by the timer TMR1 is set to 0.1 Sec.

In the 3rd line, the output of timer TMR0 is output as it is 500
It is described to be output to (any _{one of the} output terminals 0 _{1 to} 0 ₅ is assigned).

When this program is executed, the output of timer TMR1 is initially off.
R0 starts the timing operation (see α in FIG. 6B). next,
The sequence control device moves to execution of the second line. Here, since the output of the timer TMR0 is off, the timer TMR1 is not started. Next, the third line is executed. Again, the output of timer TMR0 is off, so output 500
I have to.

When the execution of the third line is completed, the operation is returned to the execution of the first line and the above operation is repeated. When 0.1 sec has elapsed, the output of the timer TMR0 turns on (see β in FIG. 6B). Only after that, when the second line is executed, the timer TMR1 is started (see γ in FIG. 6B). Next, the output 500 is set to H in the third line (see δ in FIG. 6B).

When 0.1 sec has elapsed from the time point γ, the output of the timer TMR1 is turned on (see ε in FIG. 6B). Only after that, when the first line is executed, the timer TMR0 is reset (see ζ in FIG. 6B). Next, when the second line is executed, the output of the timer TMR0 is off, so the timer TMR1 is also reset (see η in FIG. 6B). Next, when the third line is executed, the output 500 is set to L (see θ in FIG. 6B).

After that, the same operation is repeated, and from output 500 to almost 0.1
A clock pulse of Sec can be obtained.

[Problems to be Solved by the Invention] However, the conventional sequence control device as described above has the following problems.

First, in order to output a clock pulse, it was necessary to create a program with a complicated description, and the clock pulse could not be easily obtained. Further, since the program is complicated, it consumes memory and causes a long scan time (time to execute one routine) for program execution.

Secondly, as is clear from FIG. 6B, a slight error occurred in the obtained clock due to the influence of the scan time. Since this error is accumulated, it may cause a malfunction in some cases.

Thirdly, it was impossible in principle to obtain a clock pulse having a period shorter than the scan time.

An object of the present invention is to solve the above problems and to provide a sequence control device capable of easily obtaining an accurate clock pulse.

[Means for Solving the Problem] The sequence control device according to claim 1 is provided with a clock output instruction, and according to a frequency division ratio obtained by calculation by the central processing means based on the clock output instruction, It is characterized in that a frequency dividing circuit for dividing the output is provided.

In the sequence control device according to claim 2, the frequency dividing circuit is reset by a one-shot pulse from a comparator, a counter for counting the output clock of the clock oscillation circuit, and a calculation for achieving a desired frequency dividing ratio. It receives the count-up value from the central processing means, compares the count value of the counter with the count-up value, and outputs a one-shot pulse by a comparator that outputs a one-shot pulse when they match. It is characterized in that it is provided with an output control circuit for alternately changing over to an H level and an L level.

According to another aspect of the sequence control device of the present invention, the clock output instruction is assigned to a timer operation instruction for a predetermined timer.

[Operation] In the sequence control device according to the first and second aspects, a desired clock is obtained by dividing the output of the clock oscillation circuit. Therefore, an accurate clock can be easily obtained.

In the sequence control device according to the third aspect, the clock output instruction is assigned to the timer operation instruction for the predetermined timer. Therefore, compatibility with the conventional sequence control device can be maintained.

[Embodiment] FIG. 2 shows an appearance of a sequence control device according to an embodiment of the present invention. At the top of the case 20, the input terminals I _{1 to} I ₈
Is provided, and output terminals 0 _{1 to} 0 ₈ (not shown) are similarly provided on the lower portion. An LED 22 for displaying the operating state of the device and the like is arranged on the front surface of the housing 20. In addition, a recess 2 for engaging the DIN rail is provided at the rear of the housing 20.
4 are provided.

The program console 100 shown in FIG. 3 is connected when the user program of this sequence control device is created or debugged. The connection is performed by connecting a connector (not shown) provided on both sides with a cable (not shown). As shown in FIG. 3, on the front surface of the program console 100, a liquid crystal display 103 constituting the display unit 102 is provided, and a large number of command keys 150 are provided. This command key 150 is used to create a user program. In addition, a memory card reader 140 is provided inside the memory card 3
An insertion port 142 for inserting 00 is provided on the side surface. The user program can be stored in the memory card 300.

FIG. 1 is a block diagram of the sequence control device 1 and the program console 100 shown in FIGS. 2 and 3. The basic structure and operation are the same as those in FIG. In this embodiment, the system clock given to the CPU 8 which is the central processing means is also given to the counter 35. The counter 35 counts this system clock,
The count value is given to the comparator 25. The comparator 25 compares the count-up value given from the CPU 8 with the count value from the counter 35, and when they match, a compare match output
Issue 125. This compare match output 125 is a one shot pulse.

The compare match output 125 is supplied to the reset input CLR of the counter 35. Therefore, the compare match output 125 is output for each count-up value of the system clock.

Further, the compare match output 125 is also given to the control logic 55 which is an output control circuit. The control logic 55 is composed of, for example, a JK flip-flop, and changes the output H → L → H → L ... Each time the compare match output 125 is given.

Therefore, from the output 0C of the control logic, CP
A clock pulse obtained by dividing the system clock by the division ratio (count-up value) specified by U8 is obtained. The obtained clock pulse is given to the output circuit 14, and the CPU 8
Is output from any one of the output terminals 0 _{1 to} 0 ₈ .

In the sequence controller of this embodiment, 600 μSec
In order to obtain a clock pulse with a period, it is only necessary to create a program as shown in the ladder diagram of FIG. 4A. In this embodiment, the operation command for the timer 20 is
It is considered as a clock pulse output command. The program of FIG. 4A is input 1000 (any input terminal I ₁
~ I ₈ is assigned), if H is level, output 500
To 600 μSec clock pulse is output.

When this instruction is executed and the CPU 8 receives it, it is first determined whether or not the input 1000 is H. If it is at the H level, the timer operation instruction is executed. However, here, since it is an instruction for the timer TMR20, it is determined that this is a clock pulse output instruction.

In this program, the clock pulse setting is 600
It is a μSec cycle. CPU8 uses this setting cycle of 600 μSe
c and the system clock (ie the output of oscillator circuit 45)
And the cycle are compared, and the ratio is given to the comparator 25 as a count-up value. For example, if the system clock cycle is
If it is 0.1 μSec, set the count-up value to 6000. As a result, as shown in FIG. 4B, it is possible to accurately obtain a clock pulse of 600 μSec cycle from the output OC of the control logic 55.

In addition, the comparator 25, the counter 35, the oscillation circuit 45,
It is also possible to use the one provided inside the CPU 8.

Further, the CPU 8 can also stop the output of the clock pulse OC by controlling the enable terminal of the control logic via the terminal P1 of the input / output port 93.

Furthermore, it is also possible to set an initial value from the CPU 8 to the counter 35 and change the cycle of the clock pulse without changing the count-up value.

Further, in the above embodiment, the timer operation command for the specific timer is regarded as the clock output command. Therefore, it is not necessary to add a new command key to the command key 150 of the program console 100. That is, a clock output command can be newly provided while maintaining compatibility with the conventional program console 100.

If it is not necessary to maintain compatibility with conventional equipment, a new command may be provided for clock output.

In the above embodiment, the CPU is used as the central processing means, but a part or all of the CPU is also applicable to the hardware logic.

[Effect of the Invention] In the sequence control device according to the first and second aspects, a desired clock is obtained by dividing the output of the clock oscillation circuit. Therefore, an accurate clock can be obtained with a simple program.

In the sequence control device according to the third aspect, the clock output instruction is assigned to the timer operation instruction for the predetermined timer. Therefore, compatibility with the conventional sequence control device can be maintained.

[Brief description of drawings]

FIG. 1 is a block diagram of a sequence control device according to an embodiment of the present invention, FIG. 2 is an external view of the sequence control device, FIG. 3 is an external view of a program console, and FIG. 4A is a ladder showing a clock output program. FIG. 4B is a diagram showing clock pulses obtained when the program of FIG. 4A is executed, FIG. 5 is a block diagram of a conventional sequence control device, and FIG. 6A is a conventional sequence control device. FIG. 6 is a ladder diagram showing an example of a program created to output a clock pulse, and FIG. 6B is a diagram showing waveforms of respective parts when the program of FIG. 6A is executed. 1 sequence controller 8 CPU 25 comparator 35 counter 45 oscillator circuit 55 control logic

Front page continued (72) Inventor Kengo Ueki 2-13, Akita-cho, Takatsuki-shi, Osaka KEYENCE CORPORATION Examiner Yoji Sugazawa (56) References JP-A-61-278905 (JP, A)

Claims (3)

(57) [Claims] 1. A sequence control device comprising a central processing means for analyzing and executing instructions of a program, and a clock oscillating circuit for supplying a clock to the central processing means, wherein a clock output instruction is provided and the central processing is performed based on the clock output instruction. A sequence control device comprising a frequency divider circuit for dividing the output of the clock oscillation circuit according to a frequency division ratio calculated by the processing means. 2. The sequence control device according to claim 1, wherein the frequency dividing circuit is reset by a one-shot pulse from a comparator,
A counter that counts the output clock of the clock oscillation circuit, receives a count-up value calculated so as to achieve a desired frequency division ratio from the central processing means, compares the count value of the counter with the count-up value, and when they match. A sequence control device comprising: a comparator that outputs a one-shot pulse; and an output control circuit that alternately changes the output to an H level and an L level according to the one-shot pulse output from the comparator. . 3. The sequence control device according to claim 1, wherein the clock output instruction is assigned to a timer operation instruction for a predetermined timer.