JP2551001B2 - Sequential decoding method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a sequential decoding method for performing decoding while sequentially selecting a branch that seems to be most likely for a received data sequence.

(Prior Art) A convolutional coding method is a typical example of an FEC (Forward Error Correction) coding method in which an error correction code is used to automatically correct an error on the receiving side.

As one of the decoding methods using the convolutional code, there is a maximum likelihood decoding method that uses the correlation between the received information bits. The maximum likelihood decoding method is theoretically the decoding method that can reduce the bit error rate the most, but since the device configuration becomes exponentially complicated with the constraint length of the code, it is a sequential decoding that approximates the maximum likelihood decoding method. The method has been attracting attention in recent years.

FIG. 1 is a conceptual diagram of a conventional iterative decoding method using a stack algorithm. Reference numeral 1 generally gives a delay of about several thousand bits to received data which is hard-decision- or soft-decision-demodulated by a demodulator (not shown). The FIFO type input / output buffer memory unit 2 having a memory capacity of only 1 and capable of extracting a received data sequence by a control signal from an algorithm control unit 6 described later, 2 is data from the input / output buffer memory unit 1 and an algorithm described later. The branch selection unit 3 that creates a branch to be selected next from the branch selection signal from the control unit 6 is a new re-encoding based on the already set σ of the shift register state and the branch information from the branch selection unit 2. Re-encoding (shift register) unit for generating σ ′ of the digitized sequence and new shift register state, and 4 is node information on the tree structure (path metric value Γ , Shift register status σ, input /
A stack memory unit that is a large-capacity memory for storing the node position d in the output buffer memory unit 1, the branch information selected in the past, a pointer indicating the position on the tree structure, and the like,
Reference numeral 5 is a metric calculation unit for calculating a branch metric γ by comparing the received sequence read from the input / output buffer memory unit 1 with the re-encoded sequence, and 6 is a node currently searched by searching the stack memory unit 4. The node with the highest path metric value Γ (highest likelihood) is selected from among the above, and the node information is stored, and the received data sequence corresponding to the branch extending from this node from the input / output buffer memory unit 1 is selected. After taking out, the branch to be selected is determined and sent to the branch selection unit 2, and when the branch metric γ from the metric calculation unit 5 is obtained by this, the path metric Γ ′ (= Γ + γ) of the newly created node is obtained. An algorithm control unit that calculates and transfers to the stack memory unit 4.

 Next, the operation will be described.

(1) The received data sequence including the parity bit and the information sequence in which the received data encoded by the convolutional system encoder is demodulated by the demodulator and bit-synchronized is sequentially input / output buffer memory unit 1 (hereinafter , "Buffer memory unit 1").

(2) The accumulated received data sequence is the node position d from the algorithm control unit 6 (hereinafter abbreviated as “control unit 6”).
Is read out by the position control signal based on the above, and sent to the branch selection unit 2 and the metric calculation unit 5.

(3) The branch selection unit 2 creates a branch to be selected next by the signal of the branch selection signal from the control unit 6 and the received data sequence (most significant bit) forming one branch from the buffer memory unit 1 and re-encoding unit Transfer to 3.

(4) In the re-encoding (shift register) unit 3, the control unit 6
After the shift register state σ of the maximum likelihood node fetched from the stack memory unit 4 is set by the instruction from, the branch information from the branch selection unit 2 is input, a re-encoded sequence is created, and it is sent to the metric calculation unit 5. Sent. At this time, the newly created shift register state σ ′ is sent to the stack memory unit 4.

(5) The metric calculator 5 calculates the branch metric γ by comparing the received data sequence read from the buffer memory 1 with the above-mentioned re-encoded sequence, and sends it to the controller 6.

(6) The control unit 6 is newly created, including the latest path metric value Γ ′ (= Γ + γ), from the path metric value Γ having the maximum likelihood node stored up to now and the new branch metric γ. The various attributes of the node are calculated and transferred to the stack memory unit 4.

(7) Finally, the oldest stored node is taken out from the nodes stored in the stack memory unit 4, and the decoded data bit determined by this is sent to the buffer memory unit 1 to be sent to the buffer memory unit 1. The contents of 1 are updated and the decoded data stored at the end of the buffer memory unit 1 is output. At that time, the extracted node and the nodes on the path which are derived from the node and are excluded from the current search target are deleted from the stack memory unit 4.

By repeating the above processing steps, the received data sequence is sequentially error-corrected and decoded.

Since the successive decoding method sequentially selects the sequence with the highest likelihood as described above, the likelihood of branches along the received data sequence increases sequentially and the forward search is continued if the transmission path condition is good. You can do it. On the other hand, when noise increases and S / N deteriorates on the transmission path, many errors occur in the received data sequence, so the branch metric γ calculated by the metric calculator 5 is applied to every searched branch. There are cases where it does not increase. In that case, the control unit 6 retrieves the node information with the highest likelihood among the past accumulations from the stack memory unit and continues to search for another branch. However, during the search of these branches, the new reception sequence continues to be input into the buffer memory 1, and finally the reception data sequence corresponding to the branch being searched is output from the buffer memory unit 1 and no more. There occurs a phenomenon that the normal decoding operation of is impossible.

This phenomenon also occurs when the number of nodes stored in the stack memory unit 4 exceeds the memory capacity, and is generally called "decoder overflow".

In general, a systematic code or a QLI code is used as a code in order to deal with the undecodable state due to the overflow so that the information sequence can be reproduced even when the decoder becomes inoperable. Conventionally, as a method for returning from this decoder overflow state to a normal decoding state, firstly, there is a blocking method of terminating the coded sequence with a certain block length and keeping the undecodable state only within a certain block. Was being considered. With this method, when decoding a new block, a known bit pattern can be used, and this pattern can be put into the shift register of the encoder to immediately start a steady decoding process. . While this method has the advantage of being able to recover the undecodable state with certainty, throughput decreases with block termination,
Since the error is not corrected during the undecodable state, there is a problem that the error of the transmission line appears in the output as it is.

As a second method, when a decoder overflow occurs, the reproduction sequence obtained from the reception sequence is output, and this sequence is set in the shift register of the re-encoder so that information bits are stored in all stages of the shift register. When stored (below,
There is a method of restarting the decoding again in the "first state". This method can also be applied when starting decoding from an unknown initial state in continuous decoding mode. When this method is adopted, when all the correct information bits are input to the shift register in the first state, the decoding is immediately restarted, and it is possible to shift to the normal decoding operation (hereinafter, defined as "steady mode"). On the other hand, if the wrong information bit is set, there will be a great difficulty in the subsequent decoding, and there is a possibility that a decoder re-overflow often occurs.

As described above, conventionally, in some cases, such as at the start of decoding or when the decoder overflows, the decoding may start from an unknown initial state and the transition to stable mode, which is stable decoding operation, may not be performed smoothly. However, there has been a strong demand for a sequential decoding method capable of quickly shifting to the stationary mode, but none has been disclosed so far.

(Objects and Features of the Invention) The present invention has been made in order to solve the above-mentioned problems of the prior art, and provides a sequential decoding method capable of rapidly shifting from an unknown initial state to a normal decoding operation. The purpose is to do.

The first feature of the present invention is a target of a branch search between the first state in which information bits are stored in all stages of the shift register of the re-decoding unit 3 and the steady mode in which a normal decoding operation is performed. This is because at least a monitoring mode for determining the metric value Γ _{t of the} node and comparing it with a predetermined threshold value is provided.

A second feature of the present invention is that in addition to the shift register state σ stored in all stages of the shift register in the above-mentioned first state,
A plurality of other possible shift register states σ ′ are created, and the created multiple shift register states are accumulated in order of reliability, and these are automatically stored in the process of the normal decoding algorithm. I have been trying to be selected.

A third feature of the present invention is to use a plurality of shift register states created and accumulated in order of high reliability in the first state (the second feature of the present invention), and to use the maximum likelihood node as a target of a branch search. By combining the metric value Γ _j ^{(t) of} _j with a predetermined threshold value (the first feature of the present invention), it is possible to move to the steady mode more quickly.

(Operation) According to the present invention, since at least the monitoring mode is provided, a plurality of shift register states are created and accumulated in order from the highest reliability without repeating the wasteful branch search a plurality of times. Even if the shift register state is determined to be unsuitable, the search from new shift register states having high reliability is automatically started one after another.

(Structure of the Invention) The present invention will be described in detail below with reference to the drawings.

First, the monitoring mode, which is the first feature of the present invention, will be described.

(Embodiment 1) FIG. 2 is a first embodiment of the present invention and is a flow chart of a decoding process from resetting of the re-encoding unit (start of decoding) to transition to a stationary mode.

First, the state of the shift register of the re-encoding unit 3 (FIG. 1) is indefinite at the start of initial decoding or when the decoder overflows, and this state is set as the decoding start point here. Next, all the shift register stages are set by the information bits reproduced from the reception sequence (first state). When the reproduction sequence is stored in all stages of the shift register, the operation of the decoder is started, the metric value Γ _j ^{(t) of the} maximum likelihood node j is compared with a plurality of predetermined threshold values, and branch expansion is performed. Planned.

In the following explanation, we will limit this to two for simplicity.
Let Γ _wu and Γ _wl . With these thresholds, the monitor mode takes the following process.

When the maximum likelihood node j is a node corresponding to the time t of the received data sequence and has a path metric value Γ _j ^(t) , a) If Γ _j ^(t) <Γ _wl , the re-encoding unit is reset, Start again b) If Γ _wl ≤ Γ _j ^(t) ≤ Γ _wu , continue monitoring mode c) If Γ _wu <Γ _j ^(t) , judge that the decoder has completely moved to the steady decoding response, and start this The process (comparison with the threshold of the metric value Γ _j ^(t) ) is terminated.

In this way, the metric value Γ _j ^(t) of the maximum likelihood node that is the target of the branch search is compared with a predetermined threshold value to make a determination, and thus an incorrect shift register state is set in the re-encoding unit. In this case, it is possible to quickly return to the first state and overcome the difficult decoding state, and as a result, it is possible to quickly shift to the steady mode. The coding rate is set to 1 / as the thresholds Γ _wu (upper limit) and Γ _wl (lower limit) that are set in advance.
2, constraint length 25, transmission line noise Es / No = 0.0dB (however, Es is energy per bit, No is one side noise power density)
Experiments were carried out with Γ _{wu ≈100} , Γ _wl ≈−20, and relatively good decoding results were obtained.

(Embodiment 2) FIG. 3 shows a second embodiment according to the present invention.
The difference is that the branch is forcibly assigned between the first state in which the reproduction sequence is set in all stages of the shift register and the monitoring mode, and the path metric value Γ ^(t) for the time point t is calculated and set in advance. A search mode is provided for comparison with the determined threshold (Γ _Sl , Γ _Su ).

In the search mode, a normal decoding process for selecting a branch is not yet taken, and a process for directly allocating a branch reproduced from a received sequence is adopted. Therefore, in the search mode, the sequence is definitely reproduced one branch by one step. Further, in this mode, two kinds of thresholds Γ _Sl and Γ _Su are provided for determination. However, if the metric value assigned at the start of the search mode is Γ _O , Γ _Sl ≦ Γ _O ≦ Γ _Su is set. With these thresholds, the search mode takes the following process.

The metric value Γ of the node that is deterministically determined at a certain time t
^{For (t)} : a) If Γ ^(t) <Γ _Sl , reset the metric value Γ ^(t) to the initial metric value Γ _O and continue the search mode. b) Γ _Sl ≤ Γ ^(t) ≤ If Γ _Su , continue search mode (at this time, the metric value Γ ^{(t + 1)} of the branch at the next time point is calculated) c) If Γ _Su <Γ ^(t) , shift to monitoring mode In monitoring mode By permitting the selection of branches, while temporarily monitoring the decoding process by the threshold value, the normal decoding process is temporarily restored.

That is, in the search mode, the branch reproduced from the reception sequence is forcibly directly assigned and its metric value Γ ^(t) is calculated without performing the branch selection unlike the monitoring mode and the steady mode, and the threshold Γ _Sl and I tried to compare with Γ _Su ,
Furthermore, the transition to the steady mode can be accelerated. An experiment conducted under the same conditions as the monitoring mode showed that Γ _Sl ≈ −20, Γ
_A good decoding result was obtained when _Su ≈ 40.

In the monitoring mode shown in the figure, the condition tt _k is added so as not to search backward for a node tried in the search mode in the past, but the condition may not necessarily be added and the node may be traced back to the past.

FIG. 4 is a schematic diagram of a sequential decoding method according to the present invention,
The difference from the conventional example (Fig. 1) is that the metric value Γ _j ^(t) (Γ
^(t) ) and a predetermined threshold value Γ _wl , Γ _wu (Γ _Sl , Γ _Su ), and a threshold value comparison unit 7 for setting search mode and monitoring mode threshold values and for inhibiting or canceling branch selection The activation control unit 8 for performing the above is provided.

The operation of this method is as follows. First, the algorithm control unit 6 sends a start signal to the start control unit 8.
Upon receiving the signal, the activation control unit 8 sends a reset signal to the stack memory unit 4 and at the same time sends a selection prohibition pulse to the branch selection unit 2 to forcibly select only the branch reproduced from the received signal. The activation control unit 8 also sends a comparison start signal and a reference threshold value to the threshold value comparing unit 7. Next, the re-encoding unit 3 receives the reset signal from the activation control unit 8 via the stack memory unit 4, and stores the information bit reproduced from the received signal sequence in the shift register.

In the search mode, since the selection function of the branch selection unit 2 remains stopped, a re-encoded sequence is obtained by the branch regenerated from the received sequence, and this sequence is input to the metric calculation unit 5 and compared with the received sequence. Then, the path metric value Γ ^(t) is calculated. The path metric value Γ ^(t) is compared in the threshold value comparison unit 7 with the threshold value Γ _O input from the activation control unit 8 in advance, and the determination result is compared to the activation control unit 8
Returned to. At this time, if the path metric value Γ ^(t) is below the lower threshold Γ _Sl , the metric calculator 5 resets the path metric value Γ _O , and the information of this node is stored in the stack memory. Even when the path metric value Γ ^(t) does not _{fall below the} threshold value Γ _Sl , the node information after the metric calculation is similarly stored in the stack memory.

If the path metric value Γ ^(t) exceeds the upper threshold Γ _Su in the threshold comparing unit 7, the mode shifts from the search mode to the monitoring mode. At this time, a new threshold value is sent from the activation control unit 8 and set in the threshold value comparing unit 7. At the same time, the activation control unit 8 sends a branch selection prohibition release pulse to the branch selection unit 2 and a return signal to the algorithm control unit 6, and thereafter shifts to the normal decoding process while holding the threshold comparison. If the path metric value Γ _j ^(t) exceeds the upper threshold value Γ _wu in this monitoring mode, it is determined that a completely stable decoding stage has been entered, and the activation control unit 8 notifies the threshold value comparison unit 7 of a stop signal. And the start control unit 8 also sends the algorithm control unit 6
Enter the mode with the start signal from. On the other hand, even in the monitoring mode, if the path metric value Γ _j ^(t) falls below the lower threshold value Γ _wl , the activation control unit 8 sends the branch selection unit 2 selection prohibition pulse again, and at the same time, the stack memory unit 4 stores After resetting and initializing the path metric value, the initial state of decoding start is restored.

Although the case where the search mode and the monitoring mode are provided has been described with reference to FIG. 4, the transition to the steady decoding operation can be performed quickly by performing at least the monitoring mode. Further, although the above description relies on the successive decoding method using the stack algorithm, the present invention is basically applicable to all successive decoding methods using the successive decoding algorithm.

Next, a description will be given of a sequential decoding method for creating / accumulating a plurality of shift register states which is the second feature of the present invention.
Note that the following description will be limited to the sequential decoding method using the stack algorithm in which the effect of the present invention is remarkably exhibited.

FIG. 5 is a diagram for explaining the principle of the second feature of the present invention, and FIG. 5 (a) shows the case where the initial state σ ₀ set in the shift register is inappropriate, and FIG. 5 (b). Indicates the case where the initial state σ ₁ of the next candidate is determined to be correct. When starting or resuming decoding, first, the information sequence reproduced from the reception sequence is set in the shift register to create the initial state σ ₀ at time t and store it in the memory. At this time, a plurality of initial value candidates σ _i (i = 1,
2, ..., μ; μ is an appropriate value that satisfies 1 μ2 ^ν ) is created as follows, and is similarly stored in the memory. That is, since the state σ is considered to be a ν-dimensional vector, if the Hamming distance between two states is represented by d _H (), then d _H (σ ₀ , σ _i ) ≦ d _H (σ ₀ , σ _j ) (however, , 0ijμ), σ _i (i = 1, 2, ..., μ) is sequentially selected. Actually, the ν-dimensional vector series h _j (i = 0,1,2, ...) Arranged in order from the smallest Hamming weight is stored in the memory, and σ
Configure σ _i with _i = σ ₀ + h _i . Also, if the soft-decision received data is available, the states σ _i are constructed in the order of being further weighted by the soft-decision bits. With the plurality of initial values set in this way, the decoding is started from the first initial value σ ₀ .

If the metric of the path resulting from this initial value increases steadily thereafter, the decoder automatically selects this initial value in the algorithm and continues the normal decoding operation. However, if the path metric starting from the state σ ₀ decreases (FIG. 5 (a)), another state σ ₁ close to the state σ ₀ is selected as the next candidate, and FIG. As in b), the search for a branch is started again from the state σ _i .

As long as there is a time margin, the decoder automatically selects the next state and continues decoding even if the path metric value extending from the state tried so far decreases. When there is no time left, the decoder and I / O buffer are reset, and the same process is repeated from the beginning.

(Embodiment 3) FIG. 6 is a third embodiment according to the present invention, in which a plurality of shift register states σ _i (0i) when hard decision received data is used and a stack algorithm is used.
It is a figure for demonstrating the accumulation | storage method and determination method of (mu).

In the diagram (a), the stack memory unit 4 is arranged in the order in which the shift register states σ _i have the highest reliability (σ ₀ has the highest reliability and σ _μ has the lowest reliability) by using the hard decision information. It shows the state of being stored in the bin a inside. As a method of creating a plurality of shift register states σ _i in descending order of reliability, a state σ ₀ is created based on the information of the received data series,
Then, it is possible by sequentially inverting at least one bit of the information bit. Furthermore, in FIG.
The state in which the branch is extended from the state σ ₀ based on the shift register state σ ₀ is shown. The node to which the branch is extended is the metric area of the bin a (hereinafter referred to as “a area”), and the node is This is an example of being included in the metric area (hereinafter, referred to as “a + 1 area”) of the bin a + 1 having a smaller metric value than the bin a.

In the same figure (b), the node having the state σ ₀ is erased and the node in the metric area of the same bin is bin a
The node in the a + 1 area is stored in the lower bin a + 1.

In FIG. 6C, the branch is further expanded from the node and the metric value with the destination node is checked. In this example, since the metric value together with the node exists in a region lower than the region a, the shift register state σ ₀ initially set at this time is automatically determined to be unsuitable, and the bin a
The shift register state σ ₁ having the next highest reliability comes at the head of the.

In the same figure (d), as in the case of the same figure (a), the branch is expanded from the state σ ₁ and the metric value of the node at the end of the branch is examined. In the figure, the node is in the bin a-1 area in which the metric value is larger than that of the current node (σ ₁ ), and then the branch is similarly expanded from the node to smoothly increase the metric value ( Then, the shift register state σ ₁ is automatically determined to be correct and the normal decoding process is continued.

Since the conventional method does not create a plurality of initial value candidates, even if the path metric extending from the initial value candidate σ _{0 in} the first state is reduced, the paths generated from the state σ ₀ are left until there is no time margin. I was in the process of continuing to search.
Therefore, if a plurality of shift register states are created and accumulated in advance as in the present invention and the initial value candidates are determined in descending order of reliability, the probability that a correct initial state will be selected at that point in time increases. As a result, the normal decoding process can be quickly performed.

FIG. 7 is a schematic diagram of a sequential decoding method according to the present invention using a stack algorithm. The difference from the conventional configuration is that an initial value candidate generating unit 9 is added.

The initial value candidate generator 9, which is a feature of the present invention, uses the shift register 91 that stores the soft-decision data from the buffer memory unit 1 as it is and the soft-decision weight information stored in the shift register 91. A sequence estimation circuit 92 for sending an inversion control signal to a portion where the high-order bit (MSB) has low reliability, and an inversion information for the contents of the shift register 91 by the inversion control signal from the sequence estimation circuit 92. It is composed of a NOT circuit with control 93 and a sequence generation circuit 94 that creates initial value candidates in ascending order of Hamming distance to the reception sequence.

First, the shift register 91 sequentially receives received data from a certain pointer in the input / output buffer memory unit 1. In this embodiment, since the received data is 3-bit soft decision data, the input to the shift register 91 is also 3-bit data. The shift register 91 has a FIFO type structure, and its series length is formed to be equal to the length (constraint length-1).

Next, when the buffer memory unit 1 or the stack memory unit 4 overflows, the algorithm control unit 6 clears the stack memory unit 4 and generates an estimation start signal to the sequence estimation circuit 92. First the sequence estimator 92, and inputs the status sigma ₀ than the channel via intact sequence generation circuit 94 most significant bits stored in the shift register 91 (MSB bit) in the stack memory unit 4. Next, the sequence estimation circuit 92 uses the soft decision weight information stored in the shift register 91 to control the inversion control signal for the portion with the lowest reliability of the MSB bit.
A condition σ in which the NOT circuit 93 is sent out, and the sequence generation circuit 94 has a sequence having a short Hamming distance to the received sequence next to σ _0.
Produce ₁ . The state σ ₁ is stored in the stack memory unit 4 through the channel as in the case of the state σ ₀ . By repeating the same operation repeatedly, the stack memory unit 4
_Stores nodes that are initial value candidates for decoding up to the states σ ₀ , σ ₁ , ..., σ _ν . However, an appropriate value is selected for μ according to the processing speed of the decoder.

For example, assume that the constraint length k is 6, and the next value is stored in the shift register 91 when an overflow occurs.

Bit 1 (MSB) ... 10011 Bit 2 ... 01100 Bit 3 (LSB) ... 10101 However, Bit 2 and Bit 3 are soft decision data indicating reliability, and (Bit 2, Bit 3) is (1, 1) (1 , 0) (0,1) (0,
Data reliability increases in the order of 0). At this time, σ ₀
Is selected as (1,0,0,1,1). If the reliability bit is subsequently examined, the fourth bit is the least reliable.
Therefore, the sequence estimation circuit 92 sends a control signal that inverts the fourth bit, so that the sequence generation circuit 94 receives the state σ ₁ = (10
001) is generated and sent to the stack memory unit 4. Similarly, the states σ ₂ = (00011) and σ ₃ = (10010) are created, sent to the stack memory unit 4, and stored therein. If μ = 3 is set as the upper limit, the sequence generation process is completed and the process is restarted. In the restart process, the branch search is performed in exactly the same process as the normal decoding starting from the node for the state σ ₁ (i = 0, 1, 2, ..., μ) set in the sequence generation process. However, the order in which the nodes are selected is σ ₀ → σ ₁ →, ..., → σ _μ . By restarting the decoding in this way, even if σ ₀ cannot be in the correct state, the decoder continues to search for the correct path while selecting the next candidate, which can speed up the transition to normal operation. it can.

Finally, a method of preliminarily creating and accumulating at least a monitoring mode (first characteristic of the present invention) and a plurality of shift register states, which are the third characteristic of the present invention, in the order of high reliability, and sequentially using them as initial value candidates ( A sequential decoding method based on a stack algorithm in which (2nd feature of the present invention) is combined will be described.

(Embodiment 4) FIG. 8 shows a fourth embodiment according to the present invention.
The difference from FIG. 2 is that when the metric value Γ _j ^(t) of the maximum likelihood node j in the monitoring mode exists between the lower limit threshold Γ _wl and the upper limit threshold Γ _wu that are set in advance. , The node state or the initial value candidate having the next highest reliability among those stored in the stack memory unit 4 in the order of the highest reliability by the stack algorithm (for example, the state of FIG. 6B) is expanded. The node group is automatically selected according to the algorithm (broken line in the figure) to continue the monitoring mode.

In other words, by combining the monitoring mode and a plurality of initial value candidates, the branch search can be performed from the node with the next highest reliability without repeating the wasteful branch search. Get faster.

FIG. 9 is a schematic diagram of a sequential decoding method for embodying the fourth embodiment according to the present invention.

This figure shows a function (threshold comparison section 7 and activation control section 8) for performing the monitoring mode (search mode) described in FIG.
The configuration is combined with the function of creating (initial value candidate generating unit 9) and accumulating (stack memory unit 4) and processing a plurality of shift register states σ _i described in the figure.

Thus, the structure of the present invention can be easily realized by adding a simple circuit to the conventional structure (FIG. 1) or changing the program.

(Effect of the Invention) As described in detail above, the present invention provides at least a monitoring mode for calculating the metric value Γ _j ^(t) of the maximum likelihood node and comparing it with a predetermined threshold, or a plurality of initial modes. By creating and accumulating value candidates in advance in descending order of reliability, determining sequentially and determining initial value candidates, and by combining these, the transition from the start of decoding to the steady decoding operation can be performed quickly. This makes it possible to reduce the bit error rate of the successive decoding method even under noise, and the effect is extremely large.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a conventional sequential decoding method, FIG. 2 is a flow chart of a decoding process when a monitoring mode according to the present invention is provided, and FIG. 3 is a decoding process when a search mode and a monitoring mode according to the present invention are provided. FIG. 4 is a flow chart of the processing, and FIG.
5A and 5B are explanatory diagrams for explaining the concept of determining initial value candidates according to the present invention, and FIGS. 6A to 6D are according to the present invention. FIG. 7 is an explanatory diagram for explaining determination of initial value candidates, FIG. 7 is a schematic diagram of a second sequential decoding method according to the present invention, and FIG. 8 is decoding using a monitoring mode and initial value candidates according to the present invention. FIG. 9 is a flow chart of processing and is a schematic diagram of a third sequential decoding method according to the present invention. 1 ... Input / output buffer memory unit, 2 ... Branch selection unit, 3 ... Re-encoding unit, 4 ... Stack memory unit, 5 ... Metric calculation unit, 6 ... Algorithm control unit, 7 ... Threshold value Comparing unit, 8 ... Activation control unit, 9 ... Initial value candidate generating unit, 91 ... Shift register, 92 ... Sequence estimating circuit, 93 ... NOT circuit with control, 94 ... Sequence generating circuit.

Claims (4)

(57) [Claims] 1. A sequential decoding method in which an initial state is set in a shift register of a re-encoding unit which performs convolutional encoding using information bits reproduced from a reception sequence in which bit synchronization is established, and a branch search is started. In the monitoring mode, information bits are stored in all stages of the shift register, a metric value of a node targeted for the branch search is obtained, and the metric value is compared with at least two types of threshold values provided in advance. When the metric value exceeds the upper limit of the thresholds, the branch search is sequentially performed to shift to a steady mode in which normal decoding operation is performed, and the metric value falls below the lower limit of the thresholds. Sometimes, the re-encoding unit is reset, information bits are stored again in all stages of the shift register, and the above-mentioned operation is repeated. 2. After storing information bits in all stages of the shift register, a metric value in which branches are forcibly assigned is obtained from the initial metric value given in the initial state, and the metric value is predetermined. A search mode in which at least two kinds of second threshold values are compared is executed, and transitions to the monitoring mode only when the metric value exceeds an upper limit threshold value of the second threshold values. The sequential decoding method according to claim 1, wherein when the threshold value is lower than the lower limit threshold value, the metric value is reset to the initial metric value and the search mode is repeated. 3. A sequential decoding method for starting an edge search by setting an initial state in a shift register of a re-encoding unit that performs a convolutional code using information bits reproduced from a reception sequence in which bit synchronization is established. , In addition to the initial shift register state stored in the shift register, one or more of the shift register states are inverted in the order of least reliable bits to create a plurality of new shift register states in advance. The initial value candidates of the initial state are set, and the plurality of initial value candidates are accumulated in advance in a stack memory in order of high reliability, and the most reliable shift register state set in the shift register is determined to be unsuitable. Then, the next-highest-reliability initial value candidate among the previously stored initial value candidates is processed by the stack decoding algorithm. A sequential decoding method characterized by automatically selecting and decoding. 4. A sequential decoding method for starting an edge search by setting an initial state in a shift register of a re-encoding unit that performs a convolutional code using an information bit reproduced from a reception sequence in which bit synchronization is established. , Information bits are stored in all the stages of the shift register, and a plurality of initial value candidates to be set in the shift register are created and accumulated in advance in descending order of reliability, and the maximum likelihood node to be the target of the branch search is stored. A monitoring mode is executed in which a metric value is obtained and the metric value is compared with at least two types of threshold values provided in advance, and when the metric value is within the threshold values of the upper limit and the lower limit, the stack algorithm is executed. Decoding by, when the metric value exceeds the upper limit threshold, the branch search is sequentially performed to shift to a steady mode in which normal decoding operation is performed, On the other hand, when the metric values of all the branches extending from the plurality of initial value candidates are lower than the lower limit threshold, the maximum coding unit is reset and information bits are stored again in all stages of the shift register. A sequential decoding method characterized by repeating the above operation.