JP2551183B2 - FIR echo canceller by high speed projection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a FIR echo canceller using a fast projection method.

[Prior Art] An echo canceller for voice must reliably perform a large number of multiplications and additions in a short time. For example, the telephone line echo canceller must perform calculations several hundred times and the acoustic echo canceller must perform calculations several thousand times within a time of about 100 mSec. Therefore, as the echo canceller which has been put into practical use, a FIR echo canceller using a learning and identification method with a simple algorithm is generally used because the amount of calculation is as small as possible.

[Problems to be Solved by the Invention]

In the conventional FIR echo canceller using the learning identification method, when the input signals are correlated, the convergence speed is significantly degraded. Therefore, an estimation method called an affine projection method, which is an extension of the learning identification method, has been proposed. However, the affine projection method requires more operations than the learning identification method, and there is a problem that the hardware is increased for practical use.

SUMMARY OF THE INVENTION An object of the present invention is to provide a FIR echo canceller using a high speed projection method which has a fast convergence speed and a small amount of calculation for a chromatic signal having a strong correlation in order to solve the above problems.

[Means for solving the problem]

An echo canceller of the present invention delays an output signal of a first storage circuit that stores the latest N received input signals, a second storage circuit that stores an impulse response Nth order of an echo path, and the first storage circuit. A first delay circuit, a first multiplication circuit that multiplies both output signals of the first storage circuit and the second storage circuit, an accumulation circuit that integrates the output signals of the first multiplication circuit, and the first storage Circuit and a correlation calculation circuit for calculating the cross-correlation from both output signals of the first delay circuit and the autocorrelation of the received input signal, a second delay circuit for delaying the transmitted output signal, the transmitted output signal and the second delay A correction amount calculation circuit for obtaining a correction amount at the current time and a correction amount at the next time from an output signal of the circuit and an output signal of the correlation calculation circuit, a third delay circuit for delaying the next time correction amount, and the third delay circuit. Output signal of delay circuit And a correction amount at the present time, a first multiplication circuit, a second multiplication circuit that multiplies both output signals of the first addition circuit and the first delay circuit, the second multiplication circuit and the second A second adder circuit for adding both output signals of the memory circuit and inputting to the second memory circuit, a third multiplying circuit for multiplying the cross correlation by the output signal of the third delay circuit, the accumulating circuit and the A third adding circuit for adding both output signals of the third multiplying circuit and a subtracting circuit for subtracting the output signal of the third adding circuit from the transmission input signal and outputting the subtracted output signal as the transmission output signal are provided.

[Action]

In the conventional learning identification method, the following equations (1) to (3) are calculated from the column vector H (j) of the estimated impulse response at time j.
To find H (j + 1) at time j + 1.

y ′ (j) = H (j) ^t X (j) (1) e (j) = y (j) −y ′ (j) (2) H (j + 1) = H (j) + αe (j) X (J) / X (j) ^t X (j) (3) In contrast, from H (j) to H in the affine projection method
The correction to (j + 1) is performed by the following equations (4) to (5).

y ′ (j) = H (j) ^t X (j) (4) e (j) = y (j) −y ′ (j) (5) H (j + 1) = H (j) + α (β (j ) X (j) + γ (j) X (j−1)) (6) where β (j) and γ (j) are solutions of the following two-dimensional simultaneous equations.

β (j) X (j) ^t X (j) + γ (j) X (j-1) ^t X (j) = e (j) (7) β (j) X (j-1) ^t X ( j) + γ (j) X (j-1) ^t X (j-1) = (1-α) e (j-1) (8) 0 <α <2 where y '(j), y (j), e (j), and X (j) are the pseudo echo signal at time j, the transmission input signal, the residual output signal, and the reception input signal. Hi (j) is an estimated impulse response at time j and tap position i. Further, the vector X (j) of the received input signal at time j and the vector H (j) of the estimated impulse response are X (j) = [x (j), x (j-1), ..., x (j- N + 1)] ^t H (j) = [h0 (j), h1 (j), ..., hN-1 (j)] ^t .

It is known that the learning identification method deteriorates the convergence speed when the input signals have a strong correlation. The affine projection method has been proposed as one of the methods for improving the convergence speed.
Assuming that the true impulse response is G, the learning identification method corrects the orthogonal projection vector of GH (j) to the one-dimensional subspace (straight line) spanned by the latest input signal vector X (j) by α times. On the other hand, the M-dimensional affine projection method uses M continuous input signal vectors X (j), X (j−1), ...
Correction is performed by multiplying the orthogonal projection vector of GH (j) to the M-dimensional space spanned by X (j-M + 1) by α. In general, the distance between a vector and its orthogonal projection on M-dimensional space is
It becomes shorter than the distance to the orthogonal projection to the M-1 dimensional space,
The convergence speed at the time of correction is improved. However, when the input vectors spanning the space are orthogonal to each other (that is, in the case of white noise), the distances are equal. Therefore, when the input signals are correlated, the affine projection method converges faster than the learning identification method.

As described above, in the affine projection method, the convergence speed for an input signal having a correlation is improved, but as the dimension M increases, the number of vectors in the correction formula increases, so that the amount of calculation increases. For example, in the second term on the right side of the equation (6) when M = 2, since there are two vectors X (j) and X (j + 1), multiplication and addition are increased by N tap lengths as compared with the learning identification method. . In this case, the equation (6) one hour before is H (j) = H (j-1) + α (β (j-1) X (j-1) + γ (j-1) X (j-2 ))
(6) '. In equations (6) and (6) ', the same vector X
Since (j-1) exists, the calculation amount is F (j + 1) = F (j) + α (β (j-1) + γ (j)) X (j-1) The addition only increases once. Although F (j + 1) is not a perfect estimated impulse response vector H (j + 1), the relationship of H (j + 1) = F (j + 1) + αβ (j) X (j) is established. Similarly, a pseudo echo y '(j) cannot be generated by F (j) ^t X (j), but y' (j) = H (j) ^t X (j) = F (j) ^t X from the above equation. (J) + αβ (j-1) X (j-1) ^tX (j) can be calculated. Since X (j−1) ^t X (j) has already been calculated to solve the equation (8), new multiplication is only performed once for multiplication and addition.

This method is named the fast affine projection method and expressed in the form of an algorithm, the following expressions (9) to (11) are obtained.

y ″ (j) = F (j) ^t X (j) (9) e (j) = y (j) −y ″ (j) −αβ (j−1) X (j−1) ^t X (j ) (10) F (j + 1) = F (j) + α · (β (j-1) + γ (j)) X (j-1) (11) where β (j), γ (j) Is the solution of the following two-dimensional simultaneous equations, and β (j-1) is the solution one hour before.

βX (j) ^t X (j) + γX (j-1) ^t X (j) = e (j) (12) βX (j-1) ^t X (j) + γX (j-1) ^t X ( j-1) = (1-α) e (j-1) (13) F (j) and H (j) have the following relationship.

H (j + 1) = F (j + 1) + αβ (j) X (j) y ′ (j) = H (j) ^t X (j) = F (j) ^t X (j) + αβ (j-1) X (j-1) ^t X (j) = y ″ (j) + αβ (j-1) X (j-1) ^t X (j) Therefore, the algorithm of this fast affine projection method is similar to the learning identification method. The calculation of can perform exactly the same calculation as the conventional affine projection method.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. First, the received input signal x (j) is transferred to the storage circuit through the switching circuit 80.
Entered in 10. The memory circuit 10 is composed of N memory units and stores the latest N received input signals. That is, when x (j) is input, the oldest x (j−N) is deleted. The memory circuit 11 is also composed of N memory units, and stores the estimated impulse response fi (j) at time j. The impulse response fi (j) and the received input signal x (j-1) are convolutionally calculated by the multiplication circuit 30 and the accumulation circuit 50. On the other hand, in the correlation calculation circuit 60, the received power X (j) ^t X (j) at the current time and the correlation X between the received signal delayed by one time from the received signal.
(J) ^t X (j-1) is obtained. From this binary correlation amount and the residual signal (transmission output) e (j), e (j-1), (1
The correction amount calculation circuit 70 calculates β (j) and γ (j) that satisfy the expressions (2) and (13).

Β (j−1) + γ in the adding circuit 42 according to the equation (11).
(J) is calculated, and the received signal x (j-
1) is multiplied, and the adder circuit 43 corrects fi (j). From the transmission signal y (j), the sum of the output of the accumulation circuit 50 and β (j−1) and the reception correlation X (j) ^t X (j−1) (adding circuit 41
Of the residual signal e of the equation (10)
Find (j).

〔The invention's effect〕

According to the present invention, it becomes possible to realize an FIR type echo canceller which has a high convergence speed for a chromatic signal and a small amount of calculation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 10,11 …… Memory circuit, 20-22 …… Delay circuit (D), 30-3
2 ... Multiplier circuit, 40 ... Subtractor circuit, 41-43 ... Adder circuit, 50 ... Accumulator circuit, 60 ... Correlation calculation circuit, 70 ... Correction amount calculation circuit, 80 ... Switching circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-101131 (JP, A) Proceedings of the Autumn National Conference of the Institute of Electronics, Information and Communication Engineers 1988 [B-2] (Showa 63-8-15) ． P. 175 IEICE Transactions Vol. J67-A No. 2 (Showa 59-2-25), P. 126-132 Proceedings of the 1990 IEICE Spring National Convention [Part 3] (1990-3-5), P. 322

Claims (1)

(57) [Claims] 1. A first memory for storing the latest N received input signals.
A memory circuit; a second memory circuit for storing the impulse response Nth order of the echo path; a first delay circuit for delaying the output signal of the first memory circuit; the first memory circuit and the second memory circuit.
A first multiplication circuit that multiplies both output signals of the storage circuit, an accumulation circuit that integrates the output signals of the first multiplication circuit, and a mutual phase between both output signals of the first storage circuit and the first delay circuit. A correlation calculation circuit that calculates the autocorrelation of the reception input signal, a second delay circuit that delays the transmission output signal, a transmission output signal, an output signal of the second delay circuit, and an output signal of the correlation calculation circuit. A correction amount calculation circuit for obtaining a correction amount of time and a correction amount of next time, a third delay circuit for delaying the next time correction amount, an output signal of the third delay circuit and the correction amount of the current time are added. A second adder circuit for multiplying both output signals of the first adder circuit and the first delay circuit, and a second adder circuit for adding both output signals of the second multiplier circuit and the second memory circuit Second addition time input to the memory circuit A third multiplication circuit that multiplies the cross-correlation and the output signal of the third delay circuit, a third addition circuit that adds both output signals of the accumulation circuit and the third multiplication circuit, and a transmission input signal And a subtraction circuit for subtracting the output signal of the third addition circuit and outputting it as the transmission output signal.