JP2551839B2 - Attenuation waveform generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an attenuated waveform generator.

[Prior Art] Due to advances in semiconductor technology, so-called melody ICs (integrated circuits) in which acoustic signals such as melody are stored in an integrated circuit.
Has been realized.

By the way, there is a softened sound quality by superimposing an envelope signal on the acoustic signal.

In the case of generating an envelope signal, conventionally, an attenuation waveform according to a time constant determined by the values of a resistor and a capacitor has been used.

[Problems to be Solved] It is generally preferable that the envelope signal for the acoustic signal has a time constant of about 0.2 to 1.0 seconds.

However, in order to obtain the above time constant, a large capacity capacitor is required, which is against the miniaturization of the circuit.

Further, it is extremely difficult to integrate a large-capacity capacitor in the integrated circuit, and the capacitor for setting the time constant has to be provided outside the integrated circuit.

An object of the invention relating to the present application is to provide an attenuation waveform generator capable of generating an envelope signal without using a large capacity capacitor.

[Means for Solving the Problem] An attenuation waveform generator according to the present invention is connected in parallel with a storage capacitor that stores electric charge supplied from a power supply unit in a first period and the storage capacitor in a second period. An inverting amplifier circuit in which a voltage difference between input and output is determined according to a voltage difference between both ends of the storage capacitor, a charge / discharge capacitor whose one end is connected to a power supply unit, and a non-conductive state in a first period, A fourth switch that repeats a conducting state and a non-conducting state between the input section of the inverting amplifier circuit and the other end of the charging / discharging capacitor in the second period; and the other end of the charging / discharging capacitor in the first period. Is in a conductive state between the power supply unit and the power supply unit, and is in a non-conductive state when the fourth switch is in a conductive state between the other end of the charge / discharge capacitor and the power supply unit in the second period. And a fifth switch which becomes conductive when the switch of No. 4 is in a non-conductive state, and between the input and output of the inverting amplifier circuit accompanying the transfer of charge from the storage capacitor to the charge and discharge capacitor in the second period. A decrease in the voltage difference causes an attenuated waveform in the output of the inverting amplifier circuit.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

First, the structure of the embodiment shown in FIGS. 1A and 1B will be described.

IA is an inverting amplifier circuit that produces an attenuated waveform at its output. In this embodiment, the inverting amplifier circuit IA has a C-MO.
An inverter composed of S etc. is used.

STC is a storage capacitor, which is connected in parallel to the inverting amplifier circuit IA when the first switch SW1 described later is closed, and between the input and output of the inverting amplifier circuit IA according to the voltage difference across the storage capacitor. The voltage difference is fixed.

CDC is a charge / discharge capacitor, and is charged and discharged by opening / closing a fourth switch SW4 and a fifth switch SW5 described later.

SW1 is a first switch, which conducts during an initialization period described later to charge the storage capacitor STC with electric charges.

SW2 is a second switch, which conducts during an initialization period described later to short-circuit the input and output of the inverting amplifier circuit IA.

SW3 is a third switch, which conducts during a waveform generation period described later and connects the inverting amplifier circuit IA and the storage capacitor STC in parallel.

SW4 is a fourth switch, which opens and closes during a waveform generation period described later, and supplies a charge from the storage capacitor STC to the charge / discharge capacitor CDC in a conductive state (during charging).

SW5 is a fifth switch, which opens and closes during a waveform generation period described later to discharge the electric charge accumulated in the charge / discharge capacitor CDC in the conductive state (during discharge).

Transistors or the like can be used for the first to fifth switches SW1 to SW5.

SG is an acoustic signal generation circuit that generates a predetermined acoustic signal.

CP is a synthesizing circuit, which synthesizes the acoustic signal from the acoustic signal generating circuit SG and the attenuated waveform signal generated at the output of the inverting amplifier circuit IA.

It should be noted that each of the above components is formed in the same integrated circuit.

Next, the operation of this embodiment will be described using the time chart shown in FIG.

In FIG. 2, sw1 to sw5 are switches SW1 to S, respectively.
It shows the open / closed state of W5, which is opened with "0",
"1" indicates the closed state.

2A to 2C show waveforms at points a to c in FIG.

(A) Initialization Period First, the operation in the initialization period (the period of t1 in FIG. 2) in which the charge is stored in the storage capacitor STC and the entire circuit is initialized will be described.

During the initialization period, the open / closed state of each switch SW1 to SW5 is
It becomes like FIG. 1 (A). That is, SW1, SW2 and
SW5 is closed and SW3 and SW4 are open.

The input / output of the inverting amplifier circuit IA is short-circuited because the second switch SW2 is closed. Therefore, the inverting amplifier circuit IA
The input and output voltages of are equal. This voltage becomes, for example, (1/2) VDD when the power supply voltage is VDD.

One terminal of the storage capacitor STC has a first switch SW1
Since it is connected to the power source (voltage VDD) via the, the positive charge is charged from the power source through the first switch SW1. The voltage of the other terminal of the storage capacitor STC is (1/2) V
Since it is DD, the voltage difference between the terminals of the storage capacitor STC is VDD- (1/2) VDD = (1/2) VDD.

(B) Waveform Generation Period Next, the operation in the waveform generation period (period t2 in FIG. 2) in which an attenuation waveform is generated at the output terminal of the inverting amplifier circuit will be described.

In the waveform generation period, as shown in FIG.
The switch SW1 and the second switch SW2 are open and the third switch SW3 is closed. The open / closed states of the fourth switch SW4 and the fifth switch SW5 are alternately inverted.

When the waveform is shifted from the initialization period to the waveform generation period, first, when the fourth switch SW4 is closed and the fifth switch SW5 is opened (during charging), a part of the negative charge stored in the storage capacitor STC is The charge / discharge capacitor CDC is charged through the switch SW4. As a result, the voltage difference between both terminals of the storage capacitor STC is reduced by the amount of the transferred charges.

Next, the fourth switch SW4 opens and the fifth switch S
When W5 is closed (at the time of discharging), the negative charge accumulated in the charge / discharge capacitor CDC is discharged through the fifth switch SW5.

When shifting to charging again, part of the negative charge stored in the storage capacitor STC is charged in the charging / discharging capacitor CDC through the fourth switch SW4 as in the previous charging. As a result, the voltage difference between both terminals of the storage capacitor STC decreases corresponding to the sum of the transferred charge amount and the transferred charge amount during the previous charging. Therefore, the output voltage of the inverting amplifier circuit IA becomes lower than the output voltage at the time of the previous charging.

As described above, the charging operation and the charging operation are alternately repeated. As a result, a staircase-like attenuation waveform as shown in FIG. 2a is generated at the output terminal of the inverting amplifier circuit IA. The shape of the attenuation waveform and the like can be appropriately determined by the opening / closing cycle of the fourth switch SW4 and the fifth switch SW5, the capacitance ratio between the storage capacitor STC and the charge / discharge capacitor CDC, and the like.

The attenuation waveform obtained as described above is input to the synthesizing circuit CP, and the acoustic signals (FIGS. 1b and 2b) output from the acoustic signal generating circuit are superimposed. The combining circuit CP outputs a signal as shown in FIG. 2c. That is, the decay waveform gives an envelope to the acoustic signal.

[Effect] In the present invention, an attenuation waveform can be created without using a large-capacity capacitor, so that the circuit can be downsized and an external capacitor is not needed when integrated.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of FIG. IA ... Inversion amplification circuit STC ... Storage capacitor CDC ... Charge / discharge capacitor SW4 ... Fourth switch SW5 ... Fifth switch t1 ... First period t2 ... Second period

Claims (2)

(57) [Claims] 1. A storage capacitor that stores electric charge supplied from a power supply unit in a first period, and a storage capacitor that is connected in parallel to the storage capacitor in a second period and is turned on according to a voltage difference between both ends of the storage capacitor. An inverting amplifier circuit that determines the voltage difference between the outputs, a charging / discharging capacitor whose one end is connected to the power supply unit, and a non-conductive state during the first period, and the input unit of the inverting amplifier circuit during the second period and the above A fourth state of repeating a conducting state and a non-conducting state between the other end of the charge / discharge capacitor
Of the switch and the other end of the charge / discharge capacitor and the power supply unit in the first period, and the fourth end of the switch between the other end of the charge / discharge capacitor and the power supply unit in the second period. And a fifth switch which is in a non-conductive state when the switch is in a conductive state and which is in a conductive state when the fourth switch is in a non-conductive state. Attenuator waveform generator that produces an attenuation waveform at the output of the inverting amplifier circuit by reducing the voltage difference between the input and output of the inverting amplifier circuit due to the movement of the. 2. The attenuation waveform generator according to claim 1, wherein the inverting amplifier circuit, the storage capacitor, the charge / discharge capacitor, the fourth switch and the fifth switch are formed in the same integrated circuit.