JP2552287B2 - System bus method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a system bus system in which a plurality of boards used in a processor control system such as a controller for a robot are connected to a backplane bus, and particularly hardware implementation. The present invention relates to a system bus system configured such that conventional software can be used as it is even if the density is increased.

[Conventional technology]

A robot controller uses a large number of boards, and the system configuration generally changes. This is because the control robots are used in various ways, and it is desirable to control many types of robots with as few types of control devices as possible. This makes it possible to reduce the development time of hardware and software and ensure economic efficiency.

As a processor control system whose system configuration changes due to such changes in the controlled object, the applicant
"How to assign board slot numbers" dated April 18, 61
Have filed a patent application for In order to make the software compatible, the concept of "logical slot number" is physically introduced to the physical slot number, and even if the system configuration of the hardware changes, each board can be "Logical slot number" is given and control is performed under this "logical slot number" to maintain software compatibility. That is, the physical slot number is given first, the module ID of each board is checked, and the "logical slot number" corresponding to this is checked.
give. As a result, even if the number of boards on the hardware changes, the conventional software can be used as it is.

[Problems to be solved by the invention]

On the other hand, the mounting density of hardware, particularly semiconductors such as LSI, is improving day by day, and the board mounting density is also increasing day by day. Therefore, the function of the hardware that was conventionally mounted on two boards can be mounted on one board.

This example is shown in FIGS. 3 (a) and 3 (b). In the figure, FIG. 3 (a) shows a conventional system configuration, and FIG. 3 (b) shows a new system with a high packaging density. In the figure, 10 is a main processor board, 20 is a sub processor board, 30 is a memory board, and 40 is an axis control board. In FIG. 3B, the mounting density is increased, and the memory processor board 10 and the sub processor board 20 can be mounted on a new board 50. Even in this case, if the conventional software cannot be used as in the case where the system configuration changes, new software development, software conversion, etc. are required.

The object of the present invention is to respond to such hardware advances by the concept of "logical slot number", which is a system bus system configured so that conventional software can be used as it is even when the board mounting density increases. To provide.

[Means for solving problems]

In order to solve the above problems, the present invention has a system bus system in which a plurality of boards are connected to a backplane bus, and has a board in which functional elements made up of a plurality of boards are mounted on one board. A register for storing a logical slot number for each functional element of the board and switching means for switching which of the registers is to be accessed by a predetermined address when assigning a logical slot number to each register, A system bus system is provided, which is characterized in that a logical slot cipher when configured with a board is given to each of the above registers, and the software when configured with a plurality of boards can be used as it is. It

[Action]

For the functions mounted on a single board due to increased packaging density, give a register to store the logical slot number for each function, and give the logical slot number to this register, so that the processor can use each functional element with the logical slot number. Or you can access the board,
Software compatibility can be maintained. Further, when setting a logical slot number, which register of one board to access is determined by a predetermined address.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, 10 is a main processor functional element, and 20 is a sub processor functional element, which are mounted on independent boards in the old system, but are mounted on one board 50 in the new system. 30 is a memory board and 40 is an axis control board. Reference numerals 11, 21, 31 and 41 are registers for storing physical slot numbers and logical slot numbers. Reference numeral 15 is a switching circuit for switching between the main processor functional element 10 and the sub processor functional element 20, which is for accessing one of the functional elements when it is accessed from the bus. It is processed by wear patterns and gate logic.

In FIG. 1, a physical slot number is initially assigned to each register. Register this in registers 11, 21, 31 and
It is shown by the number on the left side of 41. At this time, since the main processor functional element 10 and the sub processor functional element 20 are on the same board, the same physical slot cipher is set. On the other hand, next, the logical slot numbers described on the right side of the registers 11, 21, 31, and 41 are assigned. This logical slot number is the main processor functional element 10
And the logical slot number when the sub processor functional element 20 is mounted on different boards.

This operation will be described based on a time chart. FIG. 2 shows a time chart for setting the logical slot number after the physical slot number is set.
The address buses A4 to A23 become the address cycle 00030XH for the first setting of the logical slot number. In this cycle, the logical slot number is set from the module ID of each functional element and board. Regarding the board 50, when the switching circuit 15 has the address 00030XH, the main processor 10 is accessed, and the physical slot number 0 of the register 11 of the main processor 10 is referred to by its module ID to set the logical slot number 0. Set. This is done in cycle T0. Next, in cycle T1, the module ID of the memory board 30 is read and the corresponding logical slot number 2 is written in the register 31. further,
In cycle T2, read the ID module of axis control board 40,
The logical slot number 3 corresponding to this is written in the register 32. The logical slot number of each board is written in this way. Next, the address buses A4 to A23 become the address 000B0XH. At this address, switching circuit 15 of board 50 selects subprocessor functional element 20 for access from the bus. Therefore, in cycle T3, the module ID of the sub-processor functional element is read and the logical slot number 1 corresponding to it is written in the register 21.

In this way, by writing the logical slot number of each functional element and board to each register and accessing each board by this logical slot number,
Conventional software can be used as it is.

In the above embodiment, the case where the number of the two boards becomes one has been described, but the case where the number of the two or more boards becomes one can be similarly processed.

〔The invention's effect〕

As described above, according to the present invention, even when a plurality of boards are mounted on one board, which register is accessed when setting a register that stores a logical slot number for each functional element and a logical slot number Since a switching means for switching between or not at a predetermined address is provided and each board is accessed by the logical slot number of this register, the software used by the old hardware can be used as it is.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart diagram of an embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are diagrams showing changes in board mounting. . 10 …… Main processor 11 …… Register 15 …… Switching circuit 20 …… Sub processor 21 …… Register 30 …… Main board 31 …… Register 40 …… Axis control board 41 …… Register

Claims (1)

(57) [Claims] 1. A system bus system in which a plurality of boards are connected to a backplane bus has a board in which functional elements configured by a plurality of boards are mounted on one board, and each functional element of the board is provided. A register for storing a logical slot number and a switching means for switching which one of the registers is to be accessed by a predetermined address when assigning a logical slot number to each of the registers are provided. A system bus system characterized in that a logical slot number is given to each of the registers so that the software can be used as it is when it is composed of a plurality of boards.