JP2552534B2 - Substrate bias voltage generation circuit - Google Patents

Description

The present invention relates to a substrate bias voltage generating circuit used for DRAM and the like.

(B) Conventional technology In the DRAM, the substrate bias voltage generation circuit is used.
Holds V _BB negative. A block diagram of such a substrate bias voltage generating circuit is shown in FIG. This substrate bias voltage generation circuit is composed of a level detection circuit (1), a main ring oscillation circuit (2), a sub ring oscillation circuit (3), and substrate bias circuits (4) and (5). The level detection circuit (1) detects the substrate voltage V _BB and controls the operation of the main ring oscillation circuit (2), and stops its operation when the substrate voltage V _BB becomes a negative constant voltage or less. The main ring oscillator circuit (2) and the sub ring oscillator circuit (3) are inverters connected in cascade in odd stages, and the main ring oscillator circuit (2) is an oscillator that generates a large substrate voltage V _BB .
The sub-ring oscillator circuit (3) is an oscillator that generates a small substrate voltage V _BB , is always operating, and aims to maintain the substrate voltage V _BB . The substrate bias circuits (4) and (5) both have a charge pump circuit, and the main ring oscillation circuit (2)
And the substrate voltage V _BB is generated by the output from the sub ring oscillator circuit (3). When the INH input is applied to the main ring oscillator circuit (2) and the sub ring oscillator circuit (3), both of them stop operating. Further, the standby current of each circuit is as described in FIG.

Next, referring to FIG. 3, a circuit diagram of a conventional substrate bias voltage generating circuit is shown. The level detection circuit (1) connects N-channel MOS transistors T ₁ , T ₂ , T ₃ and P-channel MOS transistor T ₄ in cascade, applies a power supply voltage V _DD (5V) to the drain of MOS transistor T ₄ , and Apply substrate voltage V _BB (-3V) to the drain of transistor T ₁
Connect the gate and source of T ₁ and T _{2 respectively} , and
The gates of T ₃ and T ₄ are grounded, and the outputs are obtained from the sources of the MOS transistors T ₃ and T ₄ . The main ring oscillation circuit (2) is formed by connecting three inverters in a ring shape, and the sub ring oscillation circuit (3) is also formed by connecting three inverters in a ring shape. The substrate bias circuits (4) and (5) are charge pump circuits including two stages of inverters, capacitors and diodes.

The operation of this substrate bias voltage generating circuit is as follows. Level detection circuit when substrate voltage V _BB is 0 (1)
The output of is high level because the MOS transistors T ₁ , T ₂ , T ₃ are off and the MOS transistor T ₄ is on, so the gate (6) is opened, and the output of the main ring oscillator circuit (2) is the substrate bias circuit. It is applied to (4). As a result, when the output of the main ring oscillator circuit (2) is at a high level, the capacitor of the substrate bias circuit (4) is charged through the diode whose one side is grounded, and the output of the main ring oscillator circuit (2) becomes low. When level, it outputs a negative substrate voltage through the diode connected to the V _BB pin. Sub ring oscillator circuit (3)
The substrate bias circuit (5) also constantly performs the same operation. When the substrate voltage V _BB becomes −3V, all the MOS transistors T ₁ , T ₂ , T ₃ , T ₄ of the level detection circuit (1) are turned on,
Its output goes low. As a result, the gate (6)
Is closed and the output of the main ring oscillation circuit (2) is cut off, and the substrate voltage V _BB is generated only in the sub ring oscillation circuit (3), and the substrate voltage V _BB is maintained.

As a prior art of such a substrate bias voltage generating circuit, there is JP-A-59-126660 (H01L 27/04).

(C) Problem to be Solved by the Invention However, in the above-described conventional substrate bias voltage generating circuit, when the substrate voltage V _BB is sufficiently charged, the main ring oscillation circuit (2) and the substrate bias circuit (4 ) Is stopped, and the current I ₁ of the level detection circuit (1) is 5 μA, the current I _{3 of the} auxiliary ring oscillator circuit (3) is 20 μA, and the current I _{5 of} the substrate bias circuit (5) is I ₅ = 20 μ in the standby state.
A total current of 45 μA flows. Therefore, the current consumption in the standby state is still large.

(D) Means for Solving the Problems The present invention has been made in view of the above problems, and a substrate bias voltage that greatly improves the conventional problems by providing a Schmitt circuit that eliminates the standby current of the level detection circuit. A generator circuit is provided.

(E) Operation According to the present invention, by providing the Schmitt circuit at the output end of the level detection circuit, when the output of the level detection circuit becomes the low level, the output of the Schmitt circuit is inverted to the high level, and the output of the level detection circuit The feature is that the standby current is eliminated by cutting off the P-channel MOS transistor.

(F) Embodiment An embodiment of the present invention will be described with reference to FIG. The feature of the present invention resides in the level detection circuit, and the main ring oscillation circuit (2), the sub ring oscillation circuit (3), and the substrate bias circuits (4) and (5) provided later are the same as those in FIG. Then, the description is omitted.

The level detection circuit (11) according to the present invention is an N channel MO.
S-transistors T ₁₁ , T ₁₂ and P-channel MOS transistor T
Power supply voltage V _DD (5V) is applied to the drain of the MOS transistor T ₁₃ and substrate voltage V _BB (−3V) is applied to the drain of the MOS transistor T ₁₁ , and the MOS transistor T ₁₃ is connected in cascade.
The gates and sources of ₁₁ and T ₁₂ are connected to each other, the outputs are obtained from the sources of the MOS transistors T ₁₂ and T ₁₃ , and the Schmitt circuit (12), which is the feature of the present invention, is connected to this output. ) Output from the gate of the MOS transistor T ₁₃ and the gate (6) at the latter stage of the main ring oscillator (2) described above.
Is being applied to.

Such a level detection circuit (11) operates as follows. If the substrate voltage V _BB is not sufficiently charged, for example V _BB =
At 0V, the MOS transistors T ₁₁ and T ₁₂ are off, and the MOS transistor T ₁₃ is on. Therefore, the level detection circuit (11)
Output becomes high level and the output of the Schmitt circuit (12) becomes low level, and the MOS transistor T ₁₃ is kept ON. The output of the Schmitt circuit (12) is inverted via the inverter (13) and applied to the gate (6) at the latter stage of the main ring oscillator circuit (2), and the gate (6) is opened to open the substrate voltage V _BB.
Is generated and the substrate is charged. When the substrate voltage V _BB is sufficiently charged and reaches, for example, V _BB = −3V, the MOS transistors T ₁₁ and T ₁₂ of the level detection circuit (11) are turned on and the output of the level detection circuit (11) is changed to V _BB − Pull to 2V _tN −1.4V. Note that V
_tN is the threshold potential of the MOS transistors T ₁₁ and T ₁₂ . Then, the output of this level detection circuit (11) inverts the output of the Schmitt circuit (12) to a high level,
Bias the gate of transistor T ₁₃ to high level and
FF. Further, the gate (6) after the main ring oscillation circuit (2) is closed via the inverter (13) to stop the operation of the main ring oscillation circuit (2) and the substrate bias circuit (4). Here, when the output of the above as the Schmitt circuit (12) is inverted, the threshold voltage changes to the low threshold voltage V _t ^{* _L)} from the high threshold voltage (V _t ^{* _H).} Therefore, even if the substrate bias voltage V _BB fluctuates to some extent due to external noise or the like, the output of the Schmitt circuit (12) is prevented from being inverted to the low level again, and the output of the Schmitt circuit (12) is kept high. The level is maintained. Further, the substrate bias voltage V _BB has an oscillating component associated with the oscillation of the main ring oscillation circuit (2) in the process of being charged to a negative voltage. In this case as well,
By using the Schmitt circuit (12), it is possible to prevent the output from becoming unstable due to the vibration component. As described above, the sub ring oscillator circuit (3) and the substrate bias circuit (5) are always operating and maintain the substrate voltage V _BB .

(G) Effect of the Invention According to the present invention, by connecting the output of the level detection circuit (11) to the Schmitt circuit (12) having a hysteresis characteristic, the Schmitt circuit when the substrate voltage V _BB is sufficiently charged. MO of the level detection circuit (11) by the output of (12)
The S-transistor T ₁₃ is turned off to cut off the standby current of the level detection circuit (11), which has an advantage that the standby current can be reduced by 5 μA as compared with the conventional case. Furthermore, according to the present invention, the Schmitt circuit (1
By adopting 2), even if the substrate voltage V _BB fluctuates to some extent due to external noise, etc., the standby state can be maintained stably, and the standby current can be reduced stably.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a substrate bias voltage generating circuit according to the present invention, FIG. 2 is a block diagram illustrating a general substrate bias voltage generating circuit, and FIG. 3 is a substrate using a conventional level detection circuit. It is a circuit diagram explaining a bias voltage generation circuit. (1) is a level detection circuit, (2) is a main ring oscillation circuit,
(3) is a sub-ring oscillator circuit, (4) and (5) are substrate bias circuits, (6) is a gate, (11) is a level detection circuit,
(12) is a Schmitt circuit, and (13) is an inverter.

Claims (2)

(57) [Claims] 1. A level detection circuit in which a current-cutting MOS transistor and a level-detecting MOS transistor are connected in series between a power supply voltage and a substrate voltage and the connection point is an output, and the output of the level detection circuit is A Schmitt circuit that is input, a ring oscillation circuit that controls oscillation by the output of the Schmitt circuit, and a substrate bias circuit that generates a substrate bias voltage by the output of the ring oscillation circuit are provided, and the output of the Schmitt circuit is For current cut
A substrate bias voltage generating circuit characterized by being applied to the gate of a MOS transistor. 2. A MOS transistor for cutting the current is a P transistor.
2. The substrate bias voltage generating circuit according to claim 1, wherein the substrate bias voltage generating circuit is formed of a channel MOS transistor, and the level detecting MOS transistor is formed of an N channel MOS transistor.