JP2553201B2 - Manufacturing method of light receiving element - Google Patents
Manufacturing method of light receiving elementInfo
- Publication number
- JP2553201B2 JP2553201B2 JP1240138A JP24013889A JP2553201B2 JP 2553201 B2 JP2553201 B2 JP 2553201B2 JP 1240138 A JP1240138 A JP 1240138A JP 24013889 A JP24013889 A JP 24013889A JP 2553201 B2 JP2553201 B2 JP 2553201B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- receiving element
- light receiving
- conductivity type
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Description
【発明の詳細な説明】 〔概 要〕 本発明は、光半導体装置の製造方法に係り、特にイン
ジュウム・リン（InP）系のIII−Ｖ化合物半導体の受光
素子の製造方法に関し、 不純物の再拡散による特性の劣化を引き起こすことな
くアニール処理を行い、暗電流の低減をはかることを目
的とし、 半導体基板上に光吸収層および一導電型増倍層を順次
形成した後、前記増倍層内に反対導電型の不純物を導入
して選択的に反対導電型領域を形成し、前記反対導電型
領域上に誘電体よりなる反射防止膜を形成する工程と、
次いで、前記反射防止膜を選択的に除去して電極形成用
の開口部を形成する工程と、次いで、前記開口部内に高
融点金属よりなる下部電極層を形成する工程と、次い
で、前記反射防止膜の緻密化のための熱処理を行う工程
と、次いで、前記下部電極層上に上部電極層を形成する
工程を含むことを構成とする。The present invention relates to a method for manufacturing an optical semiconductor device, and more particularly to a method for manufacturing a light-receiving element of an indium-phosphorus (InP) -based III-V compound semiconductor, which includes re-diffusion of impurities. For the purpose of reducing the dark current by performing the annealing treatment without causing the deterioration of the characteristics due to, the light absorption layer and the one conductivity type multiplication layer are sequentially formed on the semiconductor substrate, and then the multiplication layer is formed. A step of selectively forming an opposite conductivity type region by introducing impurities of opposite conductivity type, and forming an antireflection film made of a dielectric material on the opposite conductivity type region;
Next, a step of selectively removing the antireflection film to form an opening for electrode formation, a step of forming a lower electrode layer made of a refractory metal in the opening, and then the antireflection It is configured to include a step of performing a heat treatment for densifying the film, and then a step of forming an upper electrode layer on the lower electrode layer.
本発明は、光半導体装置の受光素子の製造方法に係
り、特にインジュウム・リン（InP）系のIII−Ｖ化合物
半導体の受光素子の製造方法に関するものである。The present invention relates to a method for manufacturing a light receiving element of an optical semiconductor device, and more particularly to a method for manufacturing a light receiving element of an indium-phosphorus (InP) -based III-V compound semiconductor.
光通信システムの受信系に用いられる受光素子では、
低暗電流であることが第一に要求される。このため、従
来より暗電流の低減化のため、さまざまの努力が行われ
ている。従来シリコンを使用した受光デバイスではPN接
合へのパッシベーション技術の進歩により充分低暗電流
化が図られているが、長波長帯の受光感度を持つゲルマ
ニュウム素子や化合物半導体素子では充分満足できるパ
ッシベーション膜がなく、現在も研究が進められてい
る。In the light receiving element used for the receiving system of the optical communication system,
First, low dark current is required. Therefore, various efforts have been made to reduce the dark current. Conventional light-receiving devices that use silicon have achieved sufficiently low dark current due to advances in PN junction passivation technology. However, research is still ongoing.
通常ゲルマニュウム素子や化合物半導体素子の場合は
高温処理が出来ないためCVD成長により形成した、シリ
コン酸化膜や窒化膜をパッシベーション膜に使用してい
る。特に化合物半導体素子では、極低温成長が可能なプ
ラズマCVDにより形成するのが普通である。Usually, in the case of germanium element and compound semiconductor element, high temperature treatment cannot be performed, so a silicon oxide film or a nitride film formed by CVD growth is used for the passivation film. In particular, a compound semiconductor device is usually formed by plasma CVD capable of extremely low temperature growth.
従来、CVD膜を半導体のパッシベーション膜として使
用する場合、膜の均一化及び緻密化のため成長温度より
高い温度でアニール処理を施すのが普通であり、このア
ニール処理が受光素子の暗電流を低減させる有力な処理
の一つとなる。第３図は、インジュウム・リン（InP）
系のAPD素子における暗電流とアニール処理温度との関
係を示す。図でわかるように、アニール温度が高い程、
暗電流は減少する。プラズマCVD膜を使用した場合は、
特にアニール処理が不可欠となる。Conventionally, when a CVD film is used as a semiconductor passivation film, it is common to perform annealing treatment at a temperature higher than the growth temperature in order to make the film uniform and dense, and this annealing treatment reduces the dark current of the light receiving element. It becomes one of the powerful processing to make. Figure 3 shows Injuum Phosphorus (InP)
The relation between the dark current and the annealing temperature in the APD device of the system is shown. As you can see in the figure, the higher the annealing temperature,
Dark current decreases. When using plasma CVD film,
In particular, annealing treatment is indispensable.
しかし、受光素子において、接合の形成のための不純
物拡散後、アニール処理を行うと、拡散不純物が再拡散
を起こし拡散層の表面濃度が低下するという問題が発生
する。拡散層の表面濃度が低下すると、電極を形成した
次に接触抵抗が大きくなり、受光素子の特性に悪影響を
及ぼす。However, in the light receiving element, if the annealing treatment is performed after the diffusion of the impurities for forming the junction, the diffusion impurities cause re-diffusion and the surface concentration of the diffusion layer decreases. When the surface concentration of the diffusion layer decreases, the contact resistance increases next after the electrode is formed, which adversely affects the characteristics of the light receiving element.
第４図は、従来のAPD素子の順方向電圧（VF）とアニ
ール温度との関係をしめす。図で明らかなようにアニー
ル温度が高くなると急激にVFが上昇する。この原因は、
アニール処理の温度により、拡散されていた不純物が上
方に再拡散してしまい、表面濃度が減少したためと推定
できる。FIG. 4 shows the relationship between the forward voltage (V F ) of the conventional APD device and the annealing temperature. As is clear from the figure, V F rises rapidly as the annealing temperature increases. This is because
It can be presumed that the diffused impurities were re-diffused upward due to the temperature of the annealing treatment, and the surface concentration decreased.
従って、受光素子の構造から見ると、拡散マスクとし
て使用したCVD膜の場合は拡散工程時の温度により緻密
化が行われるが、反射防止膜（コーティング膜）の場合
は別途高温アニールを行う必要がある。しかし、前に述
べたようにコーティング膜形成後この処理を行うと、不
純物の再拡散により特性の劣化をひきおこす。Therefore, from the viewpoint of the structure of the light receiving element, in the case of the CVD film used as the diffusion mask, the densification is performed by the temperature in the diffusion process, but in the case of the antireflection film (coating film), it is necessary to perform high temperature annealing separately. is there. However, as described above, if this treatment is performed after the coating film is formed, the characteristics are deteriorated due to the re-diffusion of impurities.
本発明は、このような不純物の再拡散による特性の劣
化を引き起こすことなくアニール処理を行い、暗電流の
低減をはかることを目的とする。It is an object of the present invention to reduce the dark current by performing an annealing treatment without causing the deterioration of the characteristics due to such re-diffusion of impurities.
上記課題は本発明によれば、 半導体基板上に光吸収層および一導電型増倍層を順次
形成した後、前記増倍層内に反対導電型の不純物を導入
して選択的に反対導電型領域を形成し、前記反対導電型
領域上に誘電体よりなる反射防止膜を形成する工程と、 次いで、前記反射防止膜を選択的に除去して電極形成
用の開口部を形成する工程と、 次いで、前記開口部内に高融点金属よりなる下部電極
層を形成する工程と、 次いで、前記反射防止膜の緻密化のための熱処理を行
う工程と、 次いで、前記下部電極層上に上部電極層を形成する工
程を含むことを特徴とする受光素子の製造方法によって
解決される。According to the present invention, according to the present invention, a light absorption layer and a one conductivity type multiplication layer are sequentially formed on a semiconductor substrate, and then impurities of the opposite conductivity type are introduced into the multiplication layer to selectively form the opposite conductivity type. A step of forming a region and forming an antireflection film made of a dielectric material on the opposite conductivity type region; and a step of selectively removing the antireflection film to form an opening for electrode formation, Next, a step of forming a lower electrode layer made of a refractory metal in the opening, a step of heat treatment for densifying the antireflection film, and an upper electrode layer on the lower electrode layer. This is solved by a method for manufacturing a light receiving element, which includes a step of forming.
本発明によれば電極形成用開口部全面に形成されたチ
タン膜により不純物原子の再拡散が阻止されると共にチ
タン膜と半導体層との間の接触抵抗が低減される。According to the present invention, the titanium film formed on the entire surface of the electrode forming opening prevents re-diffusion of impurity atoms and reduces the contact resistance between the titanium film and the semiconductor layer.
以下、本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1A図ないし第1F図は本発明の１実施例によるInP系
のAPD（アバランシェ−フォトダイオード）素子の工程
断面図である。1A to 1F are process cross-sectional views of an InP-based APD (avalanche photodiode) device according to an embodiment of the present invention.
まず第1A図に示すように、Ｎ型のInP基板１上にInGaA
sからなる光吸収層10およびInPからなる増倍層11を順
次、例えば液層成長方法によって形成した後、増倍層11
上にプラズマCND法により1000−2000Åの厚さにSiN膜3a
を形成する。First, as shown in FIG. 1A, InGaA is formed on the N-type InP substrate 1.
After the light absorption layer 10 made of s and the multiplication layer 11 made of InP are sequentially formed by, for example, a liquid layer growth method, the multiplication layer 11 is formed.
SiN film 3a with a thickness of 1000-2000Å by plasma CND method
To form.
次に第1B図に示すようにフォトリソグラフィ技術を用
いて所定の位置に開口部４を設け、その開口部にB+等の
Ｐ型不純物を拡散させ、受光層２を形成する。Next, as shown in FIG. 1B, an opening 4 is provided at a predetermined position by using a photolithography technique, and a P-type impurity such as B + is diffused in the opening to form a light receiving layer 2.
次に第1C図に示すように、全露出面に上記第1A図の工
程と同様にプラズマCND法によりSiNからなり、約1800Å
の厚さの反射防止膜3bを形成する。Next, as shown in FIG. 1C, the entire exposed surface is made of SiN by the plasma CND method as in the step of FIG.
To form an antireflection film 3b having the same thickness.
次いで第1D図に示すようにフォトレジスト６を塗布
し、所定の箇所にフォトリソグラフィを用いて開口（コ
ンタクト窓）をあけ、このフォトレジスト６をマスクに
反射防止膜3bを部分的にエッチング除去して、電極用開
口部９を形成する。Then, as shown in FIG. 1D, a photoresist 6 is applied, an opening (contact window) is opened at a predetermined position by photolithography, and the antireflection film 3b is partially removed by etching using the photoresist 6 as a mask. Thus, the electrode opening 9 is formed.
次に第1E図に示すようにTi層を蒸着により全面に形成
し、フォトレジスト６を溶剤により除去すれば、ちょう
ど開口部９の中にTi層が埋められた形に形成される。Next, as shown in FIG. 1E, a Ti layer is formed on the entire surface by vapor deposition, and the photoresist 6 is removed by a solvent, so that the Ti layer is exactly filled in the opening 9.
この後第1F図に示すように500℃以下、好ましくは、4
00〜450℃で反射防止膜3bのアニール処理を行い、電極
材料であるTi,Pt,Auを順序蒸着し、同様なフォトリソグ
ラフィにより所定の電極７を形成する。その後、更にコ
ンタクト抵抗を下げるためアニール処理を行う。After this, as shown in FIG.
The antireflection film 3b is annealed at 00 to 450 ° C., Ti, Pt, and Au which are electrode materials are sequentially deposited, and a predetermined electrode 7 is formed by similar photolithography. After that, an annealing process is performed to further reduce the contact resistance.
第２図は、本発明による構造にしてアニール処理をし
た時のVFとアニール温度との関係である。図に示すよう
に本発明によれば、VFが上昇することなしにアニールが
できることがわかる。これは、Ti層により不純物の再拡
散が阻止されたためとおもわれる。FIG. 2 shows the relationship between V F and the annealing temperature when the structure of the present invention is annealed. As shown in the figure, according to the present invention, it is possible to perform annealing without increasing V F. This is probably because the Ti layer prevented the re-diffusion of impurities.
以上説明したように、本発明によれば受光素子のパッ
シベーション膜として使用しているプラズマCVDによるS
iN膜の高温アニール処理が、素子の順方向特性を劣化さ
せることなく可能となり、素子の低暗電流化がはかれ、
性能向上に寄与するところが大きい。As described above, according to the present invention, the S by plasma CVD used as the passivation film of the light receiving element is used.
High temperature annealing of iN film is possible without deteriorating the forward characteristics of the device, and low dark current of the device is achieved.
It greatly contributes to performance improvement.
第1A図ないし第1F図は本発明によるInP系のAPD（アバラ
ンシェ−フォトダイオード）素子の工程断面図であり、 第２図は本発明に係る受光素子でのアニール温度と順方
向電圧との関係を示す図であり、 第３図は受光素子における暗電流のアニール処理の効果
を示す図であり、 第４図は従来の受光素子でのアニール温度と順方向電圧
との関係を示す図である。 １……Ｎ型InP基板、２……受光層、 3a……SiN膜、3b……反射防止膜、 ４……開口部、５……チタン層、 ６……フォトレジスト、７……電極、 ９……電極用開口部。1A to 1F are process sectional views of an InP-based APD (avalanche photodiode) according to the present invention, and FIG. 2 is a diagram showing the relationship between the annealing temperature and the forward voltage in the light-receiving device according to the present invention. FIG. 3 is a diagram showing an effect of annealing treatment of dark current in the light receiving element, and FIG. 4 is a diagram showing a relationship between an annealing temperature and a forward voltage in the conventional light receiving element. . 1 ... N type InP substrate, 2 ... light receiving layer, 3a ... SiN film, 3b ... antireflection film, 4 ... opening, 5 ... titanium layer, 6 ... photoresist, 7 ... electrode, 9 ... Opening for electrodes.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−48078（ＪＰ，Ａ) 特開 昭60−196979（ＪＰ，Ａ) 特開 昭63−25986（ＪＰ，Ａ) 特開 昭63−114275（ＪＰ，Ａ) 特開 昭63−281480（ＪＰ，Ａ) 特開 昭63−228767（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 62-48078 (JP, A) JP 60-196979 (JP, A) JP 63-25986 (JP, A) JP 63- 114275 (JP, A) JP 63-281480 (JP, A) JP 63-228767 (JP, A)
Claims (1)
倍層を順次形成した後、前記増倍層内に反対導電型の不
純物を導入して選択的に反対導電型領域を形成し、前記
反対導電型領域上に誘電体よりなる反射防止膜を形成す
る工程と、 次いで、前記反射防止膜を選択的に除去して電極形成用
の開口部を形成する工程と、 次いで、前記開口部内に高融点金属よりなる下部電極層
を形成する工程と、 次いで、前記反射防止膜の緻密化のための熱処理を行う
工程と、 次いで、前記下部電極層上に上部電極層を形成する工程
を含むことを特徴とする受光素子の製造方法。1. A light absorption layer and a multiplication layer of one conductivity type are sequentially formed on a semiconductor substrate, and then impurities of opposite conductivity type are introduced into the multiplication layer to selectively form a region of opposite conductivity type. A step of forming an antireflection film made of a dielectric material on the opposite conductivity type region, a step of selectively removing the antireflection film to form an opening for forming an electrode, and a step of forming the opening. A step of forming a lower electrode layer made of a refractory metal in the portion, a step of performing a heat treatment for densifying the antireflection film, and a step of forming an upper electrode layer on the lower electrode layer. A method for manufacturing a light-receiving element, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1240138A JP2553201B2 (en) | 1989-09-18 | 1989-09-18 | Manufacturing method of light receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1240138A JP2553201B2 (en) | 1989-09-18 | 1989-09-18 | Manufacturing method of light receiving element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03102882A JPH03102882A (en) | 1991-04-30 |
| JP2553201B2 true JP2553201B2 (en) | 1996-11-13 |
Family
ID=17055061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1240138A Expired - Lifetime JP2553201B2 (en) | 1989-09-18 | 1989-09-18 | Manufacturing method of light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2553201B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI838047B (en) * | 2022-12-27 | 2024-04-01 | 台亞半導體股份有限公司 | Photodiode structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6248078A (en) * | 1985-08-28 | 1987-03-02 | Fujitsu Ltd | Semiconductor light receiving element |
-
1989
- 1989-09-18 JP JP1240138A patent/JP2553201B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03102882A (en) | 1991-04-30 |
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