JP2553620B2 - MOS type sample hold driver device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample hold driver device using an operational amplifier (hereinafter referred to as an operational amplifier) composed of a MOS transistor.

2. Description of the Related Art A conventional MOS sample hold driver device will be described below.

FIG. 4 shows a circuit configuration of a MOS type sample hold driver device using an operational amplifier (hereinafter referred to as an operational amplifier) composed of a MOS type transistor. Terminal 1 is a positive power supply, terminal 2 is an input voltage to sample and hold, terminal 3 is a reference voltage that controls the operating point of the operational amplifier, and terminal 4
Input a reference voltage to control the driver operating point.
P-channel MOS transistor (hereinafter referred to as P _ch T _r ) 13
Has a source and a substrate connected to the terminal 1 and a gate and a drain connected to the node 8. In P _ch T _r 14, the source and substrate are connected to terminal 1, the gate is connected to node 8, and the drain is connected to node 9, and P _ch T _r 13 and 14 form a current mirror circuit. The N-channel MOS transistor (hereinafter referred to as N _{ch Tr} ) 15 has a source and a substrate at node 7 and a gate at node 6.
, And the drain is connected to the node 8, respectively.
In N _ch T _r 16, the source and substrate are at node 7 and the gate is at node 1.
The drain is connected to node 0, and the drain is connected to node 9. The N _ch T _r 17 has its source and substrate grounded, and its drain connected to the node 7 via the switch 21. Further, a reference voltage is input to the gate from the terminal 3 to form a constant current source. The above P _ch T _r 13,14 and N _ch T _r 15,16,17 constitute an operational amplifier using the nodes 6 and 10 as input terminals. The switch 21 is for reducing the power consumption of the operational amplifier, and is turned on only when it is desired to operate the operational amplifier, and is turned off otherwise. The N _ch T _r 18 connects the source and the substrate to the node 10, the gate to the node 9, and the drain to the terminal 1.
N _ch T _r 19 connects the source and substrate via the switch 22,
Connect the ground and drain to node 10. In addition, the reference voltage is input to the gate from terminal 4, and it becomes a constant current source, and N _ch T
Together with _{r18, it} forms the driver circuit. The switch 22 is a switch for reducing the power consumption of the driver circuit, and is turned on only when it is desired to operate the driver circuit, and is turned off otherwise. The switch 23 is turned on when the driver circuit is operating, outputs the output of the driver circuit to the output terminal 5, and is turned off when the driver circuit is not operating to put the output terminal 5 into a high peak dance state. Is connected between the node 10 and the output terminal 5. The capacitor 11 is for sampling and holding the input voltage input via the switch 20, and is connected between the node 6 and the ground. The switch 20 is a switch for applying the input voltage input to the input terminal 2 to the capacitors 11 and 12 only during the sampling period. Capacitance 12 is parasitic on the gate of N _ch T _r 15 and mainly consists of the capacitance between the gate electrode and the substrate with the gate oxide film as a dielectric and the capacitance between the gate electrode and the source side diffusion layer. It is equivalently expressed as the capacity between the nodes 6 and 7. The capacitor 24, like the capacitor 12, is a parasitic capacitance on the gate of the N _ch T _r 16.

Regarding the sample hold driver device using the operational amplifier composed of the MOS type transistor as described above, its operation is shown in FIG.
The explanation will be given according to the opening and closing timing of 2,23.

First, at t = 0, all the switches 20 to 23 are off, and the operational amplifier and the driver circuit are off. At t = 1, the switch 20 is turned on, and the input voltage is applied to the capacitors 11 and 12 from the input terminal. t = 2
Then, when the switch 20 is turned off, there is no charge input / output path to the node 6, so that the input voltage at the time of t = 2 is 1
Hold by 1,12. The period T1 from t = 1 to t = 2 is the sampling period, and the period from t = 2 to the next turn-on of the switch 20 is the hold period T3. When the switches 21, 22, and 23 are turned on at t = 3, the operational amplifier and the driver circuit are operated, and the capacitances of 11,1
The voltage held at 2 is gain-multiplied by the operational amplifier and output to the output terminal 5 via the switch 23.
At t = 4, when the switches 21, 22, and 23 are turned off, the operational amplifier and the driver circuit are turned off, and the output terminal 5 is in a high impedance state. The period from t = 3 to t = 4 is the output period T2. The sampling operation, the hold operation, and the output operation are performed as described above.

However, in the above conventional device, P _ch T _r 13,14 ,, N _ch
When the operational amplifier composed of T _r 15,16,17 is in the off state, it samples and holds, and then the switch 20 turns off and the capacitance 1
Since there is no charge input / output path to 1 and 12, the state shifts to the ON state. Therefore, when the potential of the node 7 is different between the OFF state and the ON state of the operational amplifier, the potential of the node 6 through the capacitor 12, that is, the potential sampled and held. Had a problem that it fluctuated.

The problems in the above conventional device will be described in more detail.
In the output period T2 of FIG. 5, if the potential of V _{1 is held at} the node 6 and the gate threshold voltage of N _ch T _r 15 is V _TN , the potential V _{2 of the} node 7 becomes V ₂ the V ₁ -V _TN. Next, when the switch 21 at t = 4 of FIG. 5 is turned off, the potential V ₂ at node 7 will approach the positive power supply potential which is input to the terminal 1 through _{N ch T r 15, N ch} T r 15 Will be held before turning off. So V ₂ = V ₁ −V _TN . Then, when the next sampling period comes, the switch 20 is turned on, and when a voltage V ₃ <V ₁ is input to the node 6, V ₃ −V ₂ <V _{TN is set} and N _{ch Tr} 15 is turned off. However, since the potential of the node 6 changes from V ₁ to V ₃ , the potential V ₂ of the node 7 also changes due to the parasitic capacitance 12. This change in V ₂ is connected to node 7. N
_Since there is a parasitic capacitance 24 at the gate of _ch T _r 16, the potential change at node 6 is about 1/2. The sampling period is over,
When the switch 21 turns on in the output period, N _ch T _r 15,16
Turns on, and the potential V _{2 at the} node 7 becomes V ₃ −V _TN . Variation △ V ₂ of the potential V ₂ at node 7 at this time is a _{△ V 2 ≒ (V 1 -V} 3) / 2. Since the parasitic capacitance 12 of ΔV ₂ appears at the node 6 where there is no charge input / output path, the potential V _{3 at the} node 6 is C ₁₂ when the capacitance value of the capacitance ₁₂ is C ₁₂ and C ₁₂ is the capacitance value of the capacitance 11. △ V = △
Only V ₂ · C ₁₂ / (C ₁₁ + C ₁₂ ) changes, and accurate sampling and holding operation cannot be performed.

Conversely, when the voltage V ₃ input to the node 6 in the next sampling period is higher than the voltage V ₁ sampled and held one cycle before, V ₃ −V _TN > V ₂ and N _ch T _r 15
Is not turned off, the potential of the node 7 finally becomes V ₃ −V _TN . Therefore, the potential of the node 7 does not change even if the switch 21 is turned on and the operational amplifier is turned on in the output period, and the node 6 can maintain the sampled and held voltage.

As described above, in the conventional MOS sample hold driver device, when a voltage lower than the voltage sampled and held one cycle before is sampled and held, the sampled and held voltage changes during the hold period,
There is a problem in that a highly accurate sampling and holding operation cannot be performed.

The present invention solves the above-mentioned conventional problems, and a MOS type sample and hold driver capable of performing an accurate sampling and holding operation even when a voltage lower than the voltage sampled and held one cycle before is sampled and held. The purpose is to provide a device.

Means for Solving the Problems In order to achieve this object, a MOS type sample hold driver device of the present invention holds a switch for turning on and off a power supply of an operational amplifier composed of a MOS type transistor, which holds an input voltage. It has a configuration in which the capacitance for operating is turned on also during a period when a switch for applying an input voltage for a specific period is turned on.

Operation With this configuration, even if a voltage lower than the voltage sampled and held one cycle before is applied to the input terminal, during the sampling period, that is, during the period when the charge input / output path to / from the capacitor for holding the input voltage is present, The potential of the node 7 in FIG. 4 can be set to the potential that the node 7 would have during the output period, and the difference between the potential of the node 7 during the sampling period and the hold period and the potential of the node 7 during the output period. Since it disappears, it is possible to eliminate the change in the potential of the node 6, that is, the sampled and held voltage when the hold period shifts to the output period, and it is possible to perform the sample hold operation with high accuracy.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the structure of a MOS type sample and hold driver device according to an embodiment of the present invention, in which 1 is a positive power supply terminal, 2 is an input terminal, 3 and 4 are terminals for inputting a reference voltage, and 5 is an output. Terminals, 11,12,24 are capacitors, 13,14 are P-channel MOS type transistors (hereinafter referred to as P _ch T _r ), 15,1
6, 17, 18, and 19 are N-channel MOS type transistors (hereinafter N _ch
Tr ), 20, 22 and 23 are switches, which have the same configuration as the conventional example. Switch 21 is P _ch T _r 13,14
And N _ch T _r (hereinafter referred to as operational amplifier) operational amplifier composed of 15, 16 and 17 serve to reduce the power consumption of, and on only the output period for outputting the output voltage to operate the operational amplifier. The switch 25 is for turning on the operational amplifier during the sampling period in which the capacitors 11 and 12 sample and hold the input voltage, and is connected in parallel with the switch 21.

Next, the operation of the MOS type sample and hold driver device of this embodiment is shown in FIG.
The opening / closing timings of 1, 22, 23 and 25 will be described.

2, at t = 0, switches 20, 21, 22, 23 and 2
All 5 are off. When the switch 20 and the switch 25 are turned on at t = 1, the input voltage from the input terminal 2 is the capacitance 11,1.
Applied to 2. Also, the operational amplifier is turned on. However, since the switches 22 and 23 are off, the driver circuit remains off and the output terminal 5 is in a high impedance state. Next, at t = 2, the switches 20 and 25 are turned off, and the input voltage at the time of t = 2 is held by the capacitors 11 and 12. Further, since the switch 25 is turned off, the operational amplifier is turned off. In the period from t = 1 to t = 2,
The potential of the node 7 becomes lower than the potential of the node 6 by the gate threshold voltage of N _ch T _r 15, and this period becomes the sampling period T1. From t = 2, the switch 20 and the switch 25 are turned on next. The period until both are turned on is the hold period T3. Then, at t = 3, when the switches 21, 22, and 23 are turned on,
The op amp and the driver circuit composed of N _ch T _r 18,19 turn on, the voltage held by the capacitors 11 and 12 is multiplied by the gain of the op amp and output to the output terminal 5 via the switch 23. To do. t = 4, switches 21,22,23
Is turned off, the operational amplifier and the driver circuit are turned off in the previous period, and the output terminal 5 is in a high impedance state. The period from t = 3 to t = 4 is the output period T2. The sampling operation, the hold operation, and the output operation are performed as described above.

As described above, according to the present embodiment, the switch 25 is turned on during the sampling period T1 and the switch 21 is turned on during the output period T2. The sample-hold operation can be performed with about five times the accuracy of the MOS sample-hold driver device. Furthermore, by turning on the switches 21 and 25 only in both the sampling period T1 and the output period T2, it is possible to reduce the power consumption of the operational amplifier in the previous period.

In the present embodiment, the period during which the switch 25 is turned on is the sampling period T1, which is as shown in FIG.
In the sampling period, t = 1.5, which is longer than the transition time required for the operational amplifier to switch from the OFF state to the ON state in the first half
May be set to the period T4 including the end point t = 2 of the sampling period. That is, the sample value (potential of the node 6) is determined at the moment when the switch 20 is switched from on to off, and therefore the switch 25 may be turned on at least at this moment. However, it is better to turn on the switch 25 during the period including the moment when the switch 20 switches from on to off.
It is possible to prevent that the sampling accuracy cannot be improved due to a timing error due to a delay or the like. However, in order to reduce the power consumption, the switch 25 is turned off except during these periods. In this case, the time during which the switch 25 is on, that is, the time during which the operational amplifier is on in the previous period is further shortened, and the power consumption can be further suppressed.

In this embodiment, P _ch T _r 13,14, N _ch T _r 15,16,17,18,19
Although N _ch T _r and P _ch T _r are replaced with each other, the terminal 1 may be used as a negative power source.

Further, although the capacitor 11 is connected between the node 6 and the ground in the present embodiment, it may be connected between the node 6 and the terminal 1.

In addition, in this embodiment, the configuration of the driver circuit is N _ch T _r 18
Source, substrate is node 10, gate is node 9, drain is terminal 1, N _ch T _r 19 source and substrate are at ground point via switch 22, gate is at input terminal 4 and drain is at node 10.
, And the node 10 is connected to the output terminal 5 via the switch 23. This is N _ch T _r 18
_{May be} P _ch T _r, and its source and substrate are connected to the terminal 1, the gate is connected to the node 9, and the drain is connected to the node 10.

Further, in this embodiment, the switch 22 is connected between the source of the N _ch T _r 19 and the ground, but this is between the terminal 1 and the ground, and between the transistors forming the driver circuit. Anywhere

Further, in the present embodiment, the switch 25 that is turned on during the sampling period and the switch 21 that is turned on during the output period are different from each other, but these switches are switches that are turned on during both the sampling period and the output period. You may replace it with one.

EFFECTS OF THE INVENTION The present invention provides a switch for turning on and off the power supply of an operational amplifier composed of a MOS type transistor, in addition to the output period of the MOS type sample and hold driver device.
By turning on the operational amplifier in the previous period while the input voltage is being applied to the capacitor that holds the input voltage by turning it on during the sampling period as well, the operating point of each node of the operational amplifier is brought close to the operating point in the output period. Even when a voltage lower than the voltage sampled and held before the cycle is sampled and held, the change in the sampled and held voltage due to the capacitance parasitic on the input terminal of the operational amplifier can be reduced,
A highly accurate sample hold operation can be performed.
Further, since the switch turns on the operational amplifier by turning on only the output period and the sampling period, it is possible to realize a MOS type sample and hold driver device that can obtain excellent effects such as reduction of power consumption as a device. It is a thing.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration in one embodiment of the present invention, FIG. 2 is a timing diagram showing switch opening / closing timing, and FIG. 3 is a switch opening / closing timing in another embodiment of the present invention. FIG. 4 is a diagram showing a circuit configuration in a conventional MOS type sample and hold driver device, and FIG. 5 is an opening / closing timing diagram of switches in the conventional technique shown in FIG. 1 …… Positive power supply terminal, 2 …… Input terminal, 3,4 …… Reference voltage terminal, 5 …… Output terminal, 11,12,24 …… Capacity, 13,14…
... P-channel MOS transistor, 15,16,17,18,19 ...
... N-channel MOS type transistor, 20,21,22,23,25 ...
…switch.

Claims (1)

(57) [Claims] 1. An operational amplifier composed of a MOS transistor, a first switch for reducing power consumption by turning off the power of the operational amplifier, and an input terminal connected to the operational amplifier to hold an input voltage. And a second switch for applying an input to the capacitor only for a specific period of time, and when the operational amplifier is operated, at least when the second switch is switched from on to off. A MOS type sample and hold driver device characterized in that a first switch is turned on, and the first switch is turned off at other times.