JP2553673B2 - Field effect transistor - Google Patents

Description

The present invention relates to a high speed and high performance field effect transistor suitable for integrated circuits operating in the microwave range.

III-V compound semiconductors such as GaAs are suitable for high-speed devices because they have higher electron mobility and saturation speed than Si, and GaAs Schottky gate field effect transistors (GaAs MESFETs) have already been widely used as microwave amplification elements. in use. On the other hand, in recent years, research on logic integrated circuits using GaAs has been conducted.

When configuring a logic integrated circuit using field effect transistors, in order to simplify the circuit configuration and reduce power consumption,
The transistor needs to be a normally-off type (the drain current does not flow when the gate voltage is zero). Where GaAs
As shown in FIG. 1, the MESFET operates by forming an n-type active layer 12 on a high resistance substrate 11, using this as a channel layer, and changing the channel thickness by a depletion layer 14 by a Schottky gate 13. is there. Therefore, in order to realize a normally-off FET with MESFET, the thickness of the active layer 12 is precisely controlled so that the gate depletion layer extends to the substrate interface at a gate voltage of zero and closes the channel, that is, the pinch-off voltage is 0 V. Need to control. However,
In a normal GaAs MESFET, the effective donor density of the active layer is about 1 × 10 ¹⁷ cm ^-3 , the height of the Schottky barrier is 0.8 V, and the thickness of the active layer required for the normally-off type FET is about 0.1 μm, which is extremely thin. Precise control of the thickness of such active layers is very difficult. And since the channel is at the interface with the substrate,
There is a drawback that the characteristics are very sensitive to the substrate.

On the other hand, as a normally-off type FET, an MISFET with an inversion channel (Meta
l-Insulator-Semiconductor FET, insulated gate field effect transistor) are advantageous. As shown in FIG. 2, this has a structure in which a p-type layer 22 is formed on a high resistance substrate 21, and a gate metal film 24 is provided so as to face a gate insulating film 23. 2
Reference numerals 5 and 26 are n ⁺ layers in the source and drain regions, and 27 and 28 are source and drain electrodes. At zero gate voltage, there are almost no carriers at the interface between the p-type layer 22 and the insulating film 23, and no current flows, but when a positive voltage is applied to the gate,
The p-type layer is inverted at the interface by electrostatic coupling, electrons are induced, an inverted n-channel is formed, and a drain current flows. Therefore, forming a p-type layer with an appropriate concentration,
It is only necessary to form a gate insulating film having good interface characteristics, and the control of the threshold voltage becomes much easier than in the case of MESFET. However, when GaAs is used as a semiconductor, at present, it can be said that there is no insulating film showing good interface characteristics such as SiO ₂ with respect to Si, and it is almost impossible to form an inverted n-channel. It is possible.
Further, even if an inverted n-channel is formed, its mobility may be considerably smaller than the value in the GaAs bulk crystal, and the advantage of using GaAs is lost.

As described above, the present invention provides a novel high-speed normally-off type field effect transistor using a III-V compound such as GaAs, which has been extremely difficult in the prior art.

The field effect transistor of the present invention has a p-type on a high resistance substrate.
Type first semiconductor layer is provided, an n-type second semiconductor layer having a smaller electron affinity is provided on the first semiconductor layer, and a Schottky type gate electrode is provided on the second semiconductor layer. A source electrode and a drain electrode that are ohmic in the n-channel are formed on the first semiconductor layer at positions separated from the gate electrode in the in-plane direction of the semiconductor layer, and at least under the gate, the second semiconductor layer. Are all depleted, and the depletion layer due to the surface state does not reach the depletion layer generated in the n-type second semiconductor layer due to the difference in electron affinity with the first semiconductor outside the gate, or It is characterized in that the maximum amount of inverted n-channel that has just arrived and can be accumulated on the first semiconductor layer side of the hetero interface is formed.

According to the present invention, the second semiconductor layer under the gate is made equivalent to an insulating film and the first semiconductor layer is inverted at the interface,
Moreover, since the interface is a good heterojunction, an n-channel type high-speed, normally-off FET having a large electron mobility and a small source resistance can be realized. The operating principle of the FET of the present invention will be described below with reference to energy band diagrams and the effect thereof will be described.

FIG. 3 and FIG. 4 (a) are an element structure cross-sectional view and an energy band diagram in a thermal equilibrium state under the gate along the depth direction for explaining the operating principle of the FET of the present invention.
Here, 31 is a high resistance substrate, 32 is a p-type first semiconductor layer, 33
Is an n-type second semiconductor layer having a smaller electron affinity (the difference between the energy level of free electrons in vacuum and the energy level of the lower end of the conduction band) than the first semiconductor, 34 is a gate Schottky electrode, and 35 and 36 are Ohmic source and drain metal electrodes for the n-channel, 37 and 38 are n or n ⁺ regions for reducing the contact resistance, and 35 and 37 form a substantial source electrode and 36 and 38 form a drain electrode. E _C , E _F , and E _V indicate the bottom of the conduction band, the Fermi level, and the top of the valence band, respectively. On the other hand, FIG. 4B shows a case where the second semiconductor layer 33 is thicker than that in FIG. 4A and is not completely depleted under the gate. Here, FIGS. 4A and 4B show the case where the effective donor density of the second semiconductor layer 33 is considerably higher than the effective acceptor density of the first semiconductor layer 32. At the interface between the first semiconductor layer 32 and the second semiconductor layer 33, discontinuity occurs in the conduction band due to the difference in electron affinity between the first semiconductor layer 32 and the second semiconductor layer 33, and due to the contact potential difference, the interface between the first semiconductor layer and the second semiconductor layer Deplete at. Here, when the effective donor density of the second semiconductor layer is considerably higher than the effective acceptor density of the first semiconductor layer, the total charge amount due to the ionized donors in the depletion layer of the second semiconductor layer is Since the total charge amount due to the ionized acceptor in the depletion layer of the layer is larger than the total charge amount, excess electrons are induced on the first semiconductor layer side, that is, the p-type first semiconductor layer is inverted and an n-channel is formed. It The state shown in FIG. 4 (b) represents this state. However, in this state, since the conductive layer exists in the second semiconductor layer, even if the potential of the Schottky type gate electrode is changed, the number of electrons in the n-channel formed by the inversion is changed to operate the transistor. Can not be done. If an ohmic electrode is used instead of the Schottky electrode, the number of electrons in the n-channel can be changed. However, since the barrier height of the second semiconductor with respect to the inversion channel is low, the allowable voltage range is small and the leak current is large. It is not practical. The barrier height depends on the difference in electron affinity, but there are almost no combinations having a large difference, for example, about 0.7 eV, in a combination that normally forms a good heterojunction. On the other hand, in the FET of the present invention, the thickness of the second semiconductor layer 33 is reduced to a value shown in FIG.
Are all depleted like. That is, the total amount of charges due to the ionized donors in the second semiconductor layer 33 is controlled, the bending of the conduction band of the first semiconductor layer 32 is reduced in the equilibrium state, and the degree of inversion is reduced. Therefore, as shown in FIG. 4A, it is possible to realize a normally-off type FET having a high barrier against the inversion channel of the gate 34 and having almost no electrons in the inversion channel. Here, if a positive voltage is applied to the gate, the energy band diagram becomes as shown in FIG. 5, the number of electrons in the inversion channel is greatly increased, and the drain current flows. Here E _'F is the electron quasi-Fermi level. Since the second semiconductor layer 33 is depleted and the barrier height thereof does not change with the gate voltage, the operation of the FET of the present invention is similar to that of the inverting channel type MISFET. Moreover, the advantage over MISFETs is that since a heterojunction interface with a good channel can be formed, the electron mobility can be expected to be a value in the bulk crystal. In addition, the ME
The characteristics are not affected by the substrate unlike SFET. In the present invention, the source and drain electrodes formed on the first semiconductor layer are effectively the n ⁺ regions 3 of FIG.
The 7, 38 can be separated from the gate electrode 34 in a plane, and a great effect can be obtained in ultrahigh frequency and ultrahigh speed operation.
This is because the first semiconductor layer and the second semiconductor layer are formed outside the gate electrode.
Since the semiconductor layer has no junction depletion layer due to the Schottky gate, an inversion n channel can be already formed on the first semiconductor side in the equilibrium state as in FIG. 4 (b). This is because such an overlap between the gate and the n ⁺ region is not necessary, so that the cutoff frequency can be increased without increasing the parasitic capacitance. Furthermore, this structure has a great effect of improving reliability such as increase of breakdown voltage of the gate.

However, when the thickness of the second semiconductor layer 33 is uniform as shown in FIG. 3, if there is a depletion layer due to the surface level on the surface of the second semiconductor layer outside the gate, it is outside the gate region. There is a possibility that a sufficiently low resistance n-channel is not formed at the first semiconductor interface.

Particularly in a compound semiconductor, the surface state density is large, and the band bends on the surface to easily form a surface depletion layer. In III-V group compound semiconductors, the height of the barrier on this surface may be about the same as that of the Schottky barrier (WESpic
er et al; J.Vac.Sci.Technol., 16 (5), 1979). In this case, the n-channel is hardly formed even outside the gate electrode, the source resistance becomes extremely large, and the operation of the FET becomes difficult.

In consideration of this point, the present invention is characterized in that the thickness of the second semiconductor layer 33 is increased outside the gate electrode as shown in FIG. Here, the thickness of the second semiconductor layer outside the gate electrode is made as thick as possible, but its optimum value is to form a low resistance inversion n channel at the interface of the first semiconductor layer, that is,
This is obtained by adding the thickness of the depletion layer generated by the surface level to the thickness of the depletion layer generated in the second semiconductor layer at the interface with the first semiconductor in FIG. 4B. Since the carriers of the inverted n-channel can be secured to the maximum and the second semiconductor layer is all depleted, the reliability such as reduction of gate leak can be improved and the characteristic deterioration due to parasitic capacitance can be prevented.

From the viewpoint of reducing parasitic resistance such as source resistance, the thickness of the second semiconductor layer may be thicker than the above optimum value. At this time, the source and drain metal electrodes may be in contact with any of these semiconductor layers as long as they are ohmic-connected to the inversion channel.

Next, a specific example of the present invention will be described. Semi-insulating
P type with effective acceptor density of 1 × 10 ¹⁵ cm ^-3 on GaAs substrate
GaAs is grown to a thickness of about 3 μm to form a first semiconductor layer.

Furthermore, as a second semiconductor on this, about 0.4e than GaAs
Ga _0.7 Al _0.3 As having a small V electron affinity is used to form an n-type layer having an effective donor density of 1 × 10 ¹⁷ cm ⁻³ and a thickness of 0.11 μm.
As a gate, the barrier height is 0 for n-type Ga _0.7 Al _0.3 As.
A Schottky electrode of about 8 eV is used. The source and drain electrodes are formed of n ⁺ region by ion implantation of Si, Au −
It can be formed by a usual method of heat-treating Ge or the like. Outside the gate electrode, when there is no surface depletion layer, the GaAs layer is inverted at the interface with the GaAlAs layer, and an n-channel having an areal density of about 6 × 10 ¹¹ cm ^-2 is formed. At this time, the thickness of the depletion layer formed on the GaAlAs side is about 0.06 μm. On the other hand, under the gate, the depletion layer due to the contact potential difference of the Schottky junction is also added, the GaAlAs layer is completely depleted, the inversion degree of GaAs is small, and the number of excess electrons is small, as shown in FIG. 4 (a). A normally-off type FET is formed. At this time, the barrier height with respect to the channel viewed from the gate is about 0.9 eV, and the barrier height with respect to the gate viewed from the n channel is 0.4 eV or more, which is a sufficient barrier height. Further, the thickness of depleted GaAlAs equivalent to the gate insulating film of MISFET is as thin as 0.11 μm, which is the same as that of Si MISFET, and a large mutual conductance can be obtained.

In the above, the case where the GaAlAs surface of the second semiconductor layer outside the gate portion is not depleted has been described. However, as described above, when the conduction band is bent on the GaAlAs surface due to the surface level and the surface depletion layer affects the depletion layer on the GaAs interface side, the number of excess electrons in the inversion channel is the same as in the gate portion. , And the source resistance increases. To prevent this, the thickness of the GaAlAs layer should be
The thickness of the depletion layer on the interface side needs to be equal to or greater than the value added. When the band bending on the surface of GaAlAs is 0.5 eV, the thickness of the surface depletion layer is about 0.08 μm, so the thickness of the GaAlAs layer outside the gate electrode should be 0.14 μm or more.

Although the FET of the present invention is most suitable as a normally-off type, it can also be applied as a normally-on type because of its operating principle.

In the above, the case of GaAs and GaAlAs as semiconductors was explained, but GaAs and InGaP or InAlGaP, GaInAs and AlInAs, GaInAs and InP, InP and AlG having large electron affinity differences.
Obviously, the present invention can be applied to other combinations such as aAs.

[Brief description of drawings]

FIG. 1 is a device cross-sectional view showing the structure of a conventional GaAs MESFET, 11 is a high resistance substrate, 12 is an active layer, 13 is a Schottky gate electrode, 14 is a gate depletion layer, 15 is a source electrode, 16 is a drain electrode. Is. FIG. 2 is an element cross-sectional view showing the structure of the MISFET, where 21 is a high resistance substrate, 22 is a p-type layer, 23 is a gate oxide film, 24 is a gate electrode, 25 and 26 are n ⁺ layers in the source and drain regions. , 27 and 28 are source and drain electrodes.
FIG. 3 is a sectional view of an element showing the principle of the FET of the present invention.
1 is a high resistance substrate, 32 is a p-type first semiconductor layer, 33 is an n-type second semiconductor layer, 34 is a gate electrode, 35 is a source electrode,
36 is a drain electrode, and 37 and 38 are n or n ⁺ regions for reducing the contact resistance. FIG. 4 (a) shows the present invention.
It is an energy band diagram in the equilibrium state along the depth direction of the gate portion of the FET, showing the case of the Schottky gate. E _C , E
_F, respectively E _V shows conduction band, the Fermi level, the valence band. FIG. 4B shows an energy band diagram when the FET has the same structure as that of FIG. 4A but the second semiconductor layer is thick and is not completely depleted under the gate. FIG. 5 is an energy band diagram when a positive voltage is applied to the gate of the FET of the present invention shown in FIG. 4 (a). In this case, E '
_F is the pseudo-Fermi level of the electron. FIG. 6 shows the present invention
It is an element sectional view showing a structure of FET.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-7165 (JP, A) JP-A-57-73979 (JP, A) JP-A-59-22367 (JP, A) JP-B-40- 27984 (JP, B1) Yasumi Hikosaka, 2 persons, “ED80-91 Ultra High Speed Transistor (HEMT)” (1980-10-20) The Institute of Electronics, Communication and Communication Engineers P. 43-48 Appl. Phys. Lett. 33 [7] P665-667 (1978-10-1) Japan Jourva (of Applied Physics Vol. 19, No. 5 May 1980, PP. L225-L227)

Claims (1)

(57) [Claims] 1. A p-type first semiconductor layer is provided on a high resistance substrate, and an n-type second semiconductor layer having a smaller electron affinity is provided on the first semiconductor layer. A Schottky-type gate electrode, an n-channel ohmic source electrode and a drain electrode are formed on the second semiconductor layer at positions separated from the gate electrode in the in-plane direction of the semiconductor layer, and at least below the gate. Are all depleted, and the depletion layer due to the surface level does not reach the depletion layer generated in the n-type second semiconductor layer due to the electron affinity difference with the first semiconductor outside the gate. , Or a field effect transistor having the maximum amount of inversion n-channels that has reached or just accumulated on the first semiconductor layer side of the hetero interface.