JP2553680B2 - Digital signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit for receiving a digital signal output from an optical sensor or the like and removing noise of a signal that changes in time series.

2. Description of the Related Art Conventionally, in this type of digital signal processing circuit, when processing a digital signal output from a sensor, a filter circuit is configured for the purpose of removing noise included in the signal.

FIG. 3 shows an example of a conventionally used filter circuit, which is a so-called low-pass filter for the purpose of removing noise in a time shorter than the pulse time width of the sensor signal. In the example of FIG. 3, by reducing the amplitude of the noise pulse shorter than the pulse time width of the sensor signal by the effect of the CR time constant composed of the capacitor and the resistor, the difference in the amplitude is discriminated, and the noise with the small amplitude is discriminated. It is a circuit that tries to remove the pulse.

The conventional circuit as shown in FIG. 3 is also effective when the time width difference between the sensor signal and the noise pulse is large enough to be discriminated as the amplitude difference.

However, in the above-mentioned conventional example, since the time constant circuit is included, there is a problem that if the difference between the time widths of the sensor signal and the noise pulse becomes small, the discrimination cannot be performed.

For example, the pulse train of the sensor signal 25 in FIG. 3 is t _{1 in} FIG.
When the hatched portion is a noise pulse as shown in Fig. 4, when the signal 26 passing through the CR time constant circuit reaches t ₂ in Fig. 4, the voltage V of the battery 23 that gives the threshold value T _{H of the} comparator 24
_{When TH} is _TH of t ₂ in FIG. 4, the signal of the comparator output 27 becomes like t ₃ in FIG. 4, and the noise pulse shown in the hatched portion remains. If the time width of the noise pulse changes, the noise cannot be removed unless the threshold voltage or CR time constant is changed.

The present invention solves such a conventional problem, and an object of the present invention is to provide an excellent digital signal processing circuit capable of removing noise when the pulse time widths of a signal and noise are close to each other. Is.

Means for Solving the Problems To achieve the above object, the present invention provides a flip-flop that operates in synchronization with a clock pulse signal corresponding to the pulse time width of a sensor signal, and provides a pulse shorter than the pulse time width of the sensor signal. Is detected and the detection signal is applied to the sensor signal containing the noise pulse by the gate circuit and the flip-flop to remove the noise pulse.

Operation The present invention having the above-described configuration has the following operations. That is, a clock pulse signal equal to the minimum pulse time width of the sensor signal is used as a synchronization signal for each flip-flop, and the sensor signal is input to the D input of the first D flip-flop, so that the synchronization signal rises or falls. Sampling is done on either side. The output of the first flip-flop is the D of the second D flip-flop.
Connected to the input, the second flip-flop is sampled with a sync signal that is out of phase with the first flip-flop.
On the other hand, the sensor signal is connected to the D input of the third D flip-flop and is sampled by the synchronizing signal in phase with the second flip-flop. The outputs of the second and third flip-flops are connected to the inputs of the exclusive OR gate circuit. Therefore, in the pulse train of the sensor signal, there is a noise pulse in which the logical value of the sensor signal at the time of sampling the first flip-flop and the logical value of the sensor signal at the time of sampling the third flip-flop are different. In this case, the output of the exclusive OR gate circuit is detected as a logical value “1”, and the output of the exclusive OR gate circuit is input to the J, K inputs of the fourth JK flip-flop, and the exclusive OR gate is output. When the circuit output is the logical value "1", both the J and K inputs have the logical value "0", and when the exclusive OR gate circuit output has the logical value "0", the J input has the second flip-flop. The Q output of the second flip-flop is connected to the fourth flip-flop through a gate circuit whose K input is supplied with the output of the second flip-flop. Since the fourth flip-flop is sampled by the synchronizing signal of the same phase as the first flip-flop, if the logical value of the exclusive OR circuit output is "0", the output of the fourth flip-flop after sampling is The sampling results of the first and second flip-flops are inherited, but if the logical value of the exclusive-OR circuit output is "1", the output of the fourth flip-flop after sampling is the previous one. The sampling output of is maintained, at which point the noise pulse can be removed.

Embodiment FIG. 1 shows the structure of an embodiment of the present invention.
In FIG. 1, Si is an input terminal of a sensor signal, CLK is a clock pulse signal, and So is an output terminal of a sensor signal resulting from the operation of the present invention. 1 is a D flip-flop that operates in synchronization with the rise of CLK, and 2 and 3 are
D flip-flops that operate in synchronization with the rising edge of the clock pulse signal in which CLK is inverted by the 4 inverter.
Is a two-input exclusive-OR gate having a negative logic output, 6 and 7 are two-input AND gates, and 8 is a JK flip-flop which operates in synchronization with the rise of CLK, which are connected as shown in FIG.

Next, the operation of the above embodiment will be described. FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG. T ₁ , T ₂ , T ₃ , T ₄ , T ₅ , and T ₆ in FIG. 2 are respectively shown in FIG.
The timings of points corresponding to 9,10,11,12,13,14 are shown. The sensor signal sampled at 1 in FIG. 1 at the timing 15 in FIG. 2 is output from Q in 2 in FIG. 1 at the timing 16 in T _{3 in} FIG. The sensor signal sampled at the timing indicated by 16 is output from Q in FIG. 3 and both outputs have the logical value indicated by T ₅ in FIG. 2 by the exclusive OR gate of the negative logic output. The output of each of 6 and 7 in FIG. 1, which are two AND gates that act as inputs with the logical value and the Q output and output of 2 in FIG. 1, are input to the JK flip-flops of 8 in FIG. Sampled at the timing of T _{6 in} Fig. 2
The logical value shown in is obtained. The sensor signal of T ₁ shown at the timing of 15 to 17 shown in FIG. 2 is when there is no noise pulse, but when there is a noise pulse like the hatched portion of T ₁ shown at the timing of 17 to 20 , The logical values of the result of sampling at the timing of 18 and the result of sampling at the timing of 19 do not match. In that case, at the timing of 19, the exclusive OR gate output changes like T ₅ ,
The logical value "0" is input to both the J input and the K input of the JK flip-flop sampled at the timing of, and the noise pulse is removed without changing the output after sampling.

As described above, according to the above-described embodiment, the sampling pulse time is set by paying attention to the minimum time of the sensor signal pulse, and the pulse train of the sensor signal is set to the rising edge of the sampling pulse,
By sequentially sampling at the falling edge, the sensor signal that changes in a time shorter than the cycle of the sampling pulse can be detected and removed as a noise pulse.

EFFECTS OF THE INVENTION As is apparent, one of the two signals to be exclusive-ORed is sampled with a timing pulse with respect to the input signal, further sampled with a timing pulse having a phase opposite to the timing pulse, and exclusive-ORed. Since the other of the two signals is sampled by the timing pulse having a phase opposite to that of the timing pulse with respect to the input signal, it is sampled at either the rising edge or the falling edge of the timing pulse.
With respect to the noise pulse having a width shorter than that of the timing pulse, the noise pulse positioned at the rising edge and the falling edge of the timing pulse can be detected, and the noise pulse can be removed by the JK flip-flop.

Further, when the noise pulse does not exist on the rising edge and the falling edge of the timing pulse on the input signal, the two signals subjected to the exclusive OR become equal when sampling the input signal. The logic value of the negative logic output is always 1, and it can be sampled without noise pulses.

It has the effect of.

[Brief description of drawings]

1 is a circuit diagram of a digital signal processing circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, FIG. 3 is a filter circuit diagram showing an example of a conventional method, and FIG. The figure is a timing chart showing the operation of FIG. 1,2,3 …… D flip-flop, 4 …… inverter gate, 5 …… exclusive OR gate of negative logic output, 6,7 …… 2
Input AND gate, 8 ... JK flip-flop, 9 ...
Sensor signal, 10 ... Clock pulse signal, 11 ... Flip-flop 2 output signal, 12 ... Flip-flop 3 output signal, 13 ... Gate 5 output signal, 14 ... Flip-flop 8 output signal.

Claims (1)

(57) [Claims] 1. A first D flip-flop for outputting a first output signal sampled at a first timing pulse with respect to an input signal, and a phase opposite to the first timing pulse with respect to the first output signal. A second D flip-flop for outputting a second output signal and a third output signal having a phase opposite to that of the second output signal sampled by the second timing pulse, and the input signal sampled by the second timing pulse. A logical product of the third D flip-flop for outputting the fourth output signal and the negative logical output of the exclusive OR of the fourth output signal and the second output signal with the second output signal is used as the J input. , The fourth output signal and the second
When the logical product of the negative logical output of the exclusive OR of the output signal and the third output signal is K input, and the logical value 0 is input to both the J input and the K input, the previous sampling output is generated. A digital signal processing circuit comprising: a JK flip-flop which is maintained and which, when a logical value of 1 is input to either the J input or the K input, samples the J input with a first timing pulse.