JP2554467B2 - Storage-type photoelectric conversion element control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a photoelectric conversion / accumulation, transfer, holding, and reading operation in a storage-type photoelectric conversion element driven by a basic clock created by a CPU (central processing unit). The present invention relates to an efficient method for controlling a storage-type photoelectric conversion element when reading image information in the mode cycle.

(Technical background of the invention and its problems) Amid the great development of solid-state device technology centered on integrated circuits, storage-type photoelectric conversion elements have also made rapid progress, but are still satisfactory as such. However, it is necessary to devise a great deal on the side of applying this, which makes the image information reading device complicated and expensive.

FIG. 3 shows a block diagram of a circuit system that is generally adopted at present when an image is read by a storage type photoelectric conversion element. This is CC as a storage photoelectric conversion element.
This is a case where the image sensor 10 composed of D (Charge Coupled Device) is used, and the image information is photoelectrically converted / accumulated (IA) in the image section 11 in synchronization with the drive signal CK, and then the holding section.
Transferred to 12 (TA). Then, the electric charge once stored in the holding unit 12 is transferred by the standard scanning method, and the read register 13
Is read out as an image signal PS (RA). These photoelectric conversion / accumulation (IA), transfer (TA), accumulation and read (RA)
The cycle is uniformly controlled by the drive signal CK having a predetermined frequency output from the drive signal generator 1, and its timing is as shown in FIG. In other words, as the read cycle when the image of the screen G1 is first read while timing is set by the drive signal CK, when photoelectric conversion / accumulation (IA) and transfer (TA) are completed (time t
1) The reading (RA) of the held image information (G1) is performed, and the image reading cycle of the next image G2 is started. Further, at the time t2 when the transfer and holding of the image information of the image G2 is completed, the held image information (G2) is read (RA), the reading cycle of the next image G3 is started, and so on. The operation is sequentially repeated.

By the way, as a frequency of the drive signal CK for controlling each of these cycles, a high frequency of several hundred KHz to several MHz is required. This is because if the frequency of the clock signal CK is low, the accumulation time and the transfer time become long, which causes a deterioration in the image data quality such as an increase in dark current or smear.

Therefore, it is necessary to increase the frequency of the clock signal CK, and the peripheral circuit elements are also required to have high speed performance. For this reason, the image information reading device inevitably becomes expensive as a whole. That is, if the frequency of the drive signal CK, which is the drive signal of the image sensor 10, is lowered, not only the total processing time is delayed, but also a problem of quality deterioration such as dark current and smear occurs, and the quality deterioration is prevented. If the frequency of the drive signal CK is increased, the image signal PS will be output at a speed corresponding to it, and a sample and hold circuit for matching the processing speed with the image processing system is required, Fast
This causes the inconvenience of having to use an AD converter.

Therefore, as shown in FIG. 5, the frequency of the drive signal CK from the drive signal generator 1 is switched between high and low, and the image sensor
The high frequency f1 is used in the 10 photoelectric conversion / accumulation, transfer, and retention modes, and the low frequency f2 is used only in the read mode.
A two-frequency driving method using is also proposed. That is,
First, on the first screen H1, photoelectric conversion / accumulation at high frequency f1,
The transfer and the hold are driven, and the reading from the time point t10 when the transfer and the hold are completed is performed at the low frequency f2. And screen H
While 1 is being read, the image information on the next screen HH1 is photoelectrically converted / accumulated, transferred, and retained, but this accumulated charge is due to the low frequency f2, so the dark current increases and the quality is poor. . Therefore, the screen HH1 accumulated during the low frequency f2
Is not used as the image signal PS, the high frequency f
Driven by 1 to read out the charges on the screen HH1, and also to accumulate charges on the next screen H2. The reading of the screen H2 is performed at the low frequency f2, and the image information of the screen HH2 accumulated at this time is not used as the image signal PS. Similarly, photoelectric conversion / accumulation, transfer, and holding are performed at the high frequency f1, the accumulated charge is read at the low frequency f2, and the image data including the dark current component accumulated at the time of reading the low frequency f2 is converted into the image signal. Do not use as PS. Note that such a driving method is applied to reading a still image. Since this driving method does not require high-speed processing, it has the advantage that the IC and circuit system can be configured for low speeds and the output is stable, but on the other hand, the processing speed is reduced by the lower reading frequency. Has a drawback that it becomes slow and a frequency switching circuit is required.

FIG. 6 shows a driving / reading system for a conventional general image sensor 10, which has a pulse oscillator 2 which outputs a clock pulse CP of a predetermined frequency. The clock pulse CP is input to the control timing unit 3 to generate a basic clock 4fcp for driving the image sensor 10 and input to the drive timing unit 14. Drive timing unit 14
Generates the above-mentioned drive signal CK for driving the image sensor 10 based on the basic clock 4fcp, and also generates a vertical synchronization signal Vs indicating synchronization of one screen scan of the image sensor 10.
Generate ync, etc. The entire drive system is controlled by the CPU 20, and a Log conversion memory 21, an input / output port 24 and a RAM 25 are connected via a bus line BS. Image sensor 1
The image signal PS from 0 is input to the amplifier 23 and the image signal PSA
Then, the image signal PSA is digitized (PSD) by the A / D converter 22, converted into a density value using the logarithmic table in the memory 21, and stored in the RAM 25. Further, the CPU 20 and the control timing unit 3 are connected via the input / output port 24, the timing signal TM1 such as start or end is output, and the timing signal TM2 is used to output the A / D timing of the A / D converter 22. , And the data conversion from the ROM 21 is controlled by the timing signal TM2.

In this way, the drive system of the conventional image sensor 10 is the CPU2
Since the CPU 20 manages the pulse oscillator 2 that always oscillates at a constant frequency regardless of 0 and controls the driving of the image sensor 10 and the data reading, the DMA (Direct
Memory Access) is used, but there is a drawback that the control system becomes complicated. Further, when implementing the two-frequency driving method as described above, there is a problem that the control becomes more complicated.

(Object of the Invention) The present invention has been made under the circumstances as described above, and an object of the present invention is to realize storage-type photoelectric conversion that can realize image reading with an inexpensive configuration without degrading the quality of image reading data. It is to provide a method of controlling an element.

(Summary of the Invention) The present invention relates to a method for controlling a storage-type photoelectric conversion element, in which a basic clock for driving the storage-type photoelectric conversion element is
When you read the image information created by the CPU and each mode of photoelectric conversion / accumulation, transfer, holding and reading is 1 cycle,
The frequency of the basic clock in the read mode is set lower than the frequency of the basic clock in the photoelectric conversion / accumulation, transfer and holding modes.

(Embodiment of the Invention) FIG. 1 is a block diagram showing one embodiment of an apparatus to which the method of the present invention is applied, which has no pulse oscillator and is a basic clock input to a drive timing section 14. 4f
cp is given from the CPU 20 via the input / output port 30 by on / off control. Also the basic clock
A / D converter that inputs 4 fcp as timing pulse CLK 22
The output of is stored in the RAM 25 via the input / output port 30 as it is as a true value, or subjected to other processing. In addition to the vertical synchronizing signal Vsync, the driving timing unit 14 generates a pixel clock SP corresponding to one pixel of the image sensor 10 and a horizontal synchronizing signal Hsync indicating the timing of one scan line, and the input / output port 30. After that, each is given to the CPU 20. Therefore, the CPU 20 receives the vertical sync signal Vsync and the horizontal sync signal Hsync from the driving timing unit 14.
By inputting the pixel clock SP and the pixel clock SP, the operation mode of the image sensor 10 can be known.

The processing of the CPU 20 is performed according to the flow shown in FIG. That is, when the image reading operation starts, the CPU20
Turns on the basic clock 4fcp to the "H" level (step
S1), after that, the basic clock 4fcp is turned off at "L" level (step S2), and repeated until the vertical synchronization signal Vsync becomes "L" level (step S3). Vertical sync signal Vsync
Is turned "L", the basic clock 4fcp is turned on / off again (steps S4 and S5), and the basic clock 4fcp is turned on / off until the vertical synchronizing signal Vsync changes from "H" level to "L" level (steps S4 to S9). The process until such a vertical synchronizing signal Vsync changes from "L" to "H" to "L" is A, and in this process A, the CPU 20 oscillates the basic clock 4fcp at a predetermined frequency (for example, 4 MHz). Then, when the vertical synchronizing signal Vsync becomes "L" in step S9, the oscillation is stopped for a predetermined time T (steps S10 and S11). During the steps S1 to S11, photoelectric conversion / accumulation in the image section 11 of the image sensor 10 is performed. When the time T elapses and photoelectric conversion / accumulation ends, the CPU 20 returns to the basic clock 4fc
oscillates p at a specified frequency (for example, 4MHz) (step S1
2) The charges accumulated in the image section 11 during the process A are transferred to the holding section 12 (step S20). Processing A
When the vertical sync signal Vsync changes from "L" to "H" to "L", the charge transfer ends, and the CPU20 lowers the frequency of the basic clock 4fcp for the next data read (for example, A / D converter). 2
(2) A frequency that can be used as the timing pulse CLK) and oscillates (step S30) to drive the effective area on the image sensor 10, that is, whether or not the accumulated charge is in the area to be read as image information. Timing unit 14
It is determined based on the pixel clock SP, horizontal sync signal Hsync, and vertical sync signal Vsync output from the image signal PS in the effective area is processed in steps S40 to S51 described below, and unnecessary data in the invalid area that is not the effective area is processed. Will be described later in step S60
~ Process at S68.

That is, in the present invention, when the clock 4fcp is turned on / off four times, the data of one pixel is output. Therefore, the pixel data in the invalid area is output by turning on / off the basic clock 4fcp four times in steps S60 to S67. By repeating this, invalid data is output for all pixels (step S68). Also in the pixel data of the effective area, when the basic clock 4fcp is turned on / off four times (steps S40 to S45, S47, S49), the effective data of one pixel is output, but at the time of the third on / off (step S4
0 to S45), the data of one pixel previously read is input to the A / D converter 22 via the amplifier 23 (step S46), and then the basic clock 4fcp is turned on (step S47) before the input / output port. The characteristic value calculation (for example, maximum value, minimum value, density value, etc.) of the data input via 30 is performed for a predetermined time (for example, the time within the period of the basic clock 4fcp), and then the basic clock 4fcp is turned off. (Step S49), and if further characteristic value calculation is required thereafter (Step S5)
0). Then, such reading and processing of data for one pixel is repeated for all pixels (step S5).
1).

In the above example, the output of the A / D converter 22 is directly fetched via the input / output port 30, but it may be fetched after being converted into a density value using a logarithmic table or the like. Also, in the above, the basic clock of 4 fcp by the CPU 20
The oscillation is performed at high speed during photoelectric conversion / accumulation and transfer, and at low speed at the time of reading one pixel at a time, but it is not necessarily required to be slow.

(Effects of the Invention) As described above, according to the present invention, since the CPU clock software that does not use the pulse oscillator controls the oscillation and frequency of the basic clock, the hardware configuration can be simplified. Further, since the frequency of the basic clock in the reading mode is set lower than the frequency of the basic clock in the photoelectric conversion / accumulation, transfer and holding modes, accurate image reading can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing an operation example thereof, FIG. 3 is a diagram for explaining driving of an image sensor, and FIGS. 4 and 5 are respectively. FIG. 6 is a block diagram showing an example of a conventional image reading device, and FIG. 6 is a block diagram showing an example of a conventional image reading device. 1 ... driving signal generating section, 2 ... pulse oscillator, 3 ... control timing section, 10 ... image sensor, 11 ... image section, 12 ... holding section, 13 ... reading range, 14 ... driving Timing unit, 20 …… CPU1, 21 …… ROM, 22 …… A / D converter, 25 …… RAM.

Claims (1)

(57) [Claims] 1. A basic clock for driving a storage-type photoelectric conversion element is created by a CPU, and when image information is read with each mode of photoelectric conversion / storage, transfer, holding, and reading as one cycle, in the reading mode. A method of controlling a storage-type photoelectric conversion element, characterized in that the frequency of the basic clock is set lower than the frequency of the basic clock in the photoelectric conversion / accumulation, transfer, and holding modes.