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JP2554593B2 - Power supply circuit - Google Patents
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JP2554593B2 - Power supply circuit - Google Patents

Power supply circuit

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Publication number
JP2554593B2
JP2554593B2 JP5146812A JP14681293A JP2554593B2 JP 2554593 B2 JP2554593 B2 JP 2554593B2 JP 5146812 A JP5146812 A JP 5146812A JP 14681293 A JP14681293 A JP 14681293A JP 2554593 B2 JP2554593 B2 JP 2554593B2
Authority
JP
Japan
Prior art keywords
voltage
resistor
load
circuit
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5146812A
Other languages
Japanese (ja)
Other versions
JPH06332548A (en
Inventor
克宏 古賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Japan Ltd
Original Assignee
Sony Tektronix Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Tektronix Corp filed Critical Sony Tektronix Corp
Priority to JP5146812A priority Critical patent/JP2554593B2/en
Publication of JPH06332548A publication Critical patent/JPH06332548A/en
Application granted granted Critical
Publication of JP2554593B2 publication Critical patent/JP2554593B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Control Of Voltage And Current In General (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電源回路、特に半導体
等の負荷の特性試験に使用するのに好適な電源回路に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit, and more particularly to a power supply circuit suitable for use in a characteristic test of loads such as semiconductors.

【0002】[0002]

【従来の技術】図6は、従来の電圧源/電流源回路を示
す。この回路では、可変電圧発生器10は、例えば、マ
イクロプロセッサの制御に応じた電圧を演算増幅器12
の非反転入力端子に供給する。演算増幅器12の反転入
力端子は、双投スイッチ14の可動接点に接続されてい
る。演算増幅器12の出力信号は、検出抵抗器16を介
して出力端子18に接続される。出力端子18は、緩衝
増幅器20を介して双投スイッチ14の固定接点aに接
続される。検出抵抗器16の両端電圧は、差動増幅器2
2の2つの入力端子に供給され、差動増幅器22の出力
電圧は双投スイッチ14の固定接点bに接続される。出
力端子18は、一端が接地された半導体等の負荷24の
他端に接続される。
2. Description of the Related Art FIG. 6 shows a conventional voltage source / current source circuit. In this circuit, the variable voltage generator 10 outputs a voltage according to control of a microprocessor, for example, to an operational amplifier 12
Supply to the non-inverting input terminal of. The inverting input terminal of the operational amplifier 12 is connected to the movable contact of the double throw switch 14. The output signal of the operational amplifier 12 is connected to the output terminal 18 via the detection resistor 16. The output terminal 18 is connected to the fixed contact a of the double throw switch 14 via the buffer amplifier 20. The voltage across the detection resistor 16 is the differential amplifier 2
2 is supplied to two input terminals, and the output voltage of the differential amplifier 22 is connected to the fixed contact b of the double throw switch 14. The output terminal 18 is connected to the other end of a load 24 such as a semiconductor whose one end is grounded.

【0003】双投スイッチ14の可動接点を固定接点a
に接続すると、電圧源/電流源回路は電圧源モードとな
る。電圧源モードでは、負荷24には入力電圧Viに等
しい出力電圧Voが供給される。このモードでは、入力
電圧Viを変化させ、検出抵抗器16に流れる電流を測
定して負荷の電圧/電流特性を測定できる。また、双投
スイッチ14の可動接点を固定接点bに接続すると、電
圧源/電流源回路は電流源モードとなる。電流源モード
では、検出抵抗器16の両端電圧は入力電圧Viに等し
くなり、入力電圧Viを検出抵抗器16の抵抗値Rで除
算したVi/Rに等しい出力電流Ioが負荷24に供給さ
れる。このモードでは、入力電圧Viを変化させること
で出力電流Ioを変化させ、負荷の両端電圧を測定して
負荷の電流/電圧特性を測定できる。
The movable contact of the double throw switch 14 is a fixed contact a.
When connected to, the voltage source / current source circuit is in the voltage source mode. In the voltage source mode, the load 24 is supplied with the output voltage Vo equal to the input voltage Vi. In this mode, the input voltage Vi can be changed and the current flowing through the detection resistor 16 can be measured to measure the voltage / current characteristic of the load. When the movable contact of the double throw switch 14 is connected to the fixed contact b, the voltage source / current source circuit is in the current source mode. In the current source mode, the voltage across the detection resistor 16 becomes equal to the input voltage Vi, and the output current Io equal to Vi / R obtained by dividing the input voltage Vi by the resistance value R of the detection resistor 16 is supplied to the load 24. . In this mode, the output current Io is changed by changing the input voltage Vi and the voltage across the load can be measured to measure the current / voltage characteristic of the load.

【0004】[0004]

【発明が解決しようとする課題】上述の様に、電圧源/
電流源回路を使用した負荷の電圧/電流測定では、出力
電圧Voは入力電圧Viにより決まり、それに応じた電流
が負荷24に流れる。電圧/電流測定において、入力電
圧Viを増加させていくとき、負荷24に流れる電流Io
が急激に増加し、負荷24を破壊する場合がある。この
様な負荷の破壊を防止する一つの方法は、可変電圧発生
器10の出力端子に、演算増幅器12への電圧供給を制
限可能な電流制限回路(図示せず)を接続することであ
る。電流Ioの増加に伴い差動増幅器24の出力電圧が
所定レベルを超えたことを検出し、その検出信号に応答
して、電流制限回路は電圧供給を遮断する。しかし、通
常の電流制限回路は非線形動作を行うため応答遅延時間
を有するので、負荷電流の増加が急激であると、電圧供
給が遮断される前に負荷が破壊されることになる。ま
た、負荷の破壊を防止する他の方法は、図6で矢印の右
側に示す様に出力端子18及び負荷24間に保護抵抗器
26を挿入することである。しかし、保護抵抗器26
は、負荷に流れる電流Ioを抑制して負荷の破壊防止に
有効であるが、その両端に生じる電圧により負荷に供給
される電圧を低下させる。故に、保護抵抗器26を使用
する場合は、測定値の補正を必要とし、また、抵抗値の
選択の幅も限られていた。
As described above, the voltage source /
In the load voltage / current measurement using the current source circuit, the output voltage Vo is determined by the input voltage Vi, and a current corresponding to the output voltage Vo flows through the load 24. In the voltage / current measurement, when the input voltage Vi is increased, the current Io flowing through the load 24 is increased.
May suddenly increase and destroy the load 24. One method of preventing such load breakdown is to connect a current limiting circuit (not shown) capable of limiting the voltage supply to the operational amplifier 12 to the output terminal of the variable voltage generator 10. It is detected that the output voltage of the differential amplifier 24 exceeds a predetermined level as the current Io increases, and in response to the detection signal, the current limiting circuit cuts off the voltage supply. However, since a normal current limiting circuit has a response delay time because it performs a non-linear operation, if the load current increases rapidly, the load will be destroyed before the voltage supply is cut off. Another way to prevent the load from being destroyed is to insert a protective resistor 26 between the output terminal 18 and the load 24 as shown on the right side of the arrow in FIG. However, the protection resistor 26
Is effective for preventing the load from being destroyed by suppressing the current Io flowing through the load, but lowers the voltage supplied to the load by the voltage generated across the load. Therefore, when the protective resistor 26 is used, it is necessary to correct the measurement value, and the range of selection of the resistance value is limited.

【0005】したがって、本発明の目的は、上述の電流
制限回路及び保護抵抗器を必要とせずに、負荷に過大電
流が流れた時に即座に負荷の破壊を防止できる電源回路
の提供にある。
Therefore, an object of the present invention is to provide a power supply circuit which can immediately prevent the load from being destroyed when an excessive current flows in the load without requiring the above-mentioned current limiting circuit and protection resistor.

【0006】[0006]

【課題を解決する為の手段】本発明の電源回路は、入力
端子から入力抵抗器38を介して入力電圧が電圧増幅器
40に供給され、この電圧増幅器の出力端と出力端子と
の間に第1抵抗器42が接続され、この第1抵抗器42
の両端間電圧を減算回路50で検出し、該減算回路の出
力電圧に第1乗算回路60により第1乗数Mを乗算し、
上記出力端子の電圧に第2乗算回路64により第2乗数
Nを乗算し、第1及び第2乗算回路の出力を第2及び第
3抵抗器62及び66を介して電圧増幅器40の入力端
にそれぞれ帰還することを特徴とする。
According to the power supply circuit of the present invention, the input voltage is supplied from the input terminal to the voltage amplifier 40 through the input resistor 38, and the voltage between the output terminal and the output terminal of the voltage amplifier is first. One resistor 42 is connected, and this first resistor 42
The voltage between both ends of the subtraction circuit is detected by the subtraction circuit 50, and the output voltage of the subtraction circuit is multiplied by the first multiplier M by the first multiplication circuit 60.
The voltage of the output terminal is multiplied by the second multiplier N by the second multiplier circuit 64, and the outputs of the first and second multiplier circuits are input to the input terminal of the voltage amplifier 40 via the second and third resistors 62 and 66. Each is characterized by returning.

【0007】[0007]

【作用】M=0、N≠0のときは、電源回路は電圧源モ
ードで動作する。M≠0、N=0のときは、電流源モー
ドで動作する。M≠0、N=1ときは、等価的に第1抵
抗器の抵抗値のM倍の内部抵抗値を有する電圧源として
動作し、内部抵抗値により、出力電圧の増加による負荷
の短絡時に過大な電流が流れないように抑制できる。
When M = 0 and N ≠ 0, the power supply circuit operates in the voltage source mode. When M ≠ 0 and N = 0, the operation is in the current source mode. When M ≠ 0 and N = 1, it operates equivalently as a voltage source having an internal resistance value that is M times the resistance value of the first resistor, and due to the internal resistance value, it becomes excessive when a load is short-circuited due to an increase in output voltage. It can be suppressed so that a large current does not flow.

【0008】[0008]

【実施例】図1は、本発明の電源回路を示す回路であ
る。入力端子30には、例えば、マイクロプロセッサに
より制御されるデジタル・アナログ変換器(図示せず、
以下DACという)から入力電圧Viが供給される。入
力端子30は、抵抗32を介して演算増幅器34の反転
入力端に接続され、更に、この反転入力端は抵抗器36
を介して演算増幅器34の出力端に接続される。演算増
幅器34の非反転入力端は、例えば接地電位源である基
準電位源に接続される。抵抗器32及び36は等しい抵
抗値rを有し、演算増幅器34と共に増幅率−1の反転
増幅器を構成する。故に、この反転増幅器の出力電圧は
−Viになる。しかし、抵抗器32及び36の抵抗値は
等しい必要はなく、必要に応じて任意の関係でよい。
1 is a circuit showing a power supply circuit of the present invention. The input terminal 30 includes, for example, a digital-analog converter (not shown) controlled by a microprocessor.
The input voltage Vi is supplied from a DAC). The input terminal 30 is connected to an inverting input terminal of an operational amplifier 34 via a resistor 32, and the inverting input terminal is connected to a resistor 36.
Is connected to the output terminal of the operational amplifier 34 via. The non-inverting input terminal of the operational amplifier 34 is connected to a reference potential source which is, for example, a ground potential source. The resistors 32 and 36 have the same resistance value r, and together with the operational amplifier 34, form an inverting amplifier having a gain of -1. Therefore, the output voltage of this inverting amplifier is -Vi. However, the resistance values of the resistors 32 and 36 do not have to be equal, and may have any relationship as needed.

【0009】演算増幅器34の出力端は、抵抗器38を
介して演算増幅器40の反転入力端に接続される。演算
増幅器40の非反転入力端は、基準電位源に接続され
る。演算増幅器40の出力端は、既知の抵抗値RSの抵
抗器42を介して出力端子44に接続される。出力端子
44は、抵抗値RLを有し、一端が基準電位源に接続さ
れた負荷抵抗46の他端に接続される。出力端子44に
は、負荷抵抗器46の抵抗値RL及び出力電流Ioの積に
等しい出力電圧Voが発生する。 Vo=RLIo ・・・(1)
The output terminal of the operational amplifier 34 is connected to the inverting input terminal of the operational amplifier 40 via the resistor 38. The non-inverting input terminal of the operational amplifier 40 is connected to the reference potential source. The output terminal of the operational amplifier 40 is connected to an output terminal 44 via a resistor 42 having a known resistance value RS. The output terminal 44 has a resistance value RL and is connected to the other end of the load resistor 46, one end of which is connected to the reference potential source. At the output terminal 44, an output voltage Vo equal to the product of the resistance value RL of the load resistor 46 and the output current Io is generated. Vo = RLIo (1)

【0010】抵抗器42は、その両端に発生する電圧か
らそれを流れる電流Ioを検出するための電流検出用抵
抗器であり、小電流も検出可能にするために比較的高抵
抗値を有することが望ましい。演算増幅器40の出力端
即ち抵抗器42の入力側端は、抵抗器48を介して演算
増幅器50の非反転入力端に接続され、この非反転入力
端は、更に抵抗器52を介して基準電位源に接続され
る。出力端子44即ち抵抗器42の出力側端は、緩衝増
幅器54及び抵抗器56を介して演算増幅器50の反転
入力端に接続され、この反転入力端は、更に抵抗器58
を介して演算増幅器50の出力端に接続される。抵抗器
48、52、56及び58は等しい抵抗値rを有し、演
算増幅器48と共に増幅率1の減算回路を構成し、その
出力電圧Vsは抵抗器42の両端電圧RSI0に等しい。 Vs=RSI0 ・・・(2)
The resistor 42 is a current detecting resistor for detecting a current Io flowing through it from a voltage generated across the resistor 42, and has a relatively high resistance value so that a small current can be detected. Is desirable. The output terminal of the operational amplifier 40, that is, the input side terminal of the resistor 42 is connected to the non-inverting input terminal of the operational amplifier 50 via the resistor 48, and the non-inverting input terminal is further connected to the reference potential via the resistor 52. Connected to the source. The output terminal 44, that is, the output side end of the resistor 42 is connected to the inverting input end of the operational amplifier 50 via the buffer amplifier 54 and the resistor 56, and this inverting input end is further connected to the resistor 58.
Is connected to the output terminal of the operational amplifier 50 via. The resistors 48, 52, 56 and 58 have the same resistance value r, and together with the operational amplifier 48 form a subtraction circuit with an amplification factor of 1, the output voltage Vs thereof is equal to the voltage RSI0 across the resistor 42. Vs = RSI0 (2)

【0011】演算増幅器50の出力端は乗算器60及び
抵抗器62を介して、緩衝増幅器54の出力端は乗算器
64及び抵抗器66を介して共通に演算増幅器40の反
転入力端に接続される。乗算器60及び64は夫々乗数
M及びNを有し、乗算器60及び64の出力電圧は夫々
MVS=MRSIo及びNVo=NRLIoとなる。乗算器6
0及び64は、高精度の乗算を行うために、好適にはマ
ルチプライングDACを使用する。マルチプライングD
ACを使用した場合、乗数M及びNの範囲は、0≦M≦
1及び0≦N≦1となる。抵抗器38、62及び66
は、説明の簡単のために、等しい抵抗値rを有するもの
とする。
The output terminal of the operational amplifier 50 is commonly connected to the inverting input terminal of the operational amplifier 40 through the multiplier 60 and the resistor 62, and the output terminal of the buffer amplifier 54 is commonly connected through the multiplier 64 and the resistor 66. It The multipliers 60 and 64 have multipliers M and N, respectively, and the output voltages of the multipliers 60 and 64 are MVS = MRSIo and NVo = NRLIo, respectively. Multiplier 6
0 and 64 preferably use a multiplying DAC to perform high precision multiplication. Multiplying D
When AC is used, the range of the multipliers M and N is 0 ≦ M ≦
1 and 0 ≦ N ≦ 1. Resistors 38, 62 and 66
For the sake of simplicity of explanation, it is assumed that they have the same resistance value r.

【0012】上述の電源回路の動作を以下に説明する。
抵抗器38、62及び66は、その一端が演算増幅器4
0の反転入力端子に共通接続され、他端には夫々電圧−
Vi、MRSIo及びNRLIoが供給されているので、共
通接続点の電圧Vcは次の式で表される。 Vc =1/3・(MVS+NVo−Vi) =1/3・(MRSIo+NRLIo−Vi) ・・・(3) 演算増幅器40の反転入力端に電流が流れない、即ちV
c=0になるための条件は次の式で表される。 Vi=MRSIo+NRLIo ・・・(4) 式(4)より出力電流Ioを求めると、 Io=Vi/(MRS+NRL) ・・・(5) 式(1)及び(5)より出力電圧Voを求めると、 Vo=ViRL/(MRS+NRL) ・・・(6) となる。
The operation of the above power supply circuit will be described below.
One end of each of the resistors 38, 62 and 66 has an operational amplifier 4
0 is commonly connected to the inverting input terminal, and the other end has a voltage of −
Since Vi, MRSIo and NRLIo are supplied, the voltage Vc at the common connection point is expressed by the following equation. Vc = 1 / 3.multidot. (MVS + NVo-Vi) = 1 / 3.multidot. (MRSIo + NRLIo-Vi) (3) No current flows through the inverting input terminal of the operational amplifier 40, that is, V
The condition for c = 0 is expressed by the following equation. Vi = MRSIo + NRLIo (4) When the output current Io is obtained from the equation (4), Io = Vi / (MRS + NRL) (5) When the output voltage Vo is obtained from the equations (1) and (5), Vo = ViRL / (MRS + NRL) (6)

【0013】M=0、N≠0である場合、Io及びVo
は、式(5)より Io=Vi/NRL ・・・(7) 式(6)より Vo=Vi/N ・・・(8) となり、出力電圧Voは、負荷抵抗器46の抵抗値に関
係なく、入力電圧Viの1/N倍になり、電源回路は電
圧源モードで動作する。ここで、N=1とすれば、出力
電圧Voは入力電圧Viに等しくなる。また、Nを変化さ
せて出力電圧を変えられるので、例えば、一定の入力電
圧でNを周期的に減少又は増加させることでNの値に応
じたステップ状出力電圧を発生できる。
If M = 0, N ≠ 0, then Io and Vo
From the equation (5), Io = Vi / NRL (7) From the equation (6), Vo = Vi / N (8), and the output voltage Vo is related to the resistance value of the load resistor 46. Instead, the input voltage becomes 1 / N times Vi, and the power supply circuit operates in the voltage source mode. Here, if N = 1, the output voltage Vo becomes equal to the input voltage Vi. Moreover, since the output voltage can be changed by changing N, for example, a stepped output voltage according to the value of N can be generated by periodically decreasing or increasing N with a constant input voltage.

【0014】逆に、M≠0、N=0である場合、Io及
びVoは、式(5)より Io=Vi/MRS ・・・(9) 式(6)より Vo=ViRL/MRS となり、電流Ioは、負荷抵抗器46の抵抗値に関係な
く、入力電圧Vi、抵抗器RS及び乗数Mの定数で決ま
り、電源回路は電流源モードで動作する。ここで、M=
1とすれば、電流Ioは入力電圧Vi及び抵抗器RSのみ
により決まる。また、Mの値に応じて抵抗器42の抵抗
値を等価的に変化させることができ、マルチプライング
DACではなく、1よりも大きい乗数が得られる乗算器
を使用した場合は、Mの値を大きくすることで、抵抗器
42の抵抗値を等価的に大きくできる。
On the contrary, when M ≠ 0 and N = 0, Io and Vo are Io = Vi / MRS from the equation (5) ... (9) From the equation (6), Vo = ViRL / MRS, The current Io is determined by the constants of the input voltage Vi, the resistor RS and the multiplier M, regardless of the resistance value of the load resistor 46, and the power supply circuit operates in the current source mode. Where M =
If it is 1, the current Io is determined only by the input voltage Vi and the resistor RS. In addition, the resistance value of the resistor 42 can be changed equivalently according to the value of M, and when a multiplier that obtains a multiplier greater than 1 is used instead of the multiplying DAC, the value of M By increasing, the resistance value of the resistor 42 can be equivalently increased.

【0015】本発明の主たる特徴は、M≠0、N=1に
した場合にある。N=1であるので、乗算器64を除去
し、演算増幅器54の出力端を抵抗器66に直接に接続
したと同等になる。また、M=1であれば、乗算器60
を除去し、演算増幅器50の出力端を抵抗器62に直接
に接続したと同等になる。この場合のIo及びVoを求め
ると、式(5)より、 Io=Vi/(MRS+RL) ・・・(10) 式(6)より Vo=ViRL/(MRS+RL) ・・・(11) となる。これらの式は、図2に示す様に、等価的に抵抗
値MRSの内部抵抗72を有する電圧値Viの電圧源70
に抵抗値MRSに負荷抵抗器46が接続されていると同
等である。これは、電圧源モードの動作とみなすことが
できる。内部抵抗72は保護抵抗器として働き、入力電
圧Viの増加による負荷電流の過大な増加を保護抵抗器
72により制限できる。しかも、図1の電源回路は図6
の従来の回路と異なり、出力端子44は負荷抵抗器46
に直接に接続されているので、出力電圧Voは負荷抵抗
器46への供給電圧と等しく、従来の様に補正を必要と
せずに、緩衝増幅器54の出力端から負荷抵抗器46へ
の供給電圧を得ることができる。また、図1の電源回路
の電流制限動作は線形動作であるので、遅延時間は電源
回路の応答速度そのものであるので、従来の電流制限回
路より高速に動作し、素子の破壊に至る可能性は低い。
The main feature of the present invention resides in the case where M ≠ 0 and N = 1. Since N = 1, it is equivalent to removing the multiplier 64 and directly connecting the output terminal of the operational amplifier 54 to the resistor 66. If M = 1, the multiplier 60
Is eliminated and the output terminal of the operational amplifier 50 is directly connected to the resistor 62. When Io and Vo in this case are obtained, Io = Vi / (MRS + RL) ... (10) from the equation (5) and Vo = ViRL / (MRS + RL) ... (11) from the equation (6). As shown in FIG. 2, these equations are equivalent to a voltage source 70 having a voltage value Vi having an internal resistance 72 having a resistance value MRS.
Is equivalent to connecting the load resistor 46 to the resistance value MRS. This can be considered as voltage source mode operation. The internal resistor 72 functions as a protection resistor, and the protection resistor 72 can limit an excessive increase in the load current due to an increase in the input voltage Vi. Moreover, the power supply circuit of FIG.
Unlike the conventional circuit, the output terminal 44 has a load resistor 46
Since the output voltage Vo is directly connected to the load resistor 46, the output voltage Vo is equal to the supply voltage to the load resistor 46, and the output voltage Vo from the output terminal of the buffer amplifier 54 to the load resistor 46 does not require correction as in the conventional case. Can be obtained. Further, since the current limiting operation of the power supply circuit of FIG. 1 is a linear operation, the delay time is the response speed of the power supply circuit itself. Therefore, the delay time is higher than that of the conventional current limiting circuit, and there is a possibility that the element is destroyed. Low.

【0016】M≠0、N≠0の場合のIo及びVoは、夫
々式(4)及び(5)で表される。Voを表す式(5)
を変形すると、次のようになる。 Vo=(Vi/N)・RL/{(MRS/N)+RL} ・・・(12) この式は、図3に示す様に、等価的に抵抗値MRS/N
の内部抵抗を有する電圧値Vi/Nの電圧源に負荷抵抗
46が接続されていると同等である。この場合、Nが減
少すると、電圧源74の出力電圧が増加し、これに比例
して電源回路の出力抵抗値である抵抗器76の抵抗値が
増加する。即ち、出力電圧が2倍になれば、出力抵抗値
も2倍になる。その結果、負荷抵抗器46が短絡した場
合の短絡電流は、出力電圧を増加させても一定に保た
れ、破壊的短絡事故を回避することができる。例えば、
この様な電源回路をトランジスタ特性を測定する場合の
コレクタ電圧源に使用すると、図5Aに示す状態から図
5Bに示す様にコレクタ電圧が2倍に増加すると、負荷
抵抗も2倍になり、短絡電流は一定となる。
Io and Vo when M ≠ 0 and N ≠ 0 are expressed by equations (4) and (5), respectively. Formula (5) representing Vo
When is transformed, it becomes as follows. Vo = (Vi / N) .RL / {(MRS / N) + RL} (12) This equation is equivalent to the resistance value MRS / N as shown in FIG.
This is equivalent to connecting the load resistor 46 to a voltage source having a voltage value Vi / N having an internal resistance of. In this case, when N decreases, the output voltage of the voltage source 74 increases, and in proportion to this, the resistance value of the resistor 76, which is the output resistance value of the power supply circuit, increases. That is, when the output voltage doubles, the output resistance value also doubles. As a result, the short-circuit current when the load resistor 46 is short-circuited is kept constant even if the output voltage is increased, and a destructive short-circuit accident can be avoided. For example,
When such a power supply circuit is used as a collector voltage source when measuring transistor characteristics, if the collector voltage doubles from the state shown in FIG. 5A to the one shown in FIG. 5B, the load resistance also doubles and a short circuit occurs. The current is constant.

【0017】図4は、本発明の電源回路の他の実施例で
ある。この回路は、入力部のみが図1の回路と異なる。
図1と同様に、DACからの入力電圧は入力端子に供給
されるが、入力端子30は演算増幅器40の非反転入力
端に直接に接続される。演算増幅器40の反転入力端
は、抵抗器60及び66の共通接続点に接続される。共
通接続点の電圧Vcは、次の式で表される。 Vc=(NRLIo+MIoRS)/2 ・・・(13) 演算増幅器40の反転入力端に電流が流れない、即ちV
i=Vcとすると、 Vi=(NRLIo+MIoRS)/2 ・・・(14) 式(14)よりIoを求めると、 Io=2Vi/(NRL+MRS) ・・・(15) 式(1)及び(15)よりVoを求めると、Vo=2Vi
RL/(NRL+MRS)M=0、N≠0である場合、Io
及びVoを求めると、 Io=2Vi/NRL ・・・(16) Vo=2Vi/N ・・・(17) となり、出力電圧Voは、負荷抵抗器46の抵抗値に関
係なく、入力電圧Viの2/N倍になり、電源回路は電
圧源モードで動作する。逆に、M≠0、N=0である場
合、Io及びVoを求めると、 Io=2Vi/MRS ・・・(18) Vo=2ViRL/MRS ・・・(19) となり、電流Ioは、負荷抵抗器46の抵抗値に関係な
く、入力電圧Viの2倍の電圧、抵抗器RS及び乗数Mの
定数で決まり、電源回路は電流源モードで動作する。
FIG. 4 shows another embodiment of the power supply circuit of the present invention. This circuit differs from the circuit of FIG. 1 only in the input section.
As in FIG. 1, the input voltage from the DAC is supplied to the input terminal, but the input terminal 30 is directly connected to the non-inverting input terminal of the operational amplifier 40. The inverting input of operational amplifier 40 is connected to the common connection point of resistors 60 and 66. The voltage Vc at the common connection point is expressed by the following equation. Vc = (NRLIo + MIoRS) / 2 (13) No current flows to the inverting input terminal of the operational amplifier 40, that is, V
When i = Vc, Vi = (NRLIo + MIoRS) / 2 (14) When Io is calculated from the equation (14), Io = 2Vi / (NRL + MRS) (15) Equations (1) and (15) When Vo is calculated from the above, Vo = 2Vi
If RL / (NRL + MRS) M = 0, N ≠ 0, then Io
And Vo, Io = 2Vi / NRL (16) Vo = 2Vi / N (17), and the output voltage Vo is the same as the input voltage Vi regardless of the resistance value of the load resistor 46. 2 / N times, and the power supply circuit operates in the voltage source mode. On the contrary, when M ≠ 0 and N = 0, when Io and Vo are obtained, Io = 2Vi / MRS (18) Vo = 2ViRL / MRS (19), and the current Io is the load. Regardless of the resistance value of the resistor 46, the power supply circuit operates in the current source mode, which is determined by the double voltage of the input voltage Vi, the resistor RS and the constant of the multiplier M.

【0018】M≠0、N=1にした場合 Io=2Vi/(MRS+RL) ・・・(20) Vo=2ViRL/(MRS+RL) ・・・(21) となる。これらの式は、等価的に抵抗値MRSの内部抵
抗を有する電圧値2Viの電圧源に抵抗値MRSの負荷抵
抗器46が接続されていると同等である。したがって、
図4の回路の動作は、実質的に図1の回路と同等であ
る。
When M ≠ 0 and N = 1, Io = 2Vi / (MRS + RL) (20) Vo = 2ViRL / (MRS + RL) (21) These equations are equivalent to the case where the load resistor 46 having the resistance value MRS is connected to the voltage source having the voltage value 2Vi equivalently having the internal resistance having the resistance value MRS. Therefore,
The operation of the circuit of FIG. 4 is substantially the same as that of the circuit of FIG.

【0019】[0019]

【発明の効果】本発明の電源回路は、保護抵抗器を負荷
に直列接続しなくとも、等価的に第1抵抗器の抵抗値の
M倍の内部抵抗値を有する電圧源として動作し、内部抵
抗値により、出力電圧の増加による負荷の短絡時に過大
な電流が流れないように抑制できる。出力端子は負荷に
直接に接続されているので、出力電圧Voは負荷への供
給電圧と等しく、従来の様に補正を必要とせずに、出力
端子から負荷への供給電圧を得ることができる。
The power supply circuit of the present invention operates as a voltage source having an internal resistance value equivalent to M times the resistance value of the first resistor even if the protection resistor is not connected in series to the load, and The resistance value can prevent an excessive current from flowing when the load is short-circuited due to an increase in the output voltage. Since the output terminal is directly connected to the load, the output voltage Vo is equal to the supply voltage to the load, and the supply voltage from the output terminal to the load can be obtained without the need for correction as in the conventional case.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電源回路を示す回路図。FIG. 1 is a circuit diagram showing a power supply circuit of the present invention.

【図2】図1の回路の動作を説明するための等価回路
図。
FIG. 2 is an equivalent circuit diagram for explaining the operation of the circuit of FIG.

【図3】図1の回路の動作を説明するための等価回路
図。
FIG. 3 is an equivalent circuit diagram for explaining the operation of the circuit of FIG.

【図4】本発明の電源回路の他の実施例を示す回路図。FIG. 4 is a circuit diagram showing another embodiment of the power supply circuit of the present invention.

【図5】本発明の電源回路をトランジスタ特性測定に使
用した場合の動作を説明するためのグラフ図。
FIG. 5 is a graph diagram for explaining an operation when the power supply circuit of the present invention is used for measuring transistor characteristics.

【図6】従来の電圧源/電流源回路を示す回路図。FIG. 6 is a circuit diagram showing a conventional voltage source / current source circuit.

【符号の説明】[Explanation of symbols]

40 電圧増幅器 42 第1抵抗器 60 乗算器 62 第2抵抗器 66 第3抵抗器 40 Voltage Amplifier 42 First Resistor 60 Multiplier 62 Second Resistor 66 Third Resistor

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 入力端子から入力抵抗器を介して入力電
圧が供給される電圧増幅器と、 該電圧増幅器の出力端と出力端子との間に接続された第
1抵抗器と、 該第1抵抗器の両端間電圧を検出する減算回路と、 該減算回路の出力電圧に第1乗数を乗算する第1乗算回
路と、 上記出力端子の電圧に第2乗数を乗算する第2乗算回路
と、 上記第1及び第2乗算回路の出力を上記電圧増幅器の入
力端にそれぞれ帰還する第2及び第3抵抗器とを具える
ことを特徴とする電源回路。
1. A voltage amplifier to which an input voltage is supplied from an input terminal through an input resistor, a first resistor connected between an output terminal of the voltage amplifier and an output terminal, and the first resistor. A subtraction circuit for detecting a voltage between both ends of the voltage regulator, a first multiplication circuit for multiplying an output voltage of the subtraction circuit by a first multiplier, a second multiplication circuit for multiplying a voltage of the output terminal by a second multiplier, A power supply circuit comprising: second and third resistors for respectively feeding back outputs of the first and second multiplication circuits to the input terminals of the voltage amplifier.
JP5146812A 1993-05-26 1993-05-26 Power supply circuit Expired - Lifetime JP2554593B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5146812A JP2554593B2 (en) 1993-05-26 1993-05-26 Power supply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5146812A JP2554593B2 (en) 1993-05-26 1993-05-26 Power supply circuit

Publications (2)

Publication Number Publication Date
JPH06332548A JPH06332548A (en) 1994-12-02
JP2554593B2 true JP2554593B2 (en) 1996-11-13

Family

ID=15416091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5146812A Expired - Lifetime JP2554593B2 (en) 1993-05-26 1993-05-26 Power supply circuit

Country Status (1)

Country Link
JP (1) JP2554593B2 (en)

Also Published As

Publication number Publication date
JPH06332548A (en) 1994-12-02

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