JP2555084B2 - Micro Processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a microprocessor, for example, to a technique effective when used in an embedded program wait circuit for fetching asynchronous data. is there.

[Conventional technology]

In a microprocessor such as the 68000 series which has a program wait circuit, data is received from a peripheral device such as a memory as follows. In the state 0 defined by the clock (machine cycle) signal, the address bus is in a high impedance state. The read / write signal R / W is set to the high level to indicate the read cycle.

In state 1, the address bus is released from the high impedance state.

Address strobe signal ▲ in state 2
▼ is activated at a low level, indicating that there is a valid address signal on the address bus. Peripheral devices such as a memory, the address bus and address strobe signal ▲
In response to ▼, determine whether or not you have been selected. When the selected device such as a memory is judged to have been selected, it becomes operational and sends a read signal to the data bus.

In the program wait circuit, the wait time is set in consideration of the access time of the selected device such as the selected memory. That is, one to a plurality of wait cycles are set for a relatively low speed memory device or the like.

In the state after this wait cycle, it is considered that there is valid data on the data bus and the data is taken in.

For a microprocessor incorporating the above program weight circuit, see, for example, Hitachi, Ltd., September 1985, "Hitachi Microcomputer Data Book 8-bit / 16-bit Microprocessor", page 462.
There is page 463.

[Problems to be solved by the invention]

When the bus master constituting the system is only the above microprocessor, the selected device can be accessed as described above without any problem. However,
When the system has a device that can be a bus master such as a slave microprocessor or a direct memory access device, a control circuit for instructing the above-described wait operation to the devices that have become bus masters is required.

An object of the present invention is to provide a microprocessor capable of simplifying the system.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
A wait signal formed by a built-in program wait circuit is sent to an external terminal.

[Action]

According to the above means, the program wait circuit can be used for the wait operation of the slave microprocessor, the direct memory access control device and the like.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. The microprocessor MPU is, though not particularly limited, a 68000 series microprocessor and has a program wait circuit WAITC built therein. Also, as another bus master, direct memory access controller DMAC
Is provided. The memory devices M1 and M2 are, for example, RAM (random access memory) or ROM (read only memory).
Memory), at least one of which is a relatively slow memory device, such as a dynamic RAM. The input / output device I / O is, for example, a floppy disk memory device or the like.

The microprocessor MPU, the direct memory access control device DMAC, the memory devices M1 and M2, and the input / output device I / O are mutually connected by a bus BUS including an address bus, a data bus, a control signal line, and the like.

The microprocessor MPU incorporates a program wait circuit WAITC, such as the product name "HD64180" sold by Hitachi, Ltd., for example. The program wait circuit WAITC is to insert a wait into a predetermined machine cycle when accessing a relatively low speed memory device or I / O device as described above. In this embodiment, although not particularly limited, the program wait circuit WAITC is an OR (OR)
It is supplied to the central processing unit CPU through the gate circuit G. In addition, this program wait circuit WAITC is designed to supply a wait signal to other bus masters.
It is sent from the external terminal via DV. The wait control signal WAIT output through the drive circuit DV is supplied to the direct memory access control device DMAC in the microcomputer system of this embodiment. The drive circuit DV is
Although not particularly limited, it is composed of an open-drain output circuit and can supply a wait signal from an external terminal. In other words, it enables wired logic at its output terminals. Therefore, the wait signal supplied from the external terminal is supplied to the central processing unit CPU through the OR gate circuit G.

In addition, the program wait circuit WAITC receives the signal from the bus BUS, and receives the signal from the bus BUS.
Is to be a bus master.

The direct memory access control device DMAC has a kind of microcomputer function,
It becomes a bus master in place of the MPU, for example, memory device M1
Alternatively, data is transferred between M2 and the input / output device I / O.
When transferring such data, the memory device M1 or M2
Alternatively, when the speed of the input / output device I / O is relatively slow, the weight insertion as described above is required. In this embodiment, the program wait circuit WAITC incorporated in the microprocessor MPU is activated at a predetermined timing even when the direct memory access controller DMAC acquires the bus use right in place of the microprocessor MPU. To be done. Then, the program wait circuit WAITC generates a wait signal WAIT according to the speed (access cycle) of the memory device or the input / output device which the direct memory access control device DMAC is trying to access, and the direct memory access controller WAITC directly executes the memory through the drive circuit DV. Supply to access control device DMAC.

The direct memory access control device DMAC sends out the predetermined timing signal and address signal according to the machine cycle. The peripheral device such as a memory receives the address signal and determines whether or not it has been selected. When the selected device such as a memory is judged to have been selected, it becomes operational and sends a read signal to the data bus. The program wait circuit sends a wait signal according to the access time of the selected device such as the selected memory. Therefore, direct memory access controller DMAC
Performs one or a plurality of wait cycles before the data fetching cycle and then fetches data assuming that valid data is present on the data bus. That is, one machine cycle (bus cycle) is extended by inserting the designated wait cycle.

FIG. 2 is a block diagram showing another embodiment of the present invention. The microprocessor MPU, the direct memory access control circuit DMAC and the memory are coupled via the BUS. Weight circuit W built in the microprocessor MPU
The ATIC is an address comparator 1 for determining whether the address signal on the BUS is included in a predetermined address range, a counter controller 2 for determining the number of wait cycles, a start timing and an end timing of the wait signal. And a weight signal generator 4 for forming a weight signal. The counter 3 is a gown counter, the initial value of which is given by the counter controller 2, and the countdown is started in response to the falling timing of the address strobe signal ▲ ▼. The wait signal generator 4 forms a low-level wait signal WAIT from the falling edge of the address strobe signal () until the counter value becomes zero. This weight signal WA
IT is sent to the outside of the microprocessor via the departure circuit DV 'and the output terminal T1. The wait signal WAIT sent from the microprocessor MPU is directly supplied to the memory access control device DMAC via BUS. In the direct memory access control device DMAC, the period of one machine cycle is extended according to the period in which the wait signal WAIT is low level. The address strobe signal {circle over ()} is supplied from the direct memory access control device DMAC to the memory to be accessed. When the address strobe signal ▲ ▼ falls, the accessed memory recognizes that the address signal on the BUS has been determined and fetches it internally.
After that, the data read or write operation is executed.
The address strobe signal () is taken into the inside of the microprocessor MPU via the terminal T2 and used to determine the operation timing of the counter 3.

FIG. 3 (A) shows the direct memory access control device DMAC.
Shows a timing chart for reading data from a high speed memory coupled to the BUS. 1 in this example
The machine cycle period is three cycles of the reference internal clock φ. In the first cycle T1, the direct memory access control circuit DMAC sends an address signal on the bus. When the address strobe signal {circle around (1)} falls after sending this address signal, the high-speed memory takes in the address signal internally and the data read operation is started. Then, in the third cycle T3, the read data is sent out on the BUS. The wait signal WAIT is set to the high level during the first cycle T1 to the third cycle T3. The address comparator 1 in the wait circuit WAITC monitors the address signal via the terminal T3 and can recognize that the high speed memory is being accessed.
This is because the counter controller 2 sets the initial value 0 to the counter 3 accordingly.

In FIG. 3B, the direct memory access control device DMAC
7 shows a timing chart when reading data from a low speed memory coupled to a BUS. In this example, one machine cycle period corresponds to five cycles of the reference internal clock φ. That is, a wait cycle between the second cycle T2 and the third cycle T3 depending on the operation speed of the low-speed memory.
TW1 and TW2 are added. In the first cycle T1, the direct memory access control circuit DMAC sends an address signal on the path. After the address signal is transmitted, the address strobe signal ▲ ▼ falls, so that the low-speed memory takes in the address signal internally and the data read operation is started. The address comparator 1 in the wait circuit WAITC monitors the above address signal and can recognize that the low speed memory is being accessed.
In response to this, the counter controller 2 sets the initial value 2 to the counter 3. It should be noted that this initial value can be arbitrarily set according to the operating speed of the memory to be accessed. As a result, the wait signal WAIT is set to the low level for a period of about 2 cycles from the fall time of the address strobe signal (). The timing for detecting the level of the wait signal WAIT is set to the falling point of the clock φ after the second cycle T2. That is, the first wait cycle TW1 is added because the wait signal WAIT is at the low level at the falling time t1 of the clock φ in the second cycle T2. Next, the second wait cycle TW2 is added because the wait signal WAIT is at low level at the time t2 when the clock φ falls in the wait cycle TW1. Next, at the falling edge of clock φ in the second wait cycle TW2, t
Since the wait signal WAIT in 3 is at high level, no wait cycle is added thereafter. Address signal and address strobe signal during wait cycle ▲
▼ maintains the previous state. After that, the data is sent to the data bus until the third cycle T3. Therefore, the direct memory access control device DMAC can take in the data on the bus in the third cycle T3 as valid data.

FIG. 4 is a block diagram of an embodiment of the counter controller 2 in FIG. In this embodiment, four registers 1 to 4 for storing the number of wait cycles are provided. The number of wait cycles is written by the CPU. For example, by writing 00 to register 1, it is indicated that the number of wait cycles is 0,
Writing 01 to register 2 indicates that the number of wait cycles is 1, and register 3 shows 10 cycles.
Is written to indicate that the number of wait cycles is 2, and when 11 is written to the register 4, it is indicated that the number of wait cycles is 3.
AND-gate AG to select either register
1 to AG8 and OR gates OG1 and OG2 are provided. For example, of the output signal lines l1 to l4 of the address comparator 1, when the signal line l3 is set to the high level, the AND gates AG3 and AG7 to which the signal line l3 is connected to the input terminal are selected. As a result, the content 10 of register 3 is the OR gate (OG
1, OG2) to be supplied to the counter 3.

In FIG. 2, the CPU not only executes the wait cycle by the wait signal formed by the wait circuit WAITC, but also can execute the wait cycle by the wait signal formed outside the MPU. That is, the terminal T1 is used as an input / output terminal,
When the wait signal is input, the output driver DV 'is in a high impedance output state. The wait signal is supplied to the CPU via the gate G. When at least one of the two input signals of the gate G becomes low level, a low level output signal is formed.

In this embodiment, in the microcomputer system including the microprocessor MPU incorporating the program wait circuit WAITC as described above, when the direct memory access control device DMAC or slave microprocessor which can be a bus master exists, the master microprocessor is The system can be simplified by using the built-in program wait circuit WAITC. The microprocessor MPU incorporating the program wait circuit WAITC does not use the program wait circuit WAITC because it is in a state in which the bus is opened when another device is the bus master.
Therefore, even if the program wait circuit WAITC is used in another device that operates as a bus master, no problem will occur.

Furthermore, in this embodiment, the wired logic is enabled as the drive circuit DV for sending the signal formed by the program wait circuit WAITC to the external terminal. As a result, the wait operation from the wait control circuit provided outside the microprocessor MPU can be performed if necessary.

The operational effects obtained from the above embodiment are as follows.

(1) The weight of a device that can be another bus master such as a slave microprocessor or a direct memory access control device with a simple configuration in which a wait signal formed by a built-in program wait circuit is sent to an external terminal. It can be used for operation. As a result, it is possible to obtain an effect that a microcomputer system including a plurality of devices that can be bus masters can be simplified.

(2) By using an output circuit such as open drain capable of wired logic as a drive circuit for sending a wait signal formed by the built-in program wait circuit to an external terminal, a wait signal is output from the external terminal. Can be supplied. This has the effect of diversifying the weight fibers in the microprocessor.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the bus may be one that transmits data signals and address signals in time series. That is, the slave processor, the direct memory access control device, or the like may transmit the address and the data to the address bus of the microprocessor in a time division manner. Also, a terminal to which the output signal of the program wait circuit is transmitted,
The terminal provided with a wait signal from the outside, which is provided as necessary, may be an independent terminal.

INDUSTRIAL APPLICABILITY The present invention can be widely used in microprocessors incorporating a program wait circuit.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, by sending a wait signal formed by the built-in program wait circuit to an external terminal, it can be used for a wait operation of a device that can be another bus master such as a slave microprocessor or a direct memory access control device. Therefore, the system can be simplified.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIGS. 3 (A) and 3 (B) are block diagrams of FIG. FIG. 4 is a timing chart for explaining the operation of the figure, and FIG. 4 is an example of the counter controller 2 shown in FIG. WAITC: Program wait circuit, DMAC: Direct memory access control device, M1,2: Memory device, I / O: Input / output device, CPU: Central processing unit, MPU: Microprocessor.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Shiro Baba 1450, Kamimizumoto-cho, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi Ltd. (72) Jiro Kashio 1099, Ozenji, Tama-ku, Kawasaki, Kanagawa Hitachi, Ltd. Manufacturing Systems Development Laboratory (72) Inventor Shiro Baba 1450, Kamimizuhoncho, Kodaira-shi, Tokyo Stock company Hitachi Ltd. Musashi Factory (72) Inventor, Yasushi Akao 1450, Kamimizumoto-cho, Kodaira, Tokyo Hitachi Ltd. (72) Inventor Toshio Okochi, Toshio Okochi, 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hiritsu Manufacturing Co., Ltd. (56) Reference JP-A-60-151760 (JP, A) JP-A-63-53669 ( JP, A)

Claims (1)

(57) [Claims] 1. A weight for monitoring a CPU and an address signal on an external bus, changing a level change timing of a wait signal according to a predetermined program, and defining a timing for fetching data on the external bus. A wait signal forming circuit that forms a signal, and a wired logic that allows the wait signal to be sent to the outside of the CPU and the microprocessor and from which the wait signal can be input to the CPU from the outside. A microprocessor characterized in that the formed output circuit is formed in one semiconductor integrated circuit.