JP2555903B2 - Power amplifier - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to power amplifiers, and more particularly to P-channel and N-channel amplifiers.
The present invention relates to a high-efficiency class B power amplifier that performs a push-pull operation of a channel FET (field effect transistor) in a source-grounded amplification type.

[Conventional technology]

Conventionally, as shown in FIG. 2, this type of power amplifier has first and second input signal terminals 11 and 12 which are common to each other.
Differential amplifiers 51, 52, and first and second differential amplifiers 51, 52
P-channel MOS field effect transistor (hereinafter referred to as PchFET) 31 and N-channel MOS field effect transistor (hereinafter referred to as NchFET) 3 which receives the output signals V ₅₁ and V ₅₂ of each of them at their gate electrodes and performs push-pull operation in a source-grounded amplification format
An output amplification section 41 consisting of two is provided.

Input signal V ₁₁ from the input signal terminal 11 is applied to the inverting input terminal of the first and second differential amplifier 51 and 52 (+ terminal), also the input signal V ₁₂ from the input signal terminal 12 , The non-inverting input terminals of the first and second differential amplifiers 51 and 52 (-
Terminal). Now, when V ₁₁ > V ₁₂ , the output voltages V ₅₁ , V ₅₂ of the first and second differential amplifiers ₅₁ , ₅₂ rise, so the PchFET 31 is cut off and the NchFET 32 is conductive. Drive the load via the output signal terminal 13. When V ₁₁ <V ₁₂ , the output voltages V ₅₁ , V ₅₂ of the first and second differential amplifiers ₅₁ , ₅₂ drop, so the NchFET 32
Is in the cut-off state, the PchFET 31 is in the conductive state, the load is driven through the output signal terminal 13, and the input signals V ₁₁ and V
Drive the load alternately according to ₁₂ .

By the way, in order to operate the power amplifier with high efficiency, it is necessary to suppress the current flowing through the Pch and Nch FETs 31 and 32 when there is no signal (hereinafter, referred to as a through current) to a certain value or less. Therefore, the first and second differential amplifiers ₅₁ , ₅₂ are controlled so that the output voltages V ₅₁ , V _{52 of} the first and second differential amplifiers ₅₁ , ₅₂ are close to the threshold voltages of the Pch and Nch FETs 31, 32. Each transistor that constitutes the amplifiers 51 and 52 is selected and adjusted.

[Problems to be Solved by the Invention]

In the conventional power amplifier described above, in order to suppress the shoot-through current to a certain value or less, each transistor that constitutes the differential amplifier is selected and adjusted so that the output voltage of the differential amplifier is equal to that of Pch and NchFET. It is designed to be close to the threshold voltage. However, because the threshold voltage of the MOS transistor and the output voltage setting of the differential amplifier change due to changes in ambient temperature or changes in bias voltage, the shoot-through current also changes significantly, resulting in high efficiency and low power consumption. Power amplification cannot be performed.

An object of the present invention is to provide a power amplifier capable of performing stable power amplification with high efficiency and low power consumption by keeping the output voltage of the differential amplifier unit always near the threshold voltage of Pch and NchFETs. To provide.

[Means for solving the problem]

The power amplifier of the present invention applies first and second differential amplifiers having common input signal terminals and outputs of the first and second differential amplifiers to gate electrodes of Pch and NchFETs, respectively. In a power amplifier including an output amplification section that operates in a push-pull operation in a source-grounded amplification format, a comparison Pch and NchFET having substantially the same characteristics as the Pch and NchFET, a threshold voltage of the comparison PchFET, and the The first comparison unit that compares the output voltage of the first differential amplification unit and outputs the difference, and compares the threshold voltage of the comparison NchFET and the output voltage of the second differential amplification unit. And a second comparison unit that outputs the difference, a first filter that receives the output of the first comparison unit and outputs an average value thereof, and the second filter
A second filter for receiving the output of the comparison unit of the first filter and outputting the average value thereof, and outputting the output of the first filter by the first filter.
To control the output level of the first differential amplification section, and feed back the output of the second filter to the second differential amplification section to control the second difference. This is a configuration for controlling the output voltage of the dynamic amplification unit.

〔Example〕

 The present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which first and second differential amplifier units 21 and 22 having common input signal terminals 11 and 12 and first and second differential amplifier units are provided. Pch and Nch FETs 31 and 32 that receive the output signals V ₂₁ and V ₂₂ of the parts ₂₁ and ₂₂ at their gate electrodes and perform push-pull operation in the source grounded amplification format
Comparing Pch and NchFETs 61 and 62, which have almost the same characteristics as Pch and NchFETs 31 and 32, and Pc for comparison.
A first comparator 81 for comparing the threshold voltage of the hFET 61 and the output voltage of the first differential amplifier 21 and outputting the difference, for comparison
A second comparison unit 82, which compares the threshold voltage of the NchFET 62 with the output voltage of the second differential amplification unit 22 and outputs the difference,
A first low-pass filter 91 that receives the output of the comparator 81 and outputs the average value thereof, and a second low-pass filter 92 that receives the output of the second comparator 82 and outputs the average value thereof.

Input signal V ₁₁ from the input signal terminal 11 is applied to the inverting input terminal of the first and second differential amplifier 21 and 22 (+ terminal), also the input signal V ₁₂ from the input signal terminal 12 , The non-inverting input terminals of the first and second differential amplifiers 21 and 22 (-
Terminal). When V ₁₁ > V ₁₂ , the output voltages V ₂₁ and V ₂₂ of the first and second differential amplifiers ₂₁ and ₂₂ rise and
The PchFET 31 is turned off and the NchFET 32 is turned on to drive the load via the output signal terminal 13. Also,
When V ₁₁ <V ₁₂ , the first and second differential amplifiers 21 and 22
The output voltages V ₂₁ and V ₂₂ of the Nch FET 32 drop to turn off the NchFET 32, and turn on the PchFET 31 to drive the load through the output signal terminal 13 and alternately load according to the input signals V ₁₁ and V _12. To drive.

Next, the operation of setting the output voltage of the differential amplifier section near the threshold voltage of the Pch and Nch FETs will be described.

In general, the current I _D of a MOS transistor is represented by I _D = 1/2 μC _ox (W / L) (V _GS −V _TH ) ² . Here, μ is mobility, _Cox is gate capacitance per unit area, W is channel width, L is channel length, V _GS
Is the gate-source voltage, and V _TH is the threshold voltage.
Therefore, if the aspect ratio (W / L) of the MOS transistor is made sufficiently large and the current I _D is made sufficiently small by connecting a resistor in series, V _GS ≈V _TH can be obtained.

Now, referring to FIG. 1, Pch and Nch FETs 61 and 62 for comparison are used.
Connect the drain electrode and the gate electrode of the
Threshold voltages V ₆₁ and V ₆₂ are generated by connecting 1, 72 to each other and keeping the current sufficiently small. Therefore, the first and second comparators 81 and 82 are used to compare Pch and NchF.
The threshold voltages V ₆₁ and V ₆₂ of the ETs ₆₁ and ₆₂ are compared with the output voltages V ₂₁ and V _{22 of} the first and second differential amplifiers ₂₁ and _22, and the difference is output. When the power amplifier is operating, the output voltages V ₂₁ and V ₂₂ fluctuate according to the signals, so the first comparators 81 and 82
The output level of fluctuates. For this reason, a low-pass filter
Averaged by ₉₁ , ₉₂ and output the average value as feedback voltages V ₉₁ , V ₉₂ . The feedback voltages V ₉₁ and V ₉₂ are supplied to the first and second differential amplifiers 21 and 22, respectively. In this case, if the threshold voltages V ₆₁ and V ₆₂ are higher than the output voltages V ₂₁ and V _{22, the} feedback voltages V ₉₁ and V ₉₂ rise, and the threshold voltages V ₆₁ and V ₆₂ are the output voltages V _21. feedback voltage V _91, V ₉₂ becomes lower than V ₂₂ is lowered.

The first and second differential amplifiers 21 and 22 include differential pair transistors 211 to 214, 221-224, and a current source transistor 2.
The feedback voltages V ₉₁ and V ₉₂ are applied to the gate electrodes of the current source transistors 215 and 225, respectively. Now, when the threshold voltage V ₆₁ becomes higher than the output voltage V ₂₁ and the feedback voltage V ₉₁ drops, since the current source transistor 215 of the first differential amplifier section 21 is an NchFET, the differential pair transistors 211 to 214. Operates so as to decrease the output current V ₂₁ and raises the output voltage V ₂₁ so that the threshold voltage V ₆₁ and the output voltage V ₂₁ become substantially equal in the equilibrium state. When the threshold voltage V ₆₁ becomes lower than the output voltage V ₂₁ and the feedback voltage V ₉₁ rises, the reverse operation is performed, and the threshold voltage V
₆₁ and the output voltage V ₂₁ become almost equal. Similarly, for the second differential amplifier 22, the threshold voltage is
V ₆₂ and output voltage V ₂₂ become almost equal.

〔The invention's effect〕

As described above, the present invention provides a comparison Pch and Nch FE having almost the same characteristics as the Pch and Nch FETs of the output amplifier.
By comparing the threshold voltage of T with the output voltages of the first and second differential amplifiers, respectively, and feeding back the average values of the differences to the first and second differential amplifiers, respectively. 1
And the output voltage of the second differential amplifier is Pch of the output amplifier.
Since it can be set to be almost equal to the threshold voltage of NchFET, the through current can always be kept below a certain value even if the ambient temperature changes or the bias voltage changes, and high efficiency and low power consumption are achieved. It is possible to perform stable power amplification.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a conventional power amplifier. 11,12 …… Input signal terminal, 13 …… Output signal terminal, 21,22,5
1,52 …… Differential amplifier, 31,61 …… PchFET, 32,62 …… NchF
ET, 41 …… Output amplifier, 71,72 …… Resistance, 81,82 …… Comparison, 91,92 …… Low pass filter, 211〜214,221〜224…
… Differential pair transistors, 215,225 …… Current source transistors.

Claims (1)

(57) [Claims] 1. A first and a second differential amplifier having common input signal terminals, and output voltages of the first and the second differential amplifier to gate electrodes of P-channel and N-channel FETs. In a power amplifier including an output amplifying unit that applies a push-pull operation in a grounded source amplification format, a comparison P-channel and N-channel FET having substantially the same characteristics as the P-channel and N-channel FETs,
A first comparison unit that compares the threshold voltage of the comparison P-channel FET with the output voltage of the first differential amplification unit and outputs the difference, and the threshold value of the comparison N-channel FET. A second comparing section for comparing the voltage and the output voltage of the second differential amplifying section and outputting the difference, and a first filter for receiving the output of the first comparing section and outputting its average value. And a second filter that receives the output of the second comparison unit and outputs an average value thereof, and returns the output of the first filter to the first differential amplification unit to output the first differential amplifier. And controlling the output voltage of the second differential amplifier by feeding back the output of the second filter to the second differential amplifier. And a power amplifier.