JP2556904B2 - High-speed adder / subtractor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-speed addition / subtraction arithmetic device for performing addition / subtraction of input data of a plurality of bits at high speed.

[Prior Art] FIG. 2 is a block diagram showing a configuration of a conventional addition / subtraction arithmetic device. In the figure, (1) is an adder, (2) is input data for inputting data (A), (3) is input data for inputting data (B), and (4) is a function designation signal for designating an arithmetic function. , (5) are input data (A), (B)
(6) is a function determination circuit that determines what is to be performed as an actual operation based on the magnitude relation of the input data and the designation of the code and the function. (7a), (7b)
Is an input data selection circuit for selecting input data (A) and (B) to be added to the adder (1). (8) is an input inverting circuit that inverts input data, and (9) is output data from the adder (1).

The conventional adder / subtractor computing device is configured as described above, and the input data (7) A, the input data (8) B, the code signals (5) of the input data (A) and (B), and the computation function designating signal (4). Therefore, in the function determination circuit (6), the arithmetic unit
Operation (A + B) or operation (AB) or operation (B
-A) to determine which operation is to be performed. Input data (A) and (B) are selected by the input data selection circuits (7a) and (7b) from the result of the function determination circuit (6) to be input to the adder (1).

Next, when the arithmetic unit subtracts the arithmetic operation (AB) or the arithmetic operation (BA), the input inverting circuit (8) inverts the input data (A) and (B) to adder ( This is the input data to 1). Further, in the case of subtraction, the carry input of the adder (1) is set to "1". Output data (9) Y is obtained by performing an arithmetic operation from such data in the adder (1).

[Problems to be Solved by the Invention] In the conventional adder / subtractor computing device as described above, the adder / subtractor must perform the function determination based on the magnitude relation of the input data, the sign, etc. When the function determination circuit is used, there is a problem that it takes time if the number of bits of the input data is large and the operation cannot be performed at high speed.

The present invention has been made to solve such a problem, and an object of the present invention is to obtain a high-speed addition / subtraction arithmetic device that performs addition / subtraction without waiting for the magnitude relation of input data and the determination result of the arithmetic function based on the sign or the like. And

[Means for Solving the Problem] A high-speed addition / subtraction arithmetic device according to the present invention includes an addition / subtraction designating circuit for designating addition / subtraction based on sign and function designation, and a plurality of bits when a subtraction designation is output from the addition / subtraction designating circuit. An input inversion circuit that inverts the configured second input data, the first input data configured of a plurality of bits, and the output of the input inversion circuit are added, and a subtraction designation is output from the addition / subtraction designation circuit. Then, an adder for subtracting the output of the input inverting circuit from the first input data, a subtracter for subtracting the first input data from the second input data, the sign, the function designation, And a function judging circuit for judging an arithmetic function based on the magnitude relation between the first and second input data, and the adder or the subtracter based on the judgment result of the function judging circuit. And an output data selection circuit for selecting any one of the outputs of the above.

[Operation] In the present invention, the arithmetic function determination determined by the magnitude relation of the input data and the sign is separately determined by the function determination circuit and the addition / subtraction designation circuit, so that the addition / subtraction is performed without waiting for the arithmetic function determination result. .

[Embodiment] FIG. 1 is a block diagram showing the structure of a high-speed addition / subtraction arithmetic unit according to an embodiment of the present invention. In the figure, (1)
(9) is the same as the conventional one. (10) is a subtracter that subtracts from the input data (A) and (B), and (11) is an addition / subtraction designation circuit, which is applied to the code and function designation line (4) applied to the code line (5). Specify addition / subtraction from the function specification only. Reference numeral (12) is an output data selection circuit, which adds (1) or subtracts (1) depending on the output of the function determination circuit (6).
Select one of the 0) output data.

In the high-speed addition / subtraction arithmetic device configured as described above, whether the arithmetic operation (A + B) or the arithmetic operation (AB) is performed based on the sign of the input data (A) and (B) and the arithmetic function specification is performed. Specify in 11). Calculation (AB)
If so, the input data (B) is inverted and used as the input data of the adder (1). The subtractor (10) calculates (BA)
I do.

Next, in parallel with this, the function determining circuit determines whether to perform the operation (A + B) or the operation (AB) or the operation (BA) from the input data (A), (B) and the sign and the operation function designation. The judgment is made in (6). The output data selection circuit (12) selects either the operation result of the adder (1) or the subtractor (10) according to the result of the determination, and outputs the output data (9) Y.

[Effect of the Invention] As described above, according to the present invention, the addition / subtraction designating circuit for designating addition / subtraction based on the sign and the function designation, and the second bit constituted by a plurality of bits when the subtraction designation is output from the addition / subtraction designating circuit An input inverting circuit that inverts the input data of the first input data, the first input data composed of a plurality of bits, and the output of the input inverting circuit are added, and the subtraction designation is output from the addition / subtraction designation circuit. Adder for subtracting the output of the input inverting circuit from one input data, a subtracter for subtracting the first input data from the second input data, the sign, the function designation, and the first, And a function determination circuit that determines an arithmetic function based on the magnitude relationship between the second input data and either the output of the adder or the subtracter based on the determination result of the function determination circuit. Equipped with an output data selection circuit for selection, the arithmetic function judgment determined by the magnitude relation of input data, sign, etc. is performed separately by the addition / subtraction designation circuit and the function judgment circuit, and addition / subtraction can be performed without waiting for the function judgment result by the function judgment circuit. Therefore, there is an effect that the addition / subtraction operation can be performed at high speed. Further, according to the present invention, the function determination and the addition and the subtraction are performed in parallel and simultaneously, so that the control signal to be output to the output data selection circuit is generated before the result of the addition and the subtraction is output. Therefore, there is an effect that output data can be externally obtained as a calculation result at the same time as the outputs of the adder and the subtractor. Further, according to the present invention, the function determination is performed at the same time as the addition and the subtraction by the input data and the function specification, so that the function determination can be performed faster than when the function determination is performed from the output result of the addition and the subtraction. There is an effect that arithmetic processing can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration block diagram of a high-speed addition / subtraction arithmetic device according to an embodiment of the present invention, and FIG. 2 is a configuration block diagram of a conventional addition / subtraction arithmetic device. In the figure, (1) ... adder, (6) ... function determination circuit, (8) ... input inverting circuit, (10) ... subtractor, (1
1) ... Addition / subtraction designation circuit, (12) ... Output data selection circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. An addition / subtraction designating circuit for designating addition / subtraction based on sign and function designation, and an input inverting circuit for inverting second input data composed of a plurality of bits when a subtraction designation is output from the addition / subtraction designating circuit. And adding the first input data composed of a plurality of bits and the output of the input inverting circuit, and when the addition / subtraction designating circuit outputs the subtraction designation, the input inverting circuit is constructed from the first input data. And a subtracter that subtracts the first input data from the second input data, the sign, the function designation, and the magnitude relationship between the first and second input data. A function judgment circuit for judging the arithmetic function based on the above, and an output data selection circuit for selecting either the output of the adder or the subtracter based on the judgment result of the function judgment circuit. Fast subtraction arithmetic unit, characterized in that was e.