JP2558002B2 - Method of manufacturing multi-layer stack capacitor and multi-layer stack capacitor manufactured by this method - Google Patents

Description

The present invention relates to a capacitor of a semiconductor memory device, and more particularly to a method of manufacturing a multilayer stack capacitor capable of increasing the capacitance of the capacitor in DRAM. And a multilayer stack capacitor manufactured by this method.

(Prior Art) Conventionally, a DRAM, which is a memory element for recording 1-bit data, is composed of one MOS transistor and one capacitor.

Since the number of the above devices integrated per unit area increases as the integration becomes higher, the area for forming the capacitor decreases, and the capacitance of the capacitor necessary for operating the DRAM cell can be secured. It gets harder.

A DRAM capacitor is formed by inserting a dielectric insulating film between a storage electrode and a plate electrode. For example, a planar capacitor, a stacked capacitor, and a trench capacitor are known.

(Problems to be Solved by the Invention) However, in the planar capacitor, when the size of the cell is smaller than 20 μm ² , 20 to 20
Since a capacitor having a capacitance of 30fF cannot be formed, there is a problem that it cannot be applied to a DRAM having a DRAM integration degree of 4M or more.

In addition, in the stacked capacitor, since the concave and convex portions are formed to increase the effective substrate area on the semiconductor substrate in the limited area, the capacitor is manufactured by sequentially laminating the capacitor. Although it can be applied to a DRAM having a DRAM integration density, it cannot be applied to an ultra-high integration memory device having a DRAM integration density of 64M or more because the thickness of the insulating film cannot be made thinner than 50 to 100Å. There was a problem that I could not.

In addition, since trench capacitors are manufactured by forming grooves in order to increase the effective substrate area on a limited area of the semiconductor substrate, they can be manufactured only when the cell size is 5 μm ² or more. In addition, since the manufacturing process is complicated, there is a problem in mass-producing ultra-high integrated memory devices.

Therefore, although the methods for manufacturing the planar capacitor, the stacked capacitor, and the trench capacitor are combined, hard efforts are made to maximize the capacitance of the capacitor on the semiconductor substrate in the limited area. There is a problem in that the manufacturing process cannot be simplified and the ultra-high integrated memory device is mass-produced.

Therefore, the present invention solves the above-mentioned problems of the prior art, and an object thereof is to simplify the manufacturing process in the method of manufacturing a DRAM capacitor.
Further, it is to provide a method for manufacturing a multilayer stack capacitor in which the capacitance of the capacitor is maximized on the semiconductor substrate in a limited area.

Another object is to provide a multilayer stack capacitor obtained by using the above manufacturing method.

[Structure of the Invention] (Means for Solving the Problems) In the method for manufacturing a multilayer stack capacitor according to the present invention for solving the above problems, a DRAM cell including one MOS transistor and one capacitor is provided. After forming a field oxide film on a predetermined portion of one semiconductor substrate,
Forming each region of the source, drain, and gate of the MOS transistor, and then forming one insulating film on them, and etching the insulating film formed in the source region to form a contact portion. A step of sequentially forming a first storage electrode, a first insulating film, a first plate electrode, and a second insulating film on the contact portion, and forming one pad poly on the second insulating film, The step of exposing the first plate electrode to a predetermined portion in accordance with the photo-etching technique and the progress of oxidation,
After depositing the obtained oxide film by a chemical vapor deposition method, a step of leaving only one spacer formed by etching the oxide film, and a second storage of one by the same step as the step of the first storage electrode Forming an electrode and depositing the second storage electrode so that the second storage electrode is connected to the first storage electrode; and a third insulating film and a second storage layer on the semiconductor substrate. And a step of depositing a plate electrode.

Further, the multilayer stack capacitor of the present invention includes a first plate electrode, a field oxide film, and a channel region extending from the upper part of the gate to the upper part of the gate of the channel region. A first capacitor having a first storage electrode and a first insulating film sandwiched between the first storage electrode and the first plate electrode; and a pad poly,
A second capacitor formed on the first capacitor, having the first plate electrode and one second insulating film sandwiched between the first plate electrode and the pad poly;
One second storage electrode, one second plate electrode, and one third insulating film sandwiched between the second plate electrode and the second storage electrode, and on the second capacitor. And a third capacitor formed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

1 (a) to 1 (e) show the sequence of steps in a method of manufacturing a multilayer stack capacitor according to an embodiment of the present invention.

FIG. 1A shows a MOS transistor formed on a semiconductor substrate 1 by a general DRAM cell manufacturing process and the MOS transistor.
Shown is a contact site 12 for depositing a stacked storage electrode after forming an insulator on top of a transistor.

In this step, a field oxide film 2 is formed at a predetermined portion on the p-type semiconductor substrate 1 to form a MOS transistor, adjacent to the field oxide film 2, and n
Source regions 3 and 3'which are ion-implanted in a shape and drain regions 4 which are ion-implanted in an n-type are formed at a predetermined distance from the source regions 3 and 3 '.

Further, a gate oxide film 6 is formed on the field oxide film 2 and on the channel region 5 between the upper source regions 3, 3 ′ and the drain region 4 to form the gate electrode 7,
8, 9 and 10 are formed.

Here, the semiconductor substrate as the first conductor is p-type, while the source and drain regions as the second conductor are n-type.
Although ions are implanted so as to form the n-type semiconductor substrate, it is also possible to form the n-type semiconductor substrate and the p-type source and drain regions.

After such a process, the insulating film 11 is grown on the substrate and etched by a known photolithography method to form the contact portion 12 on the source region 3. Then, the first storage electrode 13 is deposited above the contact portion 12 and above the gate electrodes 9 and 10 formed above the field oxide film 2 and the channel region 5. In this case, the first storage electrode 13 is a low pressure chemical vapor deposition method (hereinafter referred to as LPCVD) mainly using hydrogen silicate gas (SiH ₄ ).
It is referred to as), and is formed by a certain kind of polycrystal vapor deposition obtained by vapor deposition.

After doping the first storage electrode 13, a first insulating film 14 is deposited over the entire area of the semiconductor substrate 1. Here, the first insulating film 14 may be an oxide film or a nitride film, or a combination of an oxide film and a nitride film.

Next, the first plate electrode 15 is formed by depositing and doping impurities over the entire region of the semiconductor substrate 1 by the same method as that for forming the first insulating film 14,
A second insulating film 16 and a pad poly 17 are sequentially formed on the layer 15. Then, the pad poly 17 is doped again with impurities and connected to the second storage electrode 18 which will be formed in the next step and electrically short-circuited.

FIG. 1B shows a photolithographically etched portion for forming the first plate electrode 15 when the first insulating film 14 is used as an etching stopper film.

At the time of etching, the pad poly 17, the second insulating film 16 and the first plate electrode 15 have good selectivity depending on the material to be doped for the purpose of obtaining accuracy and productivity in the etching process. It is continuously etched by using the process. Here, the etching stop film, that is, the first insulating film 14 may be sufficiently thick for stable etching.

FIG. 1C shows the first storage electrode 13 and the second storage electrode 18.
7 shows a process for forming spacers 20 before they are connected to each other.

In the above process, the oxidation process is performed after etching the first plate electrode 15. Oxide film 500 on pad poly 17
When grown to a thickness of 4,000 Å, the oxide film on the first storage electrode 13 does not grow due to the first insulating film 14 acting as an antioxidant film.

After the oxide film is deposited to a thickness of 700 to 900Å by LPCVD, the oxide film of 500 to 4000Å on the oxide film deposited by pad poly 17 and LPCVD is etched by the reactive ion etching method (RIE). The first storage electrode 1
3 is exposed.

Therefore, the oxide film on the pad poly 17 is completely removed and the spacer 20 formed of the oxide film as shown in FIG.
Only remains. The spacer 20 forms an insulating film on the side surfaces of the first plate electrode 15, the second insulating film 16, and the pad poly 17.
The second storage electrode 18 formed in the next step is prevented from being electrically short-circuited.

FIG. 1D shows a process in which the first storage electrode 13 and the second storage electrode 18 are electrically connected to each other.

The second storage electrode 18 is deposited by a chemical vapor deposition process similar to the process of forming the first storage electrode 13. In this case, the second storage electrode 18
When the pattern is formed to overlap the first storage electrode 13, these storage electrodes 13 and 18 are completely connected to each other and completely separated from the first plate electrode 15. Therefore, the first storage electrode 13 and the second storage electrode 18 are electrically connected to each other.

FIG. 1E shows the third insulating film 21 and the second plate electrode 22.
The process of forming the is shown.

After depositing the third insulating film 21 over the entire surface of the semiconductor substrate 1, the second plate electrode 22 is deposited and doped in the same manner as the formation of the first plate electrode 15.

After the second plate electrode 22 is deposited and doped,
The step of connecting the first plate electrode 15 and the second plate electrode 22 to the conductors of the peripheral circuit is executed to complete the memory cell. At this time, in the etching process, the second plate electrode 22 is used as a mask and the third insulating film 21 is used as an etching stop film.

After the above steps are performed, if there is no need to make a capacitor, after performing the steps shown in FIG. 1 (e),
A passivation layer may be formed over the entire surface of the semiconductor substrate 1. On the other hand, in order to obtain a larger capacitance of the capacitor by forming the third storage electrode and the fourth storage electrode, the steps from the vapor deposition of the first storage electrode 13 to the formation of the oxide film spacer 20, or the second storage electrode. Either of the steps up to the formation of the electrode 18 may be repeated as many times as desired. That is, as in the method described above, after forming the fourth insulating film and the second pad poly on the second plate electrode 22, the spacer 20
An etching step and an oxidization step are performed to form a third storage electrode is deposited above the second storage electrode 18, resulting in a larger capacitor capacitance.

Observing a DRAM cell formed by such a process, one MOS transistor has a drain, a source, and a gate, and a memory cell connected to the transistor, that is, a capacitor is a first storage electrode 13 and a second storage electrode. Electrode 1
8, the first plate electrode 15, and the second plate electrode 22,
The first insulating film 14, the second insulating film 16, sandwiched between these electrodes,
And a third insulating film 21.

Therefore, the insulating film group formed between the storage electrode group and the plate electrode group has a three-layer structure, and the area of the insulating film capacitor can be maximized.

FIG. 2 shows the structure of the multilayer stack capacitor formed by the process of the manufacturing method according to the present invention.

Here, the field oxide film 2, the drain region 4, the source region 3, which separates the semiconductor element from other elements,
The structure of the MOS transistor having 3 ', the gate regions 7, 8, 9 and 10 is the same as that of a general DRAM cell. The capacitor connected to the transistor has the following structure. That is, the first capacitor is formed above the regions on the source regions 3, 3 ′ for the contact sites 12 and above the gates 7, 8, 9, and 10 of the field oxide 2 and the channel region 5.

The first capacitor has a first storage electrode 13, a first plate electrode 15, and a first insulating film 14 sandwiched between the first storage electrode 13 and the first plate electrode 15. The second capacitor formed on the first capacitor has a first plate electrode 15, a pad poly 17, and a second insulating film 16 sandwiched between the first plate electrode 15 and the pad poly 17. The third capacitor formed on the second capacitor has a second storage electrode 18, a second plate electrode 22, and a third insulating film 21 sandwiched between the second storage electrode 18 and the second plate electrode 22. Have.

Since the first storage electrode 13 and the second storage electrode 18 are electrically connected to each other, and the second storage electrode 18 and the pad poly 17 are electrically connected to each other, the first storage electrode 13 and the second plate electrode are eventually connected. A first capacitor formed between 22 and
The second capacitor and the third capacitor are formed as one combined capacitor, and the total capacitance is significantly increased.

FIG. 3 is a simplified view of the first storage electrode 13, the second storage electrode 18, the first plate electrode 15, and the second plate electrode 22 in the capacitor circuit shown in FIG. In this figure, the same reference numerals are used for the same electrodes as those shown in FIGS. 1 (a) to 1 (e) and FIG.

The first storage electrode 13 and the second storage electrode 18 are connected to each other at a node X on the circuit, while the first plate electrode 15
And the second plate electrode 22 are connected to each other at the node Y on the circuit. Then, the shaded portions a, b, and c between the respective electrodes are regions that actually contribute to the capacitance of the capacitor.

Therefore, by alternately stacking the storage electrodes and the plate electrodes alternately, the capacitance of the capacitor can be increased infinitely.

As described above, in the method for manufacturing a multilayer stack capacitor according to the present invention, cells of a single stack capacitor having a three-layer structure are stacked three-dimensionally one after another using the conventional method for manufacturing a stack capacitor. It is possible not only to eliminate the difficulty in manufacturing, but also to theoretically manufacture a capacitor having an infinitely large capacitance.

In addition, the contact portion 12 of the source regions 3 and 3'on which the first storage electrode 13 is formed can be formed on a relatively flat surface of the semiconductor substrate 1.
Larger capacitance can be achieved by forming an insulating film between the storage electrode and the plate electrode after repeating the step of sequentially stacking and forming the second storage electrode 18, the first plate electrode 15, and the second plate electrode 22. A capacitor having the same can be obtained. In this case, the step of using the first insulating film 14 as the etching stop film to form the first storage electrode 13 and the step of forming the spacer are such that the first storage electrode 13 and the second storage electrode 18 are laminated. This is done to prevent an electrical short circuit phenomenon with other layers.

Furthermore, since the insulating film is formed between the storage electrode and the plate electrode by using the pad poly, the capacitance of the capacitor can be improved significantly.

Therefore, according to one embodiment of the present invention, even if the area of the plane of the capacitor in the DRAM is significantly reduced by the high integration, the storage electrode and the plate electrode are sequentially stacked without forming the insulating film as a thin film. As a result, next-generation ultra-high integration DRAM can be solved
Realization of cells becomes possible.

The present invention is not limited to the above-described embodiments, but can be implemented in an appropriate mode by appropriate design changes.

[Effects of the Invention] As described above, according to the method for manufacturing a multilayer stack capacitor of the present invention, field oxidation is performed on a predetermined portion of a semiconductor substrate provided with a DRAM cell including one MOS transistor and one capacitor. After forming the film, forming the source, drain, and gate regions of the MOS transistor, and then forming one insulating film on them, and etching the insulating film formed in the source region. To form a contact portion, and sequentially form a first storage electrode, a first insulating film, a first plate electrode, and a second insulating film on the contact portion, and form a contact layer on the second insulating film. A step of forming pad poly, a step of exposing the first plate electrode to a predetermined portion by a photo-etching technique, an oxidation process, and an oxide film obtained is deposited by a chemical vapor deposition method. Eat The step of leaving only one spacer formed and the step of forming the second storage electrode by the same step as the step of forming the first storage electrode, and the second storage electrode is connected to the first storage electrode. The method may further include the step of depositing the second storage electrode, and the step of depositing one third insulating film and one second plate electrode on the semiconductor substrate. First plate electrode,
A first storage electrode extending from the upper part of the gate of the field oxide film to the upper part of the gate of the channel region through the contact region; and the first storage electrode and the first plate electrode A first capacitor having a first insulating film sandwiched between and, a pad poly, the first plate electrode, and a second insulation sandwiched between the first plate electrode and the pad poly. A second capacitor having a film and formed on the first capacitor, one second storage electrode, one second plate electrode, and between the second plate electrode and the second storage electrode. The semiconductor substrate having one third insulating film sandwiched therebetween and the third capacitor formed on the second capacitor can simplify the manufacturing process and has a limited area. The capacitance of the capacitor is the highest It can be obtained Kunar capacitor.

[Brief description of drawings]

1 (a) to 1 (e) are process diagrams of a method for manufacturing a multilayer stack capacitor according to an embodiment of the present invention, and FIG. 2 is a diagram showing the manufacturing method shown in FIGS. 1 (a) to 1 (e). FIG. 3 is a cross-sectional view of the formed multilayer stack capacitor, and FIG. 3 is a schematic circuit diagram for explaining the circuit of the capacitor shown in FIG. 1 ... Semiconductor substrate, 2 ... Field oxide film 3, 3 '... Source region, 4 ... Drain region 5 ... Channel region, 6 ... Gate oxide film 7, 8, 9, and 10 ... Gate electrode 11 ... Insulating film, 12 ... Contact area 13 ... First storage electrode, 14 ... First insulating film 15 ... First plate electrode, 16 ... Second insulating film 17 ... Pad poly, 18 ... Two storage electrodes 20 …… Spacer, 21 …… Third insulating film 22 …… Second plate electrode

Continued Front Page (72) Inventor Shin Yun-Hyun, Seoul Seoul Yangchun-gu, Shin-yun 2-Dong, Mokdong Apartment 1404-1304 (72) Inventor Choi Won-Tech, South Korea Seoul Kang-dong, Dun-cheon 2-Dong, Hyundai 1 Cha Apartment, 1034 (56) References JP 64-47067 (JP, A) JP 1-154552 (JP, A)

Claims (12)

(57) [Claims] 1. A D including a MOS transistor and a capacitor.
The M
First, forming the source (3, 3 ') and drain (4) and gate (7, 8, 9, 10) regions of the OS transistor, and forming an insulating film (11) on the substrate. A step of etching the insulating film (11) formed in the source regions (3, 3 ') to form a contact part (12), and sequentially forming a first storage electrode on the contact part (12). (13), first insulating film (1
4), first plate electrode (15), and second insulating film (16)
Forming a pad poly (17) on the second insulating film (16).
And a second step of forming the pad poly (17), the second insulating film (16) and the first plate electrode (15) at a predetermined position along the semiconductor substrate over the first insulating film (15). 14) is used as an etching stop film and removed to remove the first insulating film (1
4) exposing the third step, and the upper surface of the first insulating film (14) exposed in the third step and the pad poly (17) / second insulating film (16) / first plate electrode (15) A fourth step of depositing an oxide film on the side surfaces of the pad poly (17) and on all surfaces of the upper surface of the pad poly (17), and on the side surfaces of the pad poly (17), the second insulating film (16) and the first plate electrode (15). All oxide films except the oxide film of a predetermined width that are adjacent to each other are etched to form spacers (20) made of the oxide film of the predetermined width, and
A fifth step of exposing the first storage electrode (13) by etching the first insulating film (14) not covered with the spacer (20) among the first insulating film (14) exposed by the step And a conductive material is deposited on the upper surface of the pad poly (17), the upper and side surfaces of the spacer (20), and the upper surface of the exposed portion of the first storage electrode (13) to form the first storage electrode (13).
A second storage electrode (18) connected to the second storage electrode (18), and a sixth step of depositing a third insulating film (21) and a second plate electrode (22) on the upper surface of the second storage electrode (18). A method for manufacturing a multilayer stack capacitor, comprising: 2. In the second step, a part of the semiconductor substrate is exposed by forming the contact portion (12),
The first storage electrode (13) is formed on a part of the exposed semiconductor substrate and on the upper surface and the side surface of the first insulating film (11).
The method of claim 1 including the step of forming. 3. The second step comprises the step of storing the first position storage electrode (1).
After forming 3), including the step of removing the first storage electrode (13) and exposing the insulating film (11) at a position separated from the contact portion (12) along the surface of the semiconductor substrate. The method according to claim 2, wherein: 4. The method according to claim 1, wherein the first insulating film, the second insulating film, and the third insulating film are formed with different thicknesses from each other. 5. The method according to claim 1, wherein the contact site formed on the source region is formed on a flat surface. 6. The method as claimed in claim 1, wherein the first insulating layer formed on the first storage electrode is used as an etch stop layer. 7. The first plate electrode mask is formed so as to be shared on two cells, and the first plate electrode and the second plate electrode are connected to each other through a conductor of a peripheral circuit. The method of claim 1. 8. In a multi-layer stack capacitor comprising a DRAM cell including a MOS transistor and a capacitor, a channel region (5) is provided from above a gate (9) on a field oxide film (2) through a contact region (12). Storage electrode (13) extending to the upper part of the gate (6), a first insulating film (14) formed on a part of the upper surface of the first storage electrode (13), and the first insulating film. A first capacitor having a first plate electrode (15) formed on a part of the upper surface of (14), and the first plate electrode (15) and formed on the entire upper surface of the first plate electrode (15) A second capacitor having a formed second insulating film (16) and a pad poly (17) formed on the entire upper surface of the second insulating film (16), and on the first insulating film (14), First plate electrode (1
5) a spacer (20) formed at a predetermined location where no first electrode is formed and contacting and adjoining the side surfaces of the first plate electrode (15), the second insulating film (16) and the pad poly (17), and the first insulating film A predetermined region of the first storage electrode (13) where the film (14) is not formed, the spacer (20), and the second storage electrode (18) formed on the upper surface of the pad poly (17), A third insulating film (21) formed on the second storage electrode (18) and the semiconductor substrate, and a second plate electrode (2 formed on the entire upper surface of the third insulating film (21).
And a third capacitor having 2), and a multi-layer stack capacitor having: 9. The first plate electrode and the second plate electrode are electrically connected to each other, and similarly, the same storage electrode and the second storage electrode are electrically connected to each other. The multilayer stack capacitor described. 10. A first capacitor, a second capacitor, and a third capacitor are provided between a first plate electrode and a first storage electrode, between a first plate electrode and a pad poly, and between a second storage electrode and a second storage electrode. The multilayer stack capacitor of claim 8, wherein the multilayer stack capacitor is formed between the plate electrode and the plate electrode. 11. The multilayer stack capacitor of claim 8, wherein one spacer insulated from an external device is used to electrically connect the first storage electrode and the second storage electrode. . 12. The multilayer stack capacitor according to claim 8, wherein the capacitance of the capacitor is increased by alternately and repeatedly forming a storage electrode group and a plate electrode group.