JP2560985B2 - Recording circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording circuit in a magnetic recording device, and more particularly to a recording circuit suitable for connection with a CMOS logic circuit.

[0002]

2. Description of the Related Art Hard disk devices, floppy disk devices, magnetic tape devices and the like are used as magnetic recording devices. Further, these magnetic recording devices are provided with a recording circuit for writing information on the magnetic recording medium according to the write data signal WD. FIG. 5 is a block diagram showing the configuration of a conventional recording circuit. TTL (Transistor-Trans
A signal conversion circuit 91 for converting a write data signal WD sent at an istor logic (ESL) level into an ECL (Emitter Coupled Logic) level signal, and a T-type flip-flop provided at the output side of the signal conversion circuit 91 configured by ECL. Circuit 92, a head select circuit 93 that receives the output of the T-type flip-flop circuit 92 and the head select signal HS, and creates a signal for driving the head, and two magnetic recording heads H ₀ and H ₁ . It is configured by a head drive circuit 94 that is actually driven.

The head drive circuit 94 has a constant current source 95 for generating an accurate constant current I, and differential transistors Q ₉₁ and Q for flowing the constant current I to the head H ₀ or the head H ₁ , respectively. ₉₂ or differential transistors Q ₉₃ and Q ₉₄ . Each of the four output lines from the head select circuit 93 is connected to the base of each of the transistors Q _{91 to} Q ₉₄ .

In this recording circuit, after the write data signal WD which is an input signal is converted to an ECL level by a signal conversion circuit 91, an RZ (Return to Zero) signal-NRZ (Non Return) is converted by a T-type flip-flop circuit 92.
signal conversion is performed. Further, the head select circuit 93 performs a level shift to generate a signal for actually driving the head.

FIG. 6 is a circuit diagram specifically showing a configuration example of the recording circuit described above. Since the configurations of the signal conversion circuit 91 for converting from TTL to ECL level and the T-type flip-flop circuit 92 by ECL are well known, description of specific configurations of these circuits will be omitted.

In the head select circuit 93, a pair of outputs from the T-type flip-flop circuit 92 is received by the differential transistors Q ₈₁ and Q ₈₂ , and collector currents of these transistors Q ₈₁ and Q ₈₂ are passed through a current mirror. The collectors of the transistors Q ₈₃ and Q ₈₄ and the transistor Q, respectively.
It is output to the collector of _85, Q _86. Further, the transistor Q controlled by the head select signal HS
₈₇ and the head select signal HS via the inverter 96
And a transistor Q ₈₈ controlled by. These transistors Q ₈₇ , Q ₈₈ selectively process the collector voltage of the transistors Q ₈₃ , Q ₈₄ or the collector voltage of the transistors Q ₈₅ , Q ₈₆ to a voltage close to the ground potential by the head select signal HS. It is a thing.

[0007] With this arrangement, when the head select signal HS is at the high level, one of the collector voltage of the transistor Q ₈₃ or Q ₈₄ becomes high level in response to the write data WD, a head drive circuit Either the transistor Q ₉₁ or Q ₉₂ of 94 operates and writing is performed by the head H ₀ . At this time,
Both the transistors Q ₉₃ and Q ₉₄ are in the non-operating state, and writing by the head H ₁ is not performed.

On the contrary, the head select signal HS is low level.
Transistor Q if ₉₃, Q₉₄One of
Operates, head H₁Is written. here
Then, the number of magnetic heads was set to two, but four heads
Some are equipped with 8 ruins.

In the conventional recording circuit described here, the head drive circuit 94 is constructed by using bipolar transistors, but it is also possible to construct the head drive circuit by a CMOS inverter circuit. Japanese Patent Laid-Open No. 2-2
23002 discloses a head drive circuit using a CMOS inverter circuit. FIG. 7 shows a CMOS
The head drive circuit by a structure is shown.

This circuit comprises a constant current source 97 of constant current I,
First CMOS composed of MOS transistors Q ₉₅ and Q ₉₆
An inverter and a second CMOS inverter composed of MOS transistors Q ₉₇ and Q ₉₈ are provided, and a head H ₀ is inserted between the output terminals of both inverters.
Then, the CMOS inverter is controlled by the logic circuit 99. Recording is performed according to the direction of the current flowing through the head H ₀ . When performing the first recording, the transistors Q ₉₅ and Q ₉₈ are turned on, a constant current source 97 → transistor Q ₉₅ → head H ₀ → transistor Q ₉₈ → current flows to the ground point, and the second recording In the case of, the transistors Q ₉₆ and ₉₇ are turned on and the constant current source 9
7 → Transistor Q ₉₆ → Head H ₀ → Transistor Q ₉₇
→ Apply current to the ground point. The directions of the currents flowing through the head H ₀ are opposite between the first recording and the second recording.

[0011]

Since the conventional recording circuit as shown in FIG. 6 has a complicated circuit configuration in terms of function and uses an ECL circuit and requires a bias current in many places, It is expensive and consumes a large amount of power. Further, in the recording circuit using the CMOS inverter as shown in FIG. 4, it is necessary to flow a current of several to several tens of mA, which must be supplied to the head at the time of writing data, to the MOS transistor having a small mutual conductance g _m . Therefore, there is a problem that the MOS transistor needs to be formed in a large size, which is expensive.

An object of the present invention is to provide a recording circuit which has a small number of elements, a small current consumption, and a low cost.

[0013]

According to the recording circuit of the present invention, a write data signal to be inputted in a recording circuit of a magnetic recording device having a differential transistor pair which is connected to a magnetic head for recording and drives the magnetic head with current. To a NRZ signal, and a CMOS-type T-type flip-flop circuit, and a base voltage control circuit which is provided on the output side of the CMOS-type T-type flip-flop circuit and outputs a predetermined voltage alternatively. The respective outputs of the base voltage control circuit are connected to the bases of the respective transistors forming the dynamic transistor pair.

[0014]

The present invention uses a CMOS type T-type flip-flop circuit for converting a write data signal into an NRZ signal, and further devises an interface between the T-type flip-flop circuit and the head drive circuit. is there.
That is, conventionally, a TTL level signal is once converted into an ECL level signal and input to the head drive circuit via an ECL type flip-flop and a level shifter.
In the recording circuit of the present invention, the head drive circuit can be controlled by a simple circuit that mainly uses MOS transistors. As a drive circuit for directly driving the recording head, a drive circuit composed of a pair of differential transistors is used. The differential transistor is typically composed of a bipolar transistor having a large driving capability.

By configuring the recording circuit as described above, the ECL circuit and the level shifter are unnecessary, the number of required elements is reduced, the power consumption and the chip area are reduced, and the low voltage operation is possible, and the cost is also reduced. descend.

As the base voltage control circuit, for example,
A circuit for selectively switching the bias voltage with a MOS switch, a circuit for selectively varying the voltage with a MOS switch, or a circuit for generating a voltage by selectively flowing a constant current through a load resistor with a MOS switch, etc. Can be used.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings.

<< First Embodiment >> FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a recording circuit of an example. This record
The circuit consists of two recording heads H₀, H₁Writing data using
It is used when the
T-type flip flow that converts the data signal WD to the NRZ signal
Circuit 1, head select signal HS and T-type flip-flop
Decoder circuit to which a pair of outputs of the drop circuit 1 is input
2. Base voltage control provided on the output side of the decoder circuit 2
Control circuit 3 and base voltage control circuit 3
Recording head H ₀, H₁And the head drive circuit 4 that drives
Therefore, it is configured. Where the head select signal
HS is the recording head H₀And H₁Belief in making choices with
No.

The T-type flip-flop circuit 1 is a CMOS
It has a known configuration using. The decode circuit 2 is a CMOS logic circuit, and is composed of an inverter 12 to which the head select signal HS is input and four NAND gates 13 _{1 to} 13 ₄ ,
A pair of outputs of the T-type flip-flop circuit 1

[0020]

[Outer 1] Based on Q and the head select signal HS, only one of the NAND gates 13 _{1 to} 13 ₄ outputs "0" at the same time.

The head drive circuit 4 has a known structure having a differential transistor pair using bipolar transistors, and has four transistors Q _{1 to} Q ₄ and a constant current I.
The constant current source 11 of FIG. Each recording head H ₀ , H ₁
Is of a type having a midpoint in the winding, and a voltage _Vcc is applied to these midpoints. The collectors of the transistors Q ₁ and Q ₂ are connected to both ends of the winding of the recording head H ₀ . Similarly, the collectors of the transistors Q ₃ and Q ₄ are connected to both ends of the winding of the recording head H ₁ . The emitter of each transistor Q ₁ to Q ₄ are connected in common, a constant current source 11 is inserted between the ground point and the common connection point.

The base voltage control circuit 3 is composed of four switches S _{1 to} S ₄ composed of PMOS transistors and a bias power supply V _B. The switch S ₁ is gate-controlled by the output of the NAND gate 13 ₁ of the decoding circuit 2, and connects the bias power supply V _B and the gate of the transistor Q ₁ of the head drive circuit 4. Similarly, the switches S _{2 to} S ₄ are gate-controlled by the NAND gates 13 _{2 to} 13 ₄ , respectively, and connect the transistors Q _{2 to} Q ₄ and the bias power supply V _B.

Next, the operation of this recording circuit will be described.
You. The write data signal WD, which is an input signal, is a T-type free signal.
It is converted into an NRZ signal by the up-flop circuit 1 and
The head select signal HS is also used by the coder circuit 2.
Be decoded. Head H ₀If you choose the head
The select signal HS is at the low level, and as a result, the T type
Depending on the output of the flip-flop circuit 1, the NAND gate
To 13₁, 13₂Outputs a low level. So
As a result, the switch S₁, S₂One of the on states
And transistor Q₁, Q₂On one of the bases
Iias voltage V_BIs selectively applied, and the recording head H₀Drive
Be moved. At this time, switch S₃, S_FourIs off
Since it is in the state, transistor Q₃, Q_FourTo the base of
As voltage V_BIs not applied to the recording head H₁But
It is never driven. On the other hand, head select signal HS
Is high level, the recording head H₁Is selected and above
The recording head H as described above₁Is driven. At this time,
Itch S₁, S₂Are both in the off state and the recording head
H₀Is never driven.

As is clear from the above description, only _one of the switches S _{1 to} S ₄ is turned on at the same time, so that the bias voltage V _B is applied to the base of the transistors Q _{1 to} Q _4. There is only one at a time.

When this recording circuit is compared with the conventional recording circuit shown in FIG. 6, the recording circuit of the present embodiment is realized with a significantly reduced number of elements. Moreover, considering the logic circuit portion, the MOS transistor for the CMOS logic circuit can be formed in an area smaller than that of the bipolar transistor, so that the recording circuit of the present embodiment can be formed with a size smaller than it appears on the circuit diagram. it can. Also,
In the present embodiment, the T-type flip-flip circuit 1, the decoder circuit 2, and the base voltage control circuit 3 consume no current in a steady state, so that the circuit has extremely low power consumption.

<Second Embodiment> Next, a second embodiment of the present invention will be described with reference to FIG. This recording circuit suppresses the influence of variations in the on resistance of the switches S _{1 to} S ₄ in the first embodiment described above.
Only the configuration of the base voltage control circuit is different from that of the above embodiment. That is, the base voltage control circuit 3a in this embodiment, in place of the switches S ₁ to S ₄ of the first embodiment, four switching circuits 20 are provided. Since the switch circuits 20 have the same configuration, the switch circuit 20 connected to the transistor Q ₁ of the head drive circuit 4 will be described here.

The switch circuit 20 is a PMOS transistor.
Switch S₁₁, 2 by NMOS transistor
Switches S₁₂, S₁₃And the collector is the power supply V_ccConnected to
Bipolar transistor Q₁₁Composed by and
ing. Each switch S₁₁~ S ₁₃Is the N of the decoder circuit 2.
AND gate 13₁Is gated by the output of
ing. Transistor Q₁₁The gate of switch S₁₁To
Bias power supply V _B'It is connected to the. Transis
Q₁₁The emitter is a switch S₁₂Is grounded through
You. Also, switch S₁₃Is the transistor Q₁₁The gate of
It is provided to short-circuit the ground point with the ground point.

Now, the base current of the transistor Q ₁ of the head drive circuit 4 will be examined. When transistor Q ₁ is on, its base current is given by I / h _fe .
I is a constant current value of the constant current source 11. I = 30 mA, h
_{When fe} = 100, this base current becomes about 300 μA. Assuming that the on resistance of the switch S ₁ is 1 kΩ in the first embodiment (see FIG. 1), a voltage drop of 300 mV will occur across the switch S ₁ . As a result, variations in the operating voltage will occur due to variations in the on-resistance of the switch, and in order to suppress this variation, the on-resistance of the switch S ₁ will be about 1/10 (the size will be 10 times larger). Need to

In this embodiment, the size of the MOS switch is increased.
Transistor Q₁₁The darlington tiger
It is used as a transistor₃₁of
Base current, that is, MOS switch S₁₁Actually flows in
1 / h _feSo that this
As a result, switch S₁₁Even if the on-resistance of is 1kΩ,
Itch S₁₁Voltage drop across both ends is typically 3 mV
Will be Therefore, the problem of operating voltage variation is
Does not happen. The bias voltage V in this embodiment is_B'
Is the bias voltage V in the first embodiment described above._BThan
Also transistor Q₁₁Base-emitter voltage V_BEMinutes
Set it high. The switch S₁₂, S₁₃Is
Langista Q₁, Q₁₁Are turned off when
Langista Q₁, Q₁₁Forcibly ground the base of the
It is for removing the load. By this,
The operation speed is improved.

[0030] In this embodiment, when the output of NAND gate 13 ₁ is at a low level, the switch S _{1 1} is on, the switch S _12, S ₁₃ are turned off, the transistor Q ₁₁ operates,
A voltage is applied to the base of the transistor Q ₁ of the head drive circuit 4. On the other hand, when the output of the NAND gate 13 ₁ is at the high level, the switch S ₁₁ is off and the switches S ₁₂ , S
₁₃ is turned on, the transistor Q ₁₁ is cut off, and no voltage is applied to the base of the transistor Q ₁ of the head drive circuit 4.

<< Third Embodiment >> Next, a third embodiment of the present invention will be described with reference to FIG. This example is
The decoder circuit is simplified, and the decoder circuit is configured only by the inverter 12 to which the head select signal HS is input. The configurations of the T-type flip-flop circuit 1 and the head drive circuit 4 are the same as those in the above-described embodiments.

The base voltage control circuit 3b has four PMOs.
S switch S_{twenty one}, S_{twenty two}, S_{twenty four}, S_{twenty five}And two NMOSs
Itch S_{twenty three}, S₂₆And two bias power supplies V_B1, V_B2When,
8 resistors R₁₁~ R₁₈And is constituted by. Each
Itch S_{twenty one}, S_{twenty two}, S_{twenty four}, S_{twenty five}Has a power supply voltage V at one end_ccTo
Commonly connected, and the other end has a resistor R₁₁, R₁₃,
R _Fifteen, R₁₇Are connected. Resistance R₁₁And R₁₂Is connected in series
The head drive circuit 4 is connected to the middle point of the series connection.
Langista Q₁The base of is connected. Similarly,
Anti-R₁₃And R₁₄, Resistance R_FifteenWhen₁₆, Resistance R₁₇And R₁₈Is connected in series
The middle points of these are transistor Q respectively.
₂~ Q_FourConnected to the base of. Furthermore, the resistance R₁₂When
R₁₄And are connected, and between these connection points and the ground point,
Switch S_{twenty three}And bias power supply V_B1And are installed in parallel
There is. Also, the resistance R₁₆And R₁₈And are connected and these connections
Between the continuation point and the ground point, switch S₂₆And bias power supply V
_B2And are provided in parallel. Switch S_{twenty two}, S_{twenty five}Is
The gate output is controlled by the Q output of the T-type flip-flop circuit 1.
And switch S_{twenty one}, S_{twenty four}Is a T-type flip-flop circuit
One

[0033]

[External 2] The output is gated. The switch S ₂₃ is gate-controlled by the head select signal HS, and the switch S ₂₆ is gate-controlled by the head select signal HS via the inverter 12.

When the head select signal HS is at the low level, the switch S ₂₃ is off. At this time, if the Q output of the T-type flip-flop circuit 1 is high, the switch S ₂₁ is turned on and the transistor Q ₁ is turned on. The base voltage of
The voltage is higher than the bias voltage V _B1 by the resistance ratio. On the other hand, since the switch S ₂₂ is off, the bias voltage V _B1 is directly applied to the base of the transistor Q ₂ . Also, since the switch S ₂₆ is on,
The base potentials of the transistors Q ₃ and Q ₄ are almost ground potential. Therefore, the constant current I flows only in the transistor Q ₁ . Similarly, if the Q output goes low,
Ie

[0035]

[Exterior 3] When the output becomes high level, the switch S ₂₂ is turned on and the constant current I flows through the transistor Q ₂ . Similarly, when the head select signal HS is at high level,
The constant current I flows through either one of the transistors Q ₃ and Q ₄ .

In this embodiment, the base voltage control circuit 3b is configured to switch the bias voltage applied to the base of each transistor of the head drive circuit for each recording head, and the decoding circuit is simplified and the cost is further reduced. Can be made.

<< Fourth Embodiment >> Next, a fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, the decoding circuit is constructed only by the inverter 12 as in the third embodiment described above, and the configuration of the head drive circuit is slightly different from that of each of the above-described embodiments. The configuration of the T-type flip-flop circuit 1 is the same as that of each of the above-mentioned embodiments.

The head drive circuit 4a has the same structure as the head drive circuit 4 of the first to third embodiments except that the resistor R ₁ is used instead of the constant current source. Base voltage control circuit 3c, each transistor Q ₁ to Q ₄ of the head drive circuit 4a
Each have four switch circuits 30 corresponding to the further and two PMOS switches S _34, S _36, two NM
OS switches S ₃₅ , S ₃₇ and a constant current source 31 for a constant current I ′
And a resistor R ₁ .

Each switch circuit 30 is a PMOS switch.
S₃₁Two NMOS switches S₃₂,₃₃And two buys
Polar transistor Q₃₁, Q₃₂Composed by and
You. Transistor Q₃₁Is the power supply V_ccConnected to
Transistor Q₃₁Base and transistor Q₃₂
Collector, transistor Q₃₁Emitter and Transis
Q₃₂The bases of each are connected. Transis
Q₃₁The emitter of the head drive circuit 4a
Corresponding transistor (transistor Q₁~ Q_FourWhich of
Or) is connected to the base. Switch S₃₂, S
₃₃Is the transistor Q₃₁Emitter and base
It is provided to ground the switch. Switch S ₃₁One
The end is a transistor Q₃₁Connected to the base of. each
Transistor Q of switch circuit 30₃₂Common emitter
Connected, resistor R₁Grounded through.

In the switch circuit corresponding to the transistors Q ₁ and Q ₃ of the head drive circuit 4a, each switch S ₃₁
~ S ₃₃ is the T-type flip-flop circuit 1

[0041]

[External 4] Output is gated. Similarly, transistor Q₂Oh
And Q_FourIn the switch circuit corresponding to, each switch S₃₁
~ S₃₃However, the Q output of the T-type flip-flop circuit 1
Controlled. Also, switch S₃₄And S₃₅, Switch
Chi S₃₆And S₃₇Are each connected in series and these series
In the connected one, the PMOS side becomes the constant current source 31 side.
In this way, it is provided in parallel between the constant current source 31 and the ground point.
Have been. Switch S₃₄, S₃₇Is the head select signal
Gate controlled by HS, switch S₃₅, S₃₆Is Inver
Gate control by the head select signal HS via the controller 12.
Have been. Switch S₃₄, S₃₅The common connection point of
Transistor Q of the switch circuit 30₁And Q₂Corresponding to
Switch S₃₁The other end of is connected. Similarly,
Itch S₃₆, S₃₇At the common connection point of
Transistor Q out of₃And Q _FourCorresponding to the switch
S₃₁The other end of is connected.

When the Q output of the T-type flip-flop circuit 1 is at a high level and the head select signal HS is at a low level, the constant current source 31 corresponds to the transistor Q ₁ via the switches S ₃₄ and S _31. Switch circuit 30
A potential difference occurs in the series circuit composed of the transistors Q ₃₁ and Q ₃₂ and the resistor R ₁ . As a result, this switch circuit 3
The base voltage of the transistor Q _{32 at} 0 is I′R ₁ + V _BE
And this is the transistor Q _{1 of the} head drive circuit 4a.
Given to the base of. Since the resistor R ₂ is connected to the emitter of the transistor Q ₁ , it eventually operates as a current mirror circuit, and the collector current of the transistor Q ₁ becomes I′R ₁ / R ₂ . At this time, the other transistor Q ₂ to Q ₄ are, in the non-operative state.

The feature of this circuit is that the base voltage control circuit operates in the current mode. Further, switches S ₃₄ and S ₃₆ are provided to switch the bias current source (constant current source 31) for each recording head.
As in the third embodiment, the decoding circuit could be simplified. The switches S ₃₂ , S ₃₃ , S ₃₅ , and S ₃₇ are for rapid discharge of accumulated charges, and the transistor Q ₃₁ is for compensation of h _fe .

As is apparent from the above description, the other transistors Q _{2 to} Q _{4 are} operated in the same manner as described above according to the head select signal HS and the output of the T-type flip-flop circuit 1.
Is also driven. In this case, is only one of the transistors Q ₁ to Q ₄ to operate simultaneously. Further, in this embodiment, since the resistor R ₂ is provided in the head drive circuit 4a instead of the constant current source, the output dynamic range for the recording heads H ₀ and H ₁ is expanded as compared with the case where the constant current source is used. .

Although the embodiment of the present invention has been described with respect to the case of two recording heads, it is extremely easy to increase the number of recording heads. For example, by using three head select input lines and a 3 → 8 decoder circuit, the case of 8 heads can be easily expanded. Further, the configurations of the decode circuit and the base voltage control circuit are not limited to those shown in the above-mentioned embodiments.

[0046]

As described above, the present invention is a CMOS type T which converts an input write data signal into an NRZ signal.
Type flip-flop circuit and a base voltage control circuit which is provided on the output side of the CMOS type T flip-flop circuit and selectively outputs a predetermined voltage, and each transistor forming a differential transistor pair of the head drive circuit. By connecting each output of the base voltage control circuit to the base of, the ECL circuit and the level shifter are not required, the number of required elements is reduced, the power consumption and the chip area are reduced, and the low voltage operation is reduced. It becomes possible and the cost is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a recording circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a recording circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a recording circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a recording circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional recording circuit.

FIG. 6 is a circuit diagram showing an example of a configuration of a conventional recording circuit.

FIG. 7 is a circuit diagram showing another example of the configuration of a conventional recording circuit.

[Explanation of symbols]

1 T-type flip-flop circuit 2 Decoder circuit 3, 3a, 3b, 3c Base voltage control circuit 4, 4a Head drive circuit 11 Constant current source H ₀ , H ₁ head HS Head select signal WD write data signal S _{1 to} S ₄ switch

Claims (6)

(57) [Claims] 1. A CM for converting an input write data signal into an NRZ signal in a recording circuit of a magnetic recording device having a differential transistor pair connected to a recording magnetic head and driving the magnetic head with current.
An OS-type T-type flip-flop circuit and a base voltage control circuit which is provided on the output side of the CMOS-type T-type flip-flop circuit and which selectively outputs a predetermined voltage, constitute the differential transistor pair. A recording circuit in which each output of the base voltage control circuit is connected to a base of each transistor. 2. A signal for corresponding to a plurality of magnetic heads, wherein the base voltage control circuit selects one of the pair of outputs of the CMOS type T-type flip-flop circuit and the plurality of magnetic heads. The recording circuit according to claim 1, wherein a predetermined voltage is alternatively output according to a signal decoded from the recording circuit. 3. The recording circuit according to claim 1, wherein the differential transistor pair is composed of a bipolar transistor. 4. The recording circuit according to claim 1, wherein the base voltage control circuit is a circuit that selectively switches a bias voltage with a MOS switch. 5. The recording circuit according to claim 1, wherein the base voltage control circuit is a circuit that selectively changes the voltage by a MOS switch. 6. The base voltage control circuit sets a constant current to M
3. The recording circuit according to claim 1, wherein the recording circuit is a circuit for generating a voltage by selectively flowing it through a load resistance by an OS switch.