JP2563633B2 - Method for assembling gallium arsenide semiconductor chip - Google Patents
Method for assembling gallium arsenide semiconductor chipInfo
- Publication number
- JP2563633B2 JP2563633B2 JP2057199A JP5719990A JP2563633B2 JP 2563633 B2 JP2563633 B2 JP 2563633B2 JP 2057199 A JP2057199 A JP 2057199A JP 5719990 A JP5719990 A JP 5719990A JP 2563633 B2 JP2563633 B2 JP 2563633B2
- Authority
- JP
- Japan
- Prior art keywords
- gallium arsenide
- active layer
- comb
- arsenide semiconductor
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N52/00—Hall-effect devices
- H10N52/101—Semiconductor Hall-effect devices
Landscapes
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Hall/Mr Elements (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、砒化ガリウム半導体基板から作られた、FE
T,ホール素子,IC,LSI,ダイオードのチップのダイスボン
ドの際の組み立て方法に関する。Description: FIELD OF THE INVENTION The present invention relates to FE made from a gallium arsenide semiconductor substrate.
The present invention relates to an assembly method for die bonding of T, Hall element, IC, LSI, and diode chips.
従来の技術 砒化ガリウム半導体を出発材料にした、FET,ホール素
子，ダイオードは、多くの分野で使用されている。又I
C,LSIについても使用が検討される段階に至っている。
今までは、これらのチップをコムにダイスボンドする
際、活性層の結晶軸からの設定は行なわれておらず、ワ
イヤボンドのしやすさの点のみから個々の品種毎に設定
されていた。2. Description of the Related Art FETs, Hall elements, and diodes made of gallium arsenide semiconductor as a starting material are used in many fields. See I
The use of C and LSI is now under consideration.
Until now, when these chips were die-bonded to a comb, the crystal axis of the active layer was not set, and they were set for each individual product only in terms of wire bondability.
発明が解決しようとする課題 このような従来の方法では、樹脂モールドした際のコ
ムの熱応力による歪、あるいは保存温度によるコムの熱
応力による歪が発生し、砒化ガリウムチップの活性層に
応力が働き、FETの場合、組み立て前後のしきい値の変
動、保存温度によるしきい値の変動が発生し、ホール素
子の場合、組み立て前後のオフセット電圧の変動、保存
温度によるオフセット電圧の変動が発生し、ダイオード
の場合、組み立て前後の容量値の変動、保存温度による
容量値の変動が発生し、IC,LSIの場合は、組み立て前後
で最大動作条件の変動が起こるという問題があった。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In such a conventional method, strain due to thermal stress of the comb during resin molding or strain due to thermal stress of the comb due to storage temperature occurs, and stress is applied to the active layer of the gallium arsenide chip. In the case of FET, the threshold voltage changes before and after assembly, and the threshold value changes depending on the storage temperature.In the case of Hall element, the offset voltage changes before and after assembly, and the offset voltage changes due to the storage temperature. In the case of a diode, the capacitance value fluctuates before and after assembly, and the capacitance value fluctuates depending on the storage temperature. In the case of IC and LSI, the maximum operating condition fluctuates before and after assembly.
課題を解決するための手段 本発明は、前記の問題点を解決するため、樹脂モール
ドした際のコムの歪、あるいは保存温度によるコムの歪
に対して、特性変動が発生しない活性層の方向、すなわ
ちFETの場合は〈001〉方向または〈010〉方向、ホール
素子の場合は〈011〉または〈01〉方向に形成したも
のを、FETの場合は活性層がコムの側面と平行に、ホー
ル素子の場合は±45度傾けて、それぞれ組み立てる。Means for Solving the Problems The present invention, in order to solve the above problems, the strain of the comb during resin molding, or the strain of the comb due to storage temperature, the direction of the active layer in which characteristic fluctuation does not occur, That is, in the case of FET, those formed in <001> or <010> direction and in the case of Hall element in <011> or <01> direction, in the case of FET, the active layer is parallel to the side surface of the comb. In the case of, tilt ± 45 degrees and assemble each.
又、チップの側面が〈001〉方向または〈00〉方向
と平行に組み立てる事で、コムの歪に対する特性変動を
抑える。Also, by assembling the side surface of the chip in parallel with the <001> direction or the <00> direction, the characteristic fluctuation due to the distortion of the comb is suppressed.
作用 この組み立て方法によれば、樹脂封止前後における特
性変動、保存温度による特性変動が抑えられ、安定な歩
留りを得る事ができる。Action According to this assembly method, the characteristic variation before and after resin sealing and the characteristic variation due to the storage temperature can be suppressed, and a stable yield can be obtained.
実施例 砒化ガリウム基板表面に作られた活性層の応力に対す
る特性変化は、たとえば「オリエンテーション・エフェ
クト・オブ・セルフアラインド・ソース／ドレイン・プ
ラナー・GaAs・ショットキー・バリア・フィールド−エ
フェクト・トランジスターズ,1983,アプライド・フィジ
ックス・レター・Ｎ・ヤマグチ・エト・アル,270〜28
1」（Orientation effect of self-aligned source/dra
in planar GaAs Suhottky barrier field-effect trans
istors 1983 Applied Phys.Letter N.Yokoyama et al 2
70〜281）に示されるよう、（100）面に活性層が形成さ
れている場合、〈011〉，〈01〉方向に比べて〈01
0〉，〈001〉方向が応力の影響を受けにくい。第１図
は、本発明の一実施例、すなわちFETを含む砒化ガリウ
ム半導体チップの組み立て図を示すものであり、コムの
側面１と砒化ガリウム基板２上に作られた〈001〉，〈0
10〉方向のFETの活性層３とが平行に組み立てられてい
る。第２図は、本発明の他の実施例、すなわちホール素
子を含む砒化ガリウム半導体チップの組み立て図を示す
ものであり、コムの側面１と砒化ガリウム基板２上に作
られた〈011〉，〈01〉方向のホール素子の活性層４
とが45度もしくは−45度傾けて組み立てられている。Example A change in characteristics of an active layer formed on the surface of a gallium arsenide substrate with respect to stress is described, for example, in "Orientation Effect of Self-Aligned Source / Drain Planar GaAs Schottky Barrier Field-Effect Transistors. , 1983, Applied Physics Letter N. Yamaguchi et al., 270-28
1 ”(Orientation effect of self-aligned source / dra
in planar GaAs Suhottky barrier field-effect trans
istors 1983 Applied Phys. Letter N. Yokoyama et al 2
70 to 281), when the active layer is formed on the (100) plane, compared with the <011> and <01> directions,
The 0> and <001> directions are not easily affected by stress. FIG. 1 is an assembly diagram of an embodiment of the present invention, that is, a gallium arsenide semiconductor chip including an FET, which is formed on the side surface 1 of the comb and the gallium arsenide substrate 2 <001>, <0.
The active layer 3 of the FET in the 10> direction is assembled in parallel. FIG. 2 is an assembly drawing of another embodiment of the present invention, that is, a gallium arsenide semiconductor chip including a Hall element, which is formed on the side surface 1 of the comb and the gallium arsenide substrate 2 <011>, < Active layer 4 of Hall element in the 01> direction
And are assembled at an angle of 45 degrees or -45 degrees.
FETの場合、コムの樹脂封止前後に発生する応力ある
いは保存温度の変化によって発生する応力を、FETの活
性層が応力によって変化しにくい方向に設定する事で、
（砒化ガリウムの場合、前述の〈001〉，〈010〉方向）
影響を少なくし、特性変化を抑える。In the case of FET, by setting the stress generated before and after resin sealing of the comb or the stress generated by the change in storage temperature in the direction in which the active layer of the FET is less likely to change due to stress,
(In the case of gallium arsenide, the above <001> and <010> directions)
Minimize the influence and suppress the characteristic change.
ホール素子の場合、等価回路は、第３図に示すように
４つの抵抗５〜８（それぞれの抵抗値をR1〜R4とする）
の集合体で記述でき、オフセット電圧VHOは、印加電圧V
Cの下で で表わされる。従って抵抗５〜８（R1〜R4）の応力によ
る変化によってVHOの特性変化が生ずる。In the case of the Hall element, the equivalent circuit has four resistors 5 to 8 (each resistance value is R 1 to R 4 ) as shown in FIG.
The offset voltage V HO is the applied voltage V
Under C Is represented by Therefore, changes in the resistance of the resistors 5 to 8 (R 1 to R 4 ) due to stress cause changes in the V HO characteristics.
ところが第２図の実施例においては、抵抗５〜８（R1
〜R4）が、ホール素子の活性層の方向に対して±45度傾
いている。よってホール素子の場合、コムの樹脂封止前
後に発生する応力あるいは、保存温度の変化によって発
生する応力を、ホール素子の活性層の±45度方向が、応
力によって変化しにくい方向に設定する事で、（砒化ガ
リウムの場合、前述の〈011〉，〈01〉方向）影響を
少なくし、特性変化を抑える。However, in the embodiment shown in FIG. 2, resistors 5 to 8 (R 1
~ R 4 ) is inclined ± 45 degrees with respect to the direction of the active layer of the Hall element. Therefore, in the case of a Hall element, the stress that occurs before and after resin sealing of the comb or the stress that occurs due to changes in storage temperature should be set so that the ± 45 degree direction of the active layer of the Hall element does not easily change due to stress. (In the case of gallium arsenide, the above-mentioned <011> and <01> directions) are less affected and the characteristic change is suppressed.
ダイオードの場合、活性層の方向は、方向性を持た
ず、この点では、前述のFET,ホール素子のように組み立
ての際の活性層の方向を指定する事によっては応力の影
響を除く事ができない。しかし、コムにダイスボンドす
る際、チップの方向を指定する事で、応力の影響を小さ
く抑える事ができる。このことを第４図を用いて説明す
る。In the case of a diode, the direction of the active layer has no directivity, and at this point, the influence of stress can be eliminated by specifying the direction of the active layer during assembly like the above-mentioned FET and Hall element. Can not. However, when the die is bonded to the comb, the influence of stress can be suppressed by specifying the chip direction. This will be described with reference to FIG.
ダイオードの場合、第４図に示すように、コムの側面
１と、ダイスボンドする砒化ガリウム半導体のチップ２
の側面が〈001〉方向または〈010〉方向のものとを平行
に組み立てる。このようにすれば、応力によって特性変
化しやすい〈011〉または〈01〉方向成分を最小値に
抑える事ができ、応力の影響を小さく抑える事ができ
る。In the case of a diode, as shown in FIG. 4, the side surface 1 of the comb and the dice-bonded gallium arsenide semiconductor chip 2 are used.
Assemble the side with the <001> or <010> direction in parallel. By doing so, it is possible to suppress the <011> or <01> direction component, which is likely to change in characteristics due to stress, to the minimum value, and to suppress the influence of stress.
本発明の各実施例の効果を、第５図〜第７図に示す。 The effects of each embodiment of the present invention are shown in FIGS.
第５図はFETの樹脂封止前後（ウエハの状態と組み立
て後）のしきい値電圧VTHの変化量ΔVTHを示す。FIG. 5 shows the amount of change ΔV TH in the threshold voltage V TH before and after resin sealing of the FET (wafer state and after assembly).
第６図はホール素子の樹脂封止前後（ウエハの状態と
組み立て後）のオフセット電圧VHOの変化量ΔVHOを示
す。FIG. 6 shows the amount of change ΔV HO in the offset voltage V HO before and after resin sealing of the Hall element (wafer state and after assembly).
第７図はダイオードの樹脂封止前後（ウエハの状態と
組み立て後）の順方向電圧VFの変化量ΔVFを示す。FIG. 7 shows the amount of change ΔV F in the forward voltage V F before and after resin sealing of the diode (wafer state and after assembly).
第５図〜第７図から明らかなように、本発明による砒
化ガリウム半導体チップの組み立て方法を用いると、特
性変動がない良好な特性を得る事ができる。As is apparent from FIGS. 5 to 7, when the method for assembling a gallium arsenide semiconductor chip according to the present invention is used, good characteristics without characteristic fluctuation can be obtained.
発明の効果 本発明によれば、樹脂封止前後における特性変動、保
存温度による特性変動が抑えられ、安定な歩留りが確保
でき、信頼性の面で大きく寄与することができる。EFFECTS OF THE INVENTION According to the present invention, characteristic fluctuations before and after resin encapsulation and characteristic fluctuations due to storage temperature can be suppressed, stable yields can be secured, and reliability can be greatly contributed.
第１図，第２図，第４図は本発明の第1,第2,第３の実施
例における砒化ガリウム半導体チップの組み立て方法を
示す斜視図、第３図はホール素子の等価回路を示す回路
図、第５図〜第７図は本発明の各実施例の効果を説明す
るための特性図である。 １……コムの側面、２……砒化ガリウム基板、３……FE
Tの活性層、４……ホール素子の活性層。1, 2, and 4 are perspective views showing an assembling method of the gallium arsenide semiconductor chip in the first, second, and third embodiments of the present invention, and FIG. 3 shows an equivalent circuit of the Hall element. Circuit diagrams and FIGS. 5 to 7 are characteristic diagrams for explaining the effects of the respective embodiments of the present invention. 1 ... side of comb, 2 ... gallium arsenide substrate, 3 ... FE
Active layer of T, 4 ... Active layer of Hall element.
Claims (2)
形成された活性層の方向が、FETの活性層の場合〈001〉
方向または〈010〉方向に形成されたもの、ホール素子
の場合〈011〉または〈01〉方向に形成されたもの
を、砒化ガリウム半導体基板から直方体のダイスに分割
した後、コムにダイスボンドする際、コムの側面と活性
層の方向が、FETの活性層の場合は〈001〉方向または
〈010〉方向と平行に組み立て、ホール素子の場合は〈0
11〉方向と45度もしくは−45度傾けて組み立てる事を特
徴とする砒化ガリウム半導体チップの組み立て方法。1. When the direction of an active layer formed in a (100) plane gallium arsenide semiconductor substrate is the active layer of a FET <001>.
Direction or <010> direction, in the case of Hall element, those formed in <011> or <01> direction are divided into cuboid dice from gallium arsenide semiconductor substrate and then die-bonded to comb. Assemble the side surface of the comb and the active layer parallel to the <001> direction or <010> direction for the active layer of the FET, and <0 for the Hall element.
11) A method for assembling a gallium arsenide semiconductor chip, which is characterized by being inclined at 45 degrees or −45 degrees with respect to the direction.
ダイスボンドする砒化ガリウム半導体のチップの側面が
〈001〉方向または〈010〉方向のものと平行に組み立て
られている事を特徴とする特許請求の範囲第１項記載の
砒化ガリウム半導体チップの組み立て方法。2. When the die is bonded to a comb, the side surface of the comb and the side surface of the gallium arsenide semiconductor chip to be die-bonded are assembled in parallel with the <001> direction or the <010> direction. A method of assembling a gallium arsenide semiconductor chip according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2057199A JP2563633B2 (en) | 1990-03-08 | 1990-03-08 | Method for assembling gallium arsenide semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2057199A JP2563633B2 (en) | 1990-03-08 | 1990-03-08 | Method for assembling gallium arsenide semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03257950A JPH03257950A (en) | 1991-11-18 |
| JP2563633B2 true JP2563633B2 (en) | 1996-12-11 |
Family
ID=13048824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2057199A Expired - Fee Related JP2563633B2 (en) | 1990-03-08 | 1990-03-08 | Method for assembling gallium arsenide semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2563633B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7183354B1 (en) * | 2021-07-27 | 2022-12-05 | 三菱電機株式会社 | semiconductor module |
-
1990
- 1990-03-08 JP JP2057199A patent/JP2563633B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03257950A (en) | 1991-11-18 |
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