JP2563671B2 - Data monitoring device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data monitor device, and more particularly to a data monitor device suitable for recording a data frame of a high speed multi-channel line at high speed and performing communication processing.

2. Description of the Related Art Conventionally, when monitoring a high-speed multiplex line such as an ISDN line, for example, at the S / T point, 2B + D data is separated and divided into frames, and the format is converted so that it can be displayed on a CRT. Then, a method of storing line data in a capture memory by a direct memory access (hereinafter, referred to as DMA) method is adopted.

However, in the conventional method, in particular, when the data of the high-speed multi-channel line is stored by the DMA method, the bus of the CPU is in a floating state while the data is being transferred. Program processing is suspended.
In particular, there has been a drawback that the CPU is locked when the processing such as a human interface such as a key input is disabled and the external control input is provided. This tendency is remarkable at the time of high-speed and multi-channel recording, and there is a problem that the CPU is almost in the hold state.

Specifically, as shown in FIGS. 2 and 3, the data on the communication line is processed by the communication control unit LSI unit 1 to make a DMA request to the MAIN CPU unit 2. Then, it activates the HOLD signal and responds to the bus hold request.
When the signal becomes active and the CPU is stopped, the line data is transferred to the CRT display unit 3 by DMA transfer and displayed on the display device. At this time, if an access is made from the keyboard 4 or the external control section 5, the CPU is in the hold state and the above-described predetermined processing cannot be performed.

An object of the present invention is to provide a data monitor device capable of transferring communication line data at high speed and storing the communication line data in a capture memory by a DMA method without being held by an arithmetic unit, thereby speeding up communication processing. Especially.

Means for Solving the Problems To achieve the above object, the present invention provides a communication control unit that performs frame processing of a communication line, a capture memory unit that inputs line data from the communication control unit via a bus line, and a capture unit. An arithmetic unit that exchanges data with the memory unit via the bus line, a switching unit that switches the bus line of the capture memory unit to the communication control unit side or the arithmetic unit side in response to a command, and data transfer from the communication control unit A communication control unit selection command is output by a request, and an operation unit selection command is output by an operation unit access request to the switching unit. When there is a conflict between the requests, the communication control unit selection command is output with priority. This is a configuration of a data monitor device provided.

Further, according to the present invention, as a second device including the first device, the control unit includes a first flip-flop for inputting a data transfer request from the communication control unit and a Q for the capture memory unit.
A second flip-flop that outputs a signal, a third flip-flop that inputs an access request from the arithmetic unit, a fourth flip-flop that outputs a Q signal to the switching unit, a Q signal of the first flip-flop, and a fourth flip-flop. A first AND gate that outputs a signal that is logically ANDed to the second flip-flop to the second flip-flop, and a signal that is logically ANDed to the signal of the first flip-flop and the Q signal of the third flip-flop. The data monitor device comprises a second AND gate for outputting to four flip-flops.

Therefore, according to the present invention, when the wiring data from the communication control unit is stored in the capture memory unit, the bus line of the capture memory unit is switched to the communication control unit side.
Therefore, when the line data is DMA-transferred to the capture memory unit, the arithmetic unit has nothing to do with it and is not held. Therefore, high-speed data transfer is performed. Further, when referring to the line data of the capture memory unit by the access request from the arithmetic unit, the bus line of the capture memory unit is switched to the arithmetic unit side. When the data transfer request from the communication control unit and the access request from the arithmetic unit conflict with each other, the communication control unit side is preferentially selected, so that the data in the line is not lost and the data is accumulated in the capture memory unit. .

Embodiment 1 FIG. 1 is a block diagram of a data monitor device according to an embodiment of the present invention.

In FIG. 1, the data monitor device is a communication control unit FEP1.
1, capture memory unit 12, CPU 13, address counter 1
4, multiplexers 15 and 16, D flip-flops 17a and 17b,
17c, 17d and AND gates 18a, 18b.

The FEP11 is configured to perform frame processing for multi-channel high-speed lines, etc.
It is configured to transfer the DMA request to the flip-flop 17a while transferring to the capture memory unit 12 via the. The CPU 13 is configured as an arithmetic unit that refers to the line data of the capture memory unit 12 via the multiplexer 16 and performs various processes based on the referred data. The multiplexer 15 is an address counter 14 and a capture memory unit.
The switching unit that switches the address line connecting with 12 according to a command is configured, and the multiplexer 16 is a capture memory unit.
Bus line connecting 12 and CPU 13 and capture memory unit 1
A switching unit that switches a bus line connecting the 2 and the communication control unit FEP11, a control bus line, and the like according to a command is configured.

The flip-flop 17a is configured to input the DMA request from the FEP 11, and the flip-flop 17c is configured to input the access request from the CPU 13.
The Q signal is output to the AND gate 18a, and the signal is output to the AND gate 18b. Also flip-flop 17c
The Q signal of is input to the AND gate 18b. The flip-flop 17b outputs a Q signal to the capture memory unit 12 in response to the signal from the AND gate 18a, and the flip-flop 17d receives the Q signal in response to the signal from the AND gate 18b.
The signal is output to the multiplexers 15 and 16, and the signal is output to the AND gate 18a.

 Next, the operation of the data monitor device will be described.

First, when the FEP 11 issues a DMA request, the flip-flop 17a is set. At this time, when the access request is not issued from the CPU 13, the flip-flop 17d is in the reset state, the gate of the AND gate 18a is opened, and the flip-flop 17b is set. When the flip-flop 17d is in the reset state, the multiplexers 15 and 16 are switched to the FEP 11 side and the line data from the FEP 11 is transferred to the capture memory unit 12 via the multiplexer 16. This line data is written in the capture memory unit 12 regardless of the operation of the CPU 13.

Next, when the FEP 11 does not generate a DMA request and the CPU 13 issues an access request, the flip-flop 17c is set and the flip-flop 17a is reset. As a result, the gate of the AND gate 18b is opened, the flip-flop 17d is set, the Q signal as the set signal is output to the multiplexers 15 and 16, and the data transfer acknowledge DTACK signal is output to the CPU 13. As a result, the multiplexers 15 and 16 are switched to the CPU13 side and the CPU1
3 and the capture memory unit 12 are connected via a multiplexer 16, and data is exchanged between the CPU 13 and the capture memory unit 12. That is, the CPU 13 is the capture memory unit 1
Read / write to 2 is possible.

Next, when an access request is issued from CPU13, F
When the DMA request is generated from the EP11, the flip-flop 17c is in the set state by the access request from the CPU 13, and the CPU 13 is in the state of accessing the capture memory unit 12. Has become. At this time, the flip-flop 17a is set by the DMA request from the FEP 11, but since the gate of the AND gate 18a is closed by the signal of the flip-flop 17d, the execution by the DMA request is made to wait until the flip-flop 17d is reset. . And CPU13
When the access to the capture memory unit 12 is completed, the flip-flop 17d is reset, the gate of the AND gate 18a is opened, and the flip-flop 17b is set to start the execution in response to the DMA request.

On the other hand, when an access request is issued from the CPU 13 during execution of DMA, the flip-flop 17a is set by the DMA request and the gate of the AND gate 17b is closed, so execution by access of the CPU 13 until the flip-flop 17a is reset. Is made to wait. That is, since the DTACK signal is not input to the CPU 13 until the flip-flop 17a is reset, the access request of the CPU 13 is made to wait until the DMA cycle ends.

EFFECTS OF THE INVENTION As apparent from the above embodiment, the present invention controls the bus line of the capture memory unit independently of the DMA request from the communication control unit and the access request from the arithmetic unit. Even in the DMA transfer indicating the data transfer from the unit, the line data can be transferred at high speed without holding the arithmetic unit, and the communication processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram of a data monitor apparatus which is an embodiment of the present invention, FIG. 2 is a block diagram of a conventional example, and FIG. 3 is a timing chart of the conventional example. 11 …… Communication control unit FEP, 12 …… Capture memory unit, 13
... CPU, 14 ... address counter, 15, 16 ... multiplexer, 17a, 17b, 17c, 17d ... D flip-flop, 18
a, 18b …… AND gate.

Claims (2)

(57) [Claims] 1. A communication control unit for performing frame processing of a communication line, a capture memory unit for inputting line data from the communication control unit via a bus line, and data transfer between the capture memory unit and the bus line. The operation unit, the switching unit that switches the bus line of the capture memory unit to the communication control unit side or the operation unit side in response to the command, and the communication control unit selection command from the operation unit in response to the data transfer request from the communication control unit. A data monitor device comprising: a control unit that outputs a calculation unit selection command to a switching unit in response to an access request, and preferentially outputs a communication control unit selection command when both requests conflict. 2. The control unit inputs a first flip-flop for inputting a data transfer request from the communication control unit, a second flip-flop for outputting a Q signal to the capture memory unit, and an access request for the arithmetic unit. The third flip-flop, the fourth flip-flop that outputs the Q signal to the switching unit, and the signal that is conditional on the logical product of the Q signal of the first flip-flop and the signal of the fourth flip-flop are output to the second flip-flop. And a second AND gate for outputting a signal conditioned on the logical product of the signal of the first flip-flop and the Q signal of the third flip-flop to the fourth flip-flop. ) The data monitoring device described above.