JP2565202B2 - Video signal order conversion method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal order conversion method for converting a television scanning order digital video signal into a three-dimensional block order.

[Outline of Invention]

According to the present invention, in a video signal order conversion method for converting an input digital video signal in a television scanning order into a three-dimensional block order, one video signal is converted into a three-dimensional block order. The memory having the capacity of the number of frames included in the three-dimensional block and the memory having the capacity of the number of lines included in one subsequent three-dimensional block are provided, and the address controller of the former memory has one address. The address controller of the latter memory has a cycle twice as many as the number of frames included in the three-dimensional block, and the address controller of the latter memory has a cycle twice as many as the number of lines included in one three-dimensional block. By generating an appropriate address so that there is no duplication, the order conversion method of digital video signals can be realized with a small memory capacity. That.

[Conventional technology]

When recording / reproducing a digital video signal on a VTR,
In order to compress the amount of data to be transmitted, a high efficiency coding method has been proposed in which the number of bits per sample is reduced from the original, for example, 8 bits. As one of the encoding methods, the applicant of the present application has proposed that ADRC (Adaptive Dynamic Range C
oding) has been proposed.

For example, as described in Japanese Patent Application No. 59-266407, the level difference (dynamic range) between the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block is calculated, and a code adapted to this dynamic range is obtained. Is made. Further, as described in Japanese Patent Application No. Sho 60-232789, there is provided an apparatus for performing coding suitable for a dynamic range with respect to a three-dimensional block formed from pixels of a two-dimensional area included in each of a plurality of frames. Proposed. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable-length coding method in which the number of bits changes according to the dynamic range such that the maximum distortion generated when quantization is constant. Proposed.

The ADRC described above can significantly compress the amount of data to be transmitted, so the digital data transmission rate is not high enough.
Suitable for VTR application. The ADRC that performs coding for each three-dimensional block requires a blocking circuit that converts the order of input digital video signals into the order of three-dimensional blocks. This blocking circuit requires a memory in order to change the order of pixel data of a plurality of frames.

For example, when one field image is divided into a large number of two-dimensional regions and two one-dimensional regions included in two temporally continuous frames (four fields) form one three-dimensional block, The block circuit shown in Figure 27 was used.

In FIG. 27, 22A and 22B indicate two-frame memories, respectively, and the input digital video signal from the input terminal 21 is written into one of the two-frame memories 22A and 22B via the switch circuit 23. The data read from the other of the two frame memories 22A and 22B is taken out to the output terminal 25 via the switch circuit 24. Each of the switch circuits 23 and 24 has a terminal a connected to the 2-frame memory 22A and a terminal b connected to the 2-frame memory 22B.

The connection states of the switch circuits 23 and 24 are switched in a cycle of two frames, and one of the switch circuits 23 and 24 has a terminal a.
In the two-frame period connected to the side, the other terminal is the terminal b.
Connected to the side. Therefore, the bank switching signal from the terminal 26 is supplied to the 2-frame memory 22A and the switch circuit 23, and the bank switching signal inverted by the inverter 27 is supplied to the 2-frame memory 22B and the switch circuit 24.

Address controllers 28 and 29 are provided, the address signal formed by the address controller 28 is supplied to one terminal c of the switch circuits 30 and 31, and the address signal formed by the address controller 29 is the other of the switch circuits 30 and 31. Is supplied to the terminal d. The output signal of the switch circuit 30 is used as a write address for the two frame memories 22A and 22A.
It is supplied to B and the output signal of the switch circuit 31 is supplied to the two-frame memories 22A and 22B as a read address.

The address controller 29 and the switch circuit 31 have terminals
The switching circuit 30 is controlled by the mode switching signal from 33, and the switch circuit 30 is controlled by the mode switching signal via the inverter 32. The mode switching signal is for designating each of the block forming operation and the block disassembling operation. During the blocking operation, the address signal generated by the address controller 28 is used as a write address, and the address signal generated by the address controller 29 is used as a read address. On the other hand, during block disassembly operation, the address controller 28
The address signal generated in 1 is used as a read address, and the address signal generated in the address controller 29 is used as a write address. In this way, the relationship between the write address and the read address is reversed between the blocking operation and the block disassembly operation, and the phase relationship between the write operation and the read operation is made different. At the time of blocking, the input data in the television scanning order is written in the two-frame memories 22A and 22B in the input order, and the output data converted into the three-dimensional block order is obtained by controlling the read address.

[Problems to be solved by the invention]

The above-described configuration requires two 2-frame memories, which increases the memory capacity and the circuit scale including the memory control circuit.

Therefore, it is an object of the present invention to provide a video signal order conversion method capable of reducing a memory capacity when a three-dimensional block is divided into blocks.

[Means for solving problems]

According to the present invention, the first predetermined amount of the input digital video signal is written into the memory by the first write address control (write 1), and the second predetermined amount of the digital video signal following the first predetermined amount is changed to the second predetermined amount. Data written by the write address control (write 2) and written by the write 1 is read by the first read address control (read 1) different from the write 1, and the data written by the write 2 is written. Different from write 2 and read by the second read address control (read 2) to obtain read data in the same order as the data read by read 1, starting from the write operation by write 1, 1 in the order of read operation, write 2 write operation, read 2 read operation It is controlled to operate.

[Action]

By the write 1, the four fields of the input digital video signal are written in the two-frame memory 51 in the input order (television scanning order). The next 4 fields of the input digital video signal are written to the 2 frame memory 51 by the light 2. The data written by the address control of the write 1 is read from the 2 frame memory 51 by the read 1. The data written in the 2-frame memory by the write 2 is read from the 2-frame memory by the read 2. In this manner, the 2-frame memory 51 sequentially outputs the data of 4 fields in the order of the number of lines contained in one 3D block, for example, every 8 lines.

The 2-frame memory 51 blocks in the direction of the time axis and then blocks in the horizontal and vertical directions. That is, when the number of pixels in one line in one block is, for example, four pixels, output data in the order of a three-dimensional block consisting of four pixels included in each line of eight lines can be obtained. An 8-line memory is used for this horizontal and vertical blocking. Number of pixels in one line
Considering the case where Nh is not divisible by 8, 9 line memory 52
Is used.

One block can be made into a three-dimensional block composed of 32 pixels of (4 pixels x 2 (lines) x 4 (fields)) with a memory capacity of (2 frames + 9 lines memory). The capacity can be reduced.

〔Example〕

The present invention will be described below. This explanation will be given in the order of the following items.

a. Recording side and shuffling circuit b. Playing side and deshuffling circuit c. Block and blocking circuit d.2 Frame memory address control e.9 Line memory address control a. Recording side and shuffling circuit No. 1 The figure shows the entire structure of the recording side. In FIG. 1, an input terminal indicated by 1 is supplied with a digital video signal having a sampling frequency of, for example, 13.5 [MHz]. This input digital video signal is supplied to the shuffling circuit 2 surrounded by a broken line. The shuffling circuit 2 converts the order of video data into an order different from the order of television scanning. The output signal of the shuffling circuit 2 is supplied to the blocking circuit 3 and converted into data in the order of three-dimensional blocks.

The output data of the blocking circuit 3 is supplied to the ADRC encoder 4, and the output data whose data amount is compressed by the ADRC encoder 4 is supplied. In ADRC encoder 4, minimum value MIN, maximum value MAX, dynamic range DR for each block
(= MAX-MIN) is detected, the number of bits is set according to the dynamic range DR, the dynamic range DR is divided into the number of level ranges determined by this number of bits, and the level range to which the pixel data after removal of the minimum value belongs A code signal DT corresponding to is formed.

Dynamic range DR, maximum value MAX, minimum value MIN
Of two additional data, eg dynamic range DR
And the minimum value MIN and the code signal DT are supplied to the framing circuit 5. In the framing circuit 5, the above data from the ADRC encoder 4 is converted into recording data having a frame structure. In the framing circuit 5, the error correction code is encoded as needed. Framing circuit 5
The recording data is taken out from the output terminal 6 of and is recorded on a magnetic tape by a rotary head (not shown).

If encoding is performed in 3D block units, AD
Not limited to RC, other encoding methods may be applied.

The shuffling circuit 2 has field memories 7A and 7B, and an input digital video signal is written to these field memories 7A and 7B via the switch circuit 8 for each field. Further, the data for one field alternately read from the field memories 7A and 7B is supplied to the blocking circuit 3 via the switch circuit 9. The switch circuit 8 and the switch circuit 9 are switched for each field and operate in opposite phases. For example, in a field in which one switch circuit 8 is connected to the terminal a side, the other switch circuit 9 is connected to the terminal b side.

At the time of writing data to the field memories 7A, 7B or reading data from the field memories 7A, 7B, at least one of a write address and a read address is controlled for shuffling. As an example, the input digital video signals are written in the field memories 7A and 7B in the input order (that is, the television scanning order), and the digital video signals are read from the field memories 7A and 7B in a different order from the input. .

FIG. 3 conceptually shows shuffling. An input digital video signal is written in one field memory in the order of input, and the content of this one field memory is read in the next field period. Shuffling is performed in units of the two-dimensional area numbered in FIG. 4 consecutive fields (2 frames)
A three-dimensional block is formed by a set of four two-dimensional regions at corresponding positions of. At the time of reading from the field memory, read addresses are set so that two spatially adjacent two-dimensional regions (nine nine-dimensional regions are shown in FIG. 3 as an example) in the input field are spatially separated from each other. Is controlled to obtain a shuffled output field. Due to this shuffling, burst errors generated during the VTR recording / reproducing process are dispersed, and the errors are made inconspicuous in the reproduced image.

b. Playback Side and Deshuffling Circuit FIG. 2 shows the entire construction of the playback side. In FIG. 2, an input terminal denoted by 11 is supplied with a digital playback signal reproduced by a VTR. This digital reproduction signal is supplied to the frame decomposing circuit 12, and the dynamic range DR of each block, the minimum value MIN and the code signal DT are separated. The output signal of the frame decomposition circuit 12 is supplied to the ADRC decoder 13, and the original pixel data is restored. ADRC decoder
The output signal of 13 is in block order and is therefore fed to the block decomposition circuit 14. The output signal of the block decomposition circuit 14 is supplied to a deshuffling circuit 15 surrounded by a broken line. The deshuffling circuit 15 reverses the order of data to the original order, that is, the order of television scanning, contrary to the shuffling circuit 2 on the recording side, and a reproduced digital video signal is obtained at its output terminal 16.

Like the shuffling circuit 2, the deshuffling circuit 15 includes two field memories 17A and 17B and a switch circuit 1
It is composed of 8 and 19. The switch circuits 18 and 19 include a terminal a connected to the field memory 17A and a field 17B.
And a terminal b connected to each of them. In a certain field, these switch circuits 18 and 19 are connected to the terminal a side, and the field memory 17A performs a write operation,
The field memory 17B performs a read operation. In the next field, the connection status of the switch circuits 18 and 19 changes,
The terminal b is selected. Therefore, the field memory 17A is in the read state and the field memory 17B is in the write state. By controlling at least one of the read address and the write address, the shuffled state is restored.

c. Block and Blocking Circuit FIG. 4 shows a three-dimensional block in this embodiment. In FIG. 4, f1, f2, f3, and f4 are two-dimensional regions of four consecutive fields in time. Are shown respectively. The size of one two-dimensional area is (2 × 4 pixels).
Therefore, one block includes 32 pixel data. The blocking circuit 3 converts the shuffled pixel data for each field into a [field f1 line L11 → field f1 line L12 → field f2 line L21 → field f2 line L22 → field f3 line L31 → field f3 Line L32 → line f41 of field f4 → line L42 of field f4] (the order of the four pixel data in each line is the scanning order).

FIG. 5A shows a basic structure of an example of the block forming circuit 3, and FIG. 5B shows a basic structure of the block decomposing circuit 14. Input data from the input terminal indicated by 41 in FIG. 5A is supplied to the two-frame memory 42, and is subjected to block processing in the time axis direction. That is, the order of the input data of two temporally consecutive frames (4 fields) that form one block is converted. If the first line of each of the four fields f1, f2, f3, f4 is L11, L21, L31, L41,
The 2-frame memory 42 changes the order of data in the order of [L11 → L21 → L31 → L41]. The data order of the second line is changed to the same order.

Output data of 2 frame memory 42 is 9 line memory 43
(It has a capacity of 9 lines). This 9
The line memory 43 performs horizontal and vertical blocking. In the case of the block shown in FIG. 4, L11, L12 L21
All data contained in the lines L22, ..., L41, L42 are written in the 9-line memory 43. And 9 line memory
From 43, output data is obtained from the output terminal 44 in the order (that is, the order of blocks) divided into four pixel data.
The capacity for 9 lines is prepared as described below.
This is to deal with the case where the number of pixels in one line is not divisible by 8.

In FIG. 5B, input data in the order of blocks is supplied to the input terminal indicated by 45 and is supplied to the 9-line memory 46. The 9-line memory 46 decomposes blocks in the horizontal and vertical directions, and the output data of the 9-line memory 46 is supplied to the 2-frame memory 47. The 2-frame memory 47 performs block decomposition in the time axis direction, and output data at the output terminal 48 is obtained in the same order as in television scanning.

The 2-frame memory and the 9-line memory can be shared by the block forming circuit 2 and the block disassembling circuit 15. FIG. 6 shows an example of a blocking / block decomposition circuit. In FIG. 6, 51 indicates a 2-frame memory,
52 indicates a 9-line memory.

The switch circuit S1 and the switch circuit S2 are respectively connected to the data input / data output side of the 2-frame memory 51, and the switch circuit S3 and the switch circuit S4 are respectively connected to the data input / data output side of the 9-line memory 52. To be done. Switch circuits S5 and S6 are connected to the data input terminal 53 and the data output terminal 54, respectively. 2 frame memory
The switch circuits S7 and S8 are connected to the address signal supply path at 51, respectively, and the switch circuits S9 and S10 are similarly connected to the address signal supply path at the 9-line memory 52, respectively. The output signal of the switch circuit S7 is the 2-frame memory 51.
Is supplied as a write address to the switch circuit
The output signal of S8 is supplied to the 2-frame memory 51 as a read address. Further, the output signal of the switch circuit S9 is supplied to the 9-line memory 52 as a write address, and the output signal of the switch circuit S10 is supplied to the 9-line memory 5.
It is supplied to 2 as a read address.

The address signal for the 2-frame memory 51 is generated by the frame memory control circuits 55 and 56, and the address signal for the 9-line memory 52 is generated by the line memory control circuit.
Produced by 57 and 58. Frame memory control circuit 55
And 56, a timing signal is passed between
Similarly, timing signals are transferred between the line memory control circuits 57 and 58.

A mode switching signal is supplied from the terminal t to the switch circuits S1 to S10, the frame memory control circuit 55, and the line memory control circuit 57 to switch between the block forming operation and the block disassembling operation. When functioning as the blocking circuit 3, the switch circuits S1 to S10 are connected to the terminal a side as shown in FIG. 6, and when functioning as the block disassembling circuit 14, the switch circuits S1 to S10 are connected to the terminal b side. Is also connected.

When the switch circuits S1 to S10 are connected to the terminal a side, the input data from the input terminal 53 is input to the switch circuits S5 and S1.
And the data read from the two-frame memory 51 are written into the nine-line memory 52 via the switch circuits S2 and S3. The data read from the 9-line memory 52 is taken out to the output terminal 54 via the switch circuits S4 and S6. At the time of this blocking operation, the address signal formed by the frame memory control circuit 55 is supplied to the 2 frame memory 51 as a write address, and the address signal formed by the frame memory control circuit 56 is supplied to the 2 frame memory 51 as a read address. Supplied. Similarly, the address formed by the line memory control circuit 57 is supplied to the 9-line memory 52 as a write address, and the address formed by the line memory control circuit 58 is supplied to the 9-line memory 52 as a read address.

During the block disassembly operation in which the switch circuits S1 to S10 are connected to the terminal b side, the input data from the input terminal 53 is written to the 9-line memory 52 via the switch circuits S5 and S3 and read from the 9-line memory 52. The written data is written in the two-frame memory 51 via the switch circuits S4 and S1, and the data read from the two-frame memory 51 is taken out to the output terminal 54 via the switch circuits S2 and S6.
During this block disassembly operation, the frame memory control circuit
The read address is formed by the 55 and the line memory control circuit 57, and the write address is formed by the frame memory control circuit 56 and the line memory control circuit 58. That is, in the block forming operation and the block disassembling operation, the address signals for the 2-frame memory 51 and the 9-line memory 52 have the write address and the read address in the opposite relationship.

d.2 Address control of frame memory The address control of the two-frame memory 51 in the case of blocking is described below. This address control is
[Write 1 → Read 1 → Write 2 → Read 2] is performed cyclically so as to be completed in four frames. Seventh
FIG. 8, FIG. 9, FIG. 9 and FIG. 10 show address control when one field is composed of 12 lines for simplification. Address of 2 frame memory is Ax, Ay, Az
Given by Ax represents an address in the horizontal direction (pixel unit), Ay represents an address in the vertical direction (line unit), and Az represents an address in the time direction (field unit).

The shuffled input digital video signal is first written in the 2-frame memory by the address control of the write 1. When the address control is performed in the line 1 mode, as shown in FIGS. 7A, 7B and 7C, the two-frame memory is written in the input order. That is, the address Az (FIG. 7C) is increased stepwise for each field of the input data, and the address Ay
(Fig. 7B) is 0 to 12 for each line in one field.
It will be increased step by step.

The data written by the write 1 is read from the 2 frame memory by the address control of the read 1. As shown in FIG. 8A, FIG. 8B, and FIG. 8C, in the lead 1,
Corresponding 4 lines of 4 fields are read in order. That is, the address Az (FIG. 8C) is changed to 0, 1, 2, and 3 while the address Ay (FIG. 8B) is fixed to a predetermined line in (0 to 11). . By the operations of the write 1 and the read 1 described above, the blocks are formed in the time axis direction using the 2-frame memory.

The input data in the next 4 fields of the input data written by the write 1 is written in the 2 frame memory by the write 2. As shown in FIG. 9A, FIG. 9B, and FIG. 9C, in write 2, one field is divided into four, and 1/4 field of data is written and then 1 / n of the next field is written.
The data is written in 1/4 fields, just like writing data for 4 fields. That is, 1 field is 12
In the case of a line, one field is divided every three lines, and the address Az (FIG. 9C) changes between three lines while the address Ay (FIG. 9B) repeatedly changes for three lines.

The data written by this write 2 is read by the address control of read 2. Fig. 10A, Fig. 10B, Fig.
As shown in FIG. 10C, in lead 2, the same field
The first line of each 1/4 field is read first, then the second line of each. When this read operation is completed for that one field,
The same read operation is performed for the next field. That is, during one field period in which the address Az (FIG. 10C) has a predetermined value, the address Ay (FIG. 10B) is (0, 3,
6,9) (1,4,7,10) (2,5,8,11).

The next data written by write 2 is again written by write 1.
Is written in the two-frame memory by the address control of. With the above address control, the read data from the two-frame memory outputs the first lines of the four consecutive fields of data sequentially, and then the second lines of the four fields sequentially. In the same manner, the corresponding lines of 4 fields are sequentially output.

FIG. 11 is a diagram showing a phase relationship between a line operation and a read operation in a 2-frame memory when one field is composed of 12 lines. In FIG. 11, a vertical line indicates a length corresponding to a period in which one line of data occupies a corresponding address of a 2-frame memory. That is, the data written at the timing of one end on the upper side of this vertical line is read at the timing of the other end on the lower side. The order of the fields of the input data is [f01 → f02 → f03 → f04 → f11 → f12 ... ・ ・ ・ f23
→ f24], the input data of the first 4 fields is sequentially written in the 2 frame memory by the address control of write 1, and then this data is sequentially read from the 2 frame memory by the address control of read 1. .
From the middle of the read 1 period, the input data of the next field f11 is written in the 2 frame memory by the address control of the write 2. From the middle of the light 2 period,
The written data is read by the address control of the read 2. The input data of the next field f21 is written by the address control of the write 1 from the middle of the read 2 period. As shown in FIG. 11, the lines in the vertical direction do not overlap each other, so that the input data is written in the two-frame memory without excess or deficiency and is read without any loss.

Generally, when reading the first written data of write 1 by read 1, the number of lines in one field is
If it is Nf, it is performed at the timing of the line of (3Nf-3).

The above is the address control of the two-frame memory during the blocking operation. Address control at the time of block decomposition is
The write address and the read address are exchanged.

FIG. 12 shows a concrete example of an address counter for performing the address control performed at the time of the above-mentioned block formation. 12th
In the figure, CTx indicates a counter for generating the address Ax, CTy−1, CTy-2 indicate counters for generating the address Ay, and CTz indicates a counter for generating the address Az. . The counter CTx has a count range of (0 to Nh-1) when the number of pixels included in one line is Nh, and the weight of one count is 1. Counter CT
y−1 is the maximum value of the address Ay Nv (= 4 × m, where m
Is a natural number and has a count range of (0 to 1/4 Nv-1), and the weight of 1 count is 1. Counter CTy
-2 has a count range of (0 to 3) and the weight of 1 count is 1/4 Nv. The counter CTz has a count range of (0 to 3), and the weight of 1 count is 1 (1 field).

The four counters CTx, CTy-1, CTy-2, CTz are configured to transmit the carry output of the lower counter to the upper counter. In FIG. 12A, the carry output is transmitted in order from the lower counter to the upper counter, and the address signal in the case of write 1 is formed.

As shown in FIG. 12B, the carry output of the counter CTx is transmitted to the counter CTz, the carry output of the counter CTz is transmitted to the counter CTy-1, and the carry output of the counter CTy-1 is transmitted to the counter CTy-2. With this configuration, an address for lead 1 is formed.

As shown in FIG. 12C, the carry output of the counter CTx is transmitted to the counter CTy-1, the carry output of the counter CTy-1 is transmitted to the counter CTz, and the carry output of the counter CTz is transmitted to the counter CTy-2. With this configuration, an address for write 2 is formed.

As shown in FIG. 12D, the carry output of the counter CTx is transmitted to the counter CTy-2, the carry output of the counter CTy-2 is transmitted to the counter CTy-1, and the counter CTy-1.
The address for the lead 2 is formed by the structure in which the carry output is transmitted to the counter CTz.

As is clear from FIG. 12, the address counter needs a system corresponding to four types of address control.
However, the write 1 and the write 2 do not overlap in time, and only one counter configuration is required for address control during the write operation. Switching between the write 1 and the write 2 is performed by the gate circuit. It is sufficient to switch the connection relationship between them. Similarly, only one counter is required for address control during the read operation, and the leads 1 and 2 can be changed by switching the connection relationship between the counters.

e.9 Line memory address control By the block formation using the 2 frame memory described above,
In 4 fields that are temporally continuous, (2 lines × 4 = 8 lines) of data necessary for constructing a three-dimensional block are continuous in the time direction and blocked. next,
The 9-line memory divides each line into 4-pixel data, and blocks in the horizontal and vertical directions in which 4 pixels each belonging to the above-mentioned 8 lines are collected.

Blocking using the 9-line memory will be described below. For easy understanding, one field consists of 8 lines, and the number of pixels in each line is divisible by 8 (8n). The address control of the 9-line memory is performed in a cycle of [write 1 → read 1 → write 2 → read 2].

As shown in FIG. 13A, the input data of the first 8 lines is written in the 9-line memory in the order of input (write 1). No data is written to the 9th line of the 9-line memory. As shown in FIG. 14A, the next eight lines of input data are written in eight lines for each n pixels formed by dividing each line into eight (write 2).

The read of the data written by the address control of the write 1 is performed for each pixel at the same position in the vertical direction as shown in FIG. 13B (read 1). The data of four consecutive columns (total 32 pixel data) constitutes one three-dimensional block. Further, as shown in FIG. 14B, reading of the data written by the address control of the write 2 is skipped every 4 pixels in the horizontal direction of each line (read 2). After reading one line,
The next line is similarly read. Like the data read by the address control of the read 1, the data read by the address control of the read 2 forms one three-dimensional block by 32 pixel data which are temporally continuous.

Regarding the address control of the 9-line memory described above, a case where the number of pixels Nh in one line is 32 (n = 4) will be described as an example. During address control of write 1, FIG. 15A and FIG.
As shown in FIG. B, the address Ay increases to (0,1,2, ... 7), and the address Ay is increased within a predetermined value period.
Increases to (0,1,2, ... 31,32 (= 0)).

When address control of the read 1 is performed, as shown in FIGS. 16A and 16B, the address Ay is (0, 1, 2 ... 7, 8 (= 0) during a period when the address Ax has a predetermined value. )), The pixels at the same position are sequentially read from each line.

During the address control of the write 2, as shown in FIGS. 17A and 17B, the address Ay is incremented every time the address Ax changes to (0, 1, 2, 3).

At the time of address control of the lead 2, as shown in FIGS. 18A and 18B, the address Ay is incremented every 32 pixel data period, and the address Ax is a discrete value (0, 4) every 4 pixels. , 8, ... 28) (1,5,9, ... 29) ...
.. (3,7,11, ... 31) to be changed.

FIG. 19 is a diagram showing the phase relationship between the write operation and the read operation in the 9-line memory. Similar to FIG. 11 described above, in FIG. 19, the closed area has 9 lines of data.
The period during which a predetermined address of the line memory is occupied is shown. That is, the data written at the timing of one end on the upper side of the closed region is read at the timing of the other end on the lower side. The input data of the first 8 lines of the input data is sequentially written in the 9-line memory by the write 1 address control, and then this data is sequentially read from the 9-line memory by the read 1 address control.
The input data of the next 8 lines is written in the 9-line memory by the address control of the write 2 from the middle of the period of this read 1. The written data is read from the middle of the period of the write 2 by the address control of the read 2. The input data of the next 8 lines is written by the address control of write 1 from the middle of the period of read 2. As shown in FIG. 19, the closed areas do not overlap each other, so that the input data is written in the 9-line memory without excess or deficiency, and is read without any omission.

Generally, the data written in the 9-line memory at the beginning of the 8-line input data is read at the timing of (7Nh-7) data.

The above is the address control of the 9-line memory during the block operation. Address control at the time of block decomposition is performed by exchanging the write address and the read address.

Address control when the number of pixels Nh in one line is not divisible by 8 will be described below. Similarly to the above, address control is performed in the cycle of [write 1 → read 1 → write 2 → read 2].

As shown in FIG. 20A, in the address control of the write 1, the input data is sequentially written from the first line in the order of input. The 9-line memory has a horizontal address corresponding to the number of pixels Nh in one line. This number of pixels Nh
Is (8n + Δ). The data written by the write 1 address control is read from the 9-line memory by the read 1 address control. As shown in FIG. 20B,
The lead 1 sequentially reads pixel data at the same position in the vertical direction. The address control of these write 1 and read 1 is the same as when the number of pixels Nh in one line is divisible by 8.

At the time of writing the next 8 lines of input data, n
The data is divided into a group of pixel data and a group of mod. (Nh, 8) pixels, and these groups are written over 9 lines as shown in FIG. 21A (write 2). The data written by the write 2 address control is read 2
Is read from the 9-line memory by the address control of. As shown in FIG. 21B, in the lead 2, reading is performed in every four pixels in the horizontal direction.

Address control when the number of pixels Nh in one line is not divisible by 8 will be described as (Nh = 34). FIG. 22 shows addresses Ax and Ay when writing data by the write 1 operation. The address Ay (Fig. 22B) is (0,
1, 2, ... 7) every 34 pixels, and the address Ax (FIG. 22A) is (0, 1, 2,
・ ・ ・ ・ 34)

The data written by the operation of write 1 described above is read by the operation of read 1. Figure 23 shows
Address when reading data by read 1 operation
Ax and Ay are shown. In the lead 1, since the pixel data at the same position in the vertical direction is sequentially read from each line,
Address Ax (Fig. 23A) is (0,1,2, ... 34) and 8
The value is increased pixel by pixel and the address Ay (FIG. 23B) is (0, 1, 2, ... 7) within the period of the predetermined value of the address Ax.
Is changed.

FIG. 24 shows addresses Ax and Ay when writing data by the operation of write 2. The address Ay (FIG. 24B) is changed to (0, 1, 2, ... 8) every 4 pixels within a period in which input data of 34 pixels for one line is supplied. Further, the address Ax (FIG. 24A) is changed to (0, 1, 2, 3) within the period of 4 pixels.

The data written by this write 2 is read from the 9-line memory by the operation of read 2. As shown in FIG. 25B, the address Ay is (0, 1,
2 ... 8) changes. In the period of one line where the address Ay is a predetermined value, the address Ax (FIG. 25A) changes every four, and the address Ax changes four times,
Data of one line is read.

FIG. 26 shows a specific example of the address counter for performing the address control performed when the blocks are divided in the horizontal and vertical directions. In Figure 26, CTx-1 and CTx
-2 indicates a counter for generating the address Ax,
CTy indicates a counter for generating the address Ay.
The counter CTx-1 has a count range of [0 to int (Nh / 8) -1], and a weight of 1 count is 1 pixel (in the horizontal direction). The counter CTx-2 has a count range of (0 to 8), and the weight of 1 count is int (Nh / 8) (however, in the horizontal direction). The counter CTy has a count range of (0 to 8) and the weight of 1 count is 1 (however, in the vertical direction).

FIG. 26A shows a connection configuration of the counter and the gate circuit when the address control of the write 1 is performed. FIG. 26B shows a connection configuration of the counter and the gate circuit when the address control of the lead 1 is performed. FIG. 26C shows a connection configuration of the counter and the gate circuit when the address control of the write 2 is performed. FIG. 2D shows the connection configuration of the counter and the gate circuit when the address control of the lead 2 is performed.

As is clear from FIG. 26, the address counter needs a system corresponding to four types of address control.
However, like the control of the two-frame memory, the write 1 and the write 2 do not overlap in time, and only one counter configuration is required for address control during the write operation.
To switch between the light 1 and the light 2, the connection relationship between the counters may be switched by the gate circuit. Further, only one counter configuration is required for address control during the read operation, and the lead 1 and the lead 2 can be changed by switching the connection relationship between the counters.

〔The invention's effect〕

According to the present invention, the three-dimensional block can be divided into blocks with a small memory capacity. That is, the processing of blocking can be performed with the memory having the capacity of the number of frames included in one three-dimensional block and the number of lines included in one three-dimensional block.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the recording side of a digital VTR in which the blocking circuit according to the present invention is used, and FIG. 2 is a block diagram showing the configuration of the reproducing side of a digital VTR in which the blocking circuit is used. FIG. 3 is a schematic diagram showing an outline of the shuffling, FIG. 4 is a schematic diagram for explaining a three-dimensional block in this embodiment, and FIGS. 5 and 6 are a block circuit and a block disassembly circuit. Block diagram, 7th
FIG. 8, FIG. 9, FIG. 9 and FIG. 10 are schematic diagrams for explaining the address control of the 2-frame memory provided in the block circuit, and FIG. 11 are for explaining the address control of the 2-frame memory. FIG. 12 is a block diagram showing the configuration of the address counter of the 2-frame memory, and FIGS. 13 and 14 are schematic diagrams for explaining writing and reading of data to and from the 9-line memory. Figure 15, Figure 16, Figure 17, Figure 18
FIG. 19 and FIG. 19 are schematic diagrams for explaining address control of a 9-line memory, and FIGS. 20 and 21 are schematic lines for explaining another example of writing and reading data to and from the 9-line memory. FIG. 22, FIG. 23, FIG. 23, FIG. 24 and FIG. 25 are schematic diagrams for explaining another example of address control, and FIG. 26 is a block diagram showing the configuration of an address counter of a 9-line memory.
FIG. 27 is a block diagram showing a configuration of an example of the block circuit. Description of main symbols in the drawings 1: Digital video signal input terminal, 2: Shuffling circuit, 3: Blocking circuit, 14: Block disassembly circuit, 15: Deshuffling circuit, 51: 2 Frame memory, 52: 9 Line memory, 53: Data input terminal, 54: Data output terminal, 55, 56:
Frame memory control circuit, 57, 58: line memory control circuit.

Claims (1)

(57) [Claims] 1. A first predetermined amount of an input digital video signal is written to a memory by a first write address control, and a second predetermined amount of the digital video signal following the first predetermined amount is a second predetermined amount. The data written in the memory by the write address control and written by the first write address control is read out by the first read address control different from the first write address control, and the second write address The data written by the control is different from that of the second write address control, and is read by the second read address control for obtaining the read data in the same order as the data read by the first read address control. Is issued, starting from the write operation under the first write address control, the first read add The video is characterized in that the memory is controlled so as to operate in the order of the read operation by the memory control, the write operation by the second write address control, and the read operation by the second read address control. Signal order conversion method.