JP2568698B2 - Bus control method - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problem Actions Embodiment I. Correspondence between embodiment and FIG. 1 II Configuration and operation of the embodiment Effect of the Invention [Overview] Regarding a bus control system that inputs and outputs data via a bus using a complementary MOS, it is possible to prevent an increase in power consumption and to degrade elements due to heat generation. Data receiving means for receiving data supplied via a bus by a complementary MOS, and a plurality of first bus drivers for transmitting data to the bus in accordance with drive signals supplied to the buses, respectively. Determining means for determining that all of the plurality of drive signals have not been supplied, and transmitting data to the bus based on the determination result of the determination means when all of the plurality of drive signals have not been supplied. Second bus driver It comprises so that it may have.

Further, when transmitting data from a plurality of bus drivers to the bus, one bus driver is driven at a time, and one of the bus drivers is always driven, and the bus that has been driven first is The configuration is such that the time when the drive signal is supplied redundantly to the driver and the bus driver driven following the bus driver is eliminated.

[Industrial applications]

The present invention relates to a bus control system for inputting / outputting data via a bus using a complementary MOS (hereinafter referred to as CMOS).

[Conventional technology]

CMOS has a configuration in which a p-channel type and an n-channel type MOSFET are combined, and the power consumption is extremely low.
It has excellent features different from conventional logic elements, such as a wide operating voltage range, and is widely used with TTL.

FIG. 4 shows the configuration of a digital signal processor (hereinafter referred to as DSP) configured using CMOS.

In the figure, a DSP 411 includes a processing execution unit (hereinafter referred to as an ALU) 421 for performing operations such as addition and multiplication, a ROM 431 for holding execution programs and data, and an RA for storing execution data.
An M441, registers 451 and 461 for exchanging data with the outside of the DSP 411, and a bus driver 471 for sending data to an internal bus are provided, and each component is connected by the internal bus.

In such a DSP 411, when the ALU421 or the like sends data to other components via the internal bus, the data is set in the output register inside the ALU421, and then the bus driver 471 composed of CMOS is driven to drive the internal bus. To send data. The side (for example, the RAM 441) that receives the data transmitted to the internal bus in this way receives the data by an input register having a CMOS inverter or the like inside.

[Problems to be solved by the invention]

By the way, in the above-described conventional system, the bus is opened by setting the output terminal of the bus driver 471 which does not transmit data to a high impedance state in order to avoid data collision on the internal bus. Therefore, when a state occurs in which all the bus drivers 471 do not transmit data to the internal bus, the input terminal of the CMOS inverter or the like on the data receiving side enters a high impedance state (open state).

FIG. 5 shows the configuration and input / output relationship of the CMOS inverter. As shown in the figure, the CMOS inverter is composed of pMOSFET and n
It has a configuration in which a MOSFET and a pair are connected, and when the input logic is "0", the pMOSFET is turned on, so that the output logic is "1" ((a) in FIG. ). Conversely,
When the input logic is "1", the nMOSFET is turned on, so that the output logic is "0" (FIG. 9B). The input side of such a CMOS inverter is connected to the internal bus, and this input side has a high impedance state (open state).
If CMOS continues for a long time, depending on the potential state on the input side, CMOS
In some cases, the pMOSFET and the nMOSFET inside are turned on at the same time, and a current flows between the power supplies V _DD and V _SS (FIG. 3C). Therefore, there is a problem that the power consumption increases due to the energization and heat is generated due to the power consumption to deteriorate the element.

Further, at the time of switching the driving state of the bus driver 471 made of CMOS (for example, when driving of the bus driver 471 connected to the ALU 421 is completed and then driving of the bus driver 471 connected to the ROM 431), In some cases, data is temporarily sent from the two bus drivers 471 to the internal bus.

Data is sent simultaneously from two bus drivers 471,
Further, when data of different logic is transmitted, the output terminal of the CMOS inverter shown in FIG.
Is connected to the output terminal of the CMOS inverter shown in (1).
, A current flows between the power supplies V _DD and V _SS .
Therefore, this energization increases power consumption and
There is a problem that heat is generated due to the power consumption and the element is deteriorated.

The present invention has been made in view of such a point, and an object of the present invention is to provide a bus control system which prevents an element from deteriorating due to an increase in power consumption and heat generation.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of the bus control system according to the present invention.

(I) Invention of Claim 1 In FIG. 1A, the data receiving means 111
Data supplied via 10 is received by the complementary MOS.

Each of the plurality of first bus drivers 121 sends data to the bus 110 according to the drive signal supplied to each.

The determination unit 131 determines that all of the plurality of drive signals have not been supplied.

The second bus driver 141, based on the determination result of the determination unit 131, when all of the plurality of drive signals have not been supplied,
The data is transmitted to the bus 110.

Therefore, as a whole, the second bus driver 131 is configured to be driven in accordance with the driving state of the plurality of first bus drivers 121.

(Ii) Claim 2 In FIG. 1 (B), each of the plurality of bus drivers 151 sends data to the bus 150 by the complementary MOS in response to the respective drive signals.

The selection signal creation unit 161 is provided with the plurality of bus drivers 151.
Signal periods for are assigned in time series,
A selection signal is assigned to each of the remaining bus drivers except one of the plurality of bus drivers 151, and during an arbitrary signal period on the time series, temporarily,
One of the remaining bus drivers is selected, and outputs a selection signal at a first signal level during a signal period corresponding to the selection (hereinafter, referred to as a selection signal period). On the other hand, it outputs a non-selection signal at the second signal level during the selection signal period.

The OFF signal output unit 171 ends the signal period from a predetermined time elapsed from the signal period start time of the signal period in the time series, regardless of whether the selection signal is output by the selection signal generation unit 161. It is at the first signal level until a time before a predetermined time before the time, and is predetermined from a time before a predetermined time before the end time of each signal period and a start time of the next signal period of the signal period. And outputs the off signal at the second signal level until the elapsed time.

The bus driver control means 181 is provided with the selection signal creation means 1
The selection signal output from 61 and the off signal output means 17
A drive signal is supplied to the bus driver corresponding to the selection signal during the selection signal period in response to the off signal output from 1, and the selection signal period generated for any bus driver not selected. The drive signal is supplied to the plurality of bus drivers 151 in response to the non-selection signal and the OFF signal during the period.
To one of the bus drivers.

The invention according to claim 2 is characterized in that the plurality of bus drivers 151
And the selection signal generation means 161, the off signal output means 171, and the bus driver control means 181.

(Operation)

(I) Claim 1 The plurality of first bus drivers 121 are driven according to drive signals supplied to each of them, and transmit data to the bus 110. The determination means 131 determines that all of the drive signals supplied to each of the first bus drivers 121 are in an unsupplied state. At this time, the second bus driver 141 is driven to transmit data to the bus 110. Send out. The data transmitted to the bus 110 is received by the complementary MOS in the data receiving means 111.

According to the invention of claim 1, a plurality of first bus drivers are provided.
By driving the second bus driver 141 when the determination unit 131 determines that all of the 121 are not driven,
The receiving end of the data receiving means 111 for receiving data by the complementary MOS is prevented from being open for a long time.

(Ii) The remaining bus drivers other than one of the plurality of bus drivers 151 are output from the selection signal output unit 161 and the off signal output unit 171. Bus driver control means 18 responding to the OFF signal
For the remaining bus drivers except one bus driver of the plurality of bus drivers 151 from 1 at a time,
A drive signal is supplied to only one bus driver (selected), and data is transferred to the bus 15 via the bus driver.
Supplied to 0.

Further, during the selection signal period in which no selection signal is output from the selection signal generation means 161 and each non-selection signal is output, the bus driver control means 181 responding to each of the non-selection signals and the off signal outputs the selection signal. A drive signal is supplied to one of the plurality of bus drivers 151 and supplied to the bus 150 via the bus driver.

When any of these bus drivers are driven,
According to the second signal level of the off signal output from the off signal output means 171, the driving signal is supplied to the bus driver that is driven first and the bus driver that is driven following the bus driver in an overlapping manner. Things will be gone.

Therefore, among the plurality of bus drivers, only one bus driver is driven at a time, and the two bus drivers are not driven simultaneously at the time of switching.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a configuration of a DSP according to an embodiment to which the bus control system of the present invention is applied.

I. Correspondence Between Embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be described.

 The bus 110 corresponds to the internal bus 291.

The data receiving means 111 corresponds to the input registers 271, 273, 275.

The first bus driver 121 corresponds to the bus drivers 211, 213, 215.

 The determining means 131 corresponds to the bus control circuit 231.

The second bus driver 141 corresponds to the bus driver 217.

 The bus 150 corresponds to the internal bus 291.

The bus driver 151 corresponds to the bus drivers 211, 213, 215, 217.

The selection signal creation means 161 corresponds to the output register selection circuit 253.

 The off signal output unit 171 corresponds to the off circuit 255.

The bus driver control unit 181 corresponds to the bus control circuit 231.

An embodiment of the present invention will be described below assuming that there is the above correspondence.

II. Configuration and operation of embodiment In FIG. 265 is the instruction register, 2
71, 273 and 275 indicate input registers, and 291 indicates an internal bus.

FIG. 2 shows the configuration of the DSP focusing on the data input / output operation via the internal bus 291. The overall configuration is the same as that of FIG.

The bus drivers 211, 213, 215, and 217 are for transmitting data to the internal bus 291. When the logic of the drive signal supplied from the bus control circuit 231 is "1", the bus drivers 211, 213, 215, and 217 are held in the corresponding output registers 221 to 227. Data to the internal bus 291. On the other hand, when the logic of the drive signal is “0”, the output terminal is set to a high impedance state to prevent data collision on the internal bus 291.

The output registers 221, 223, 225, and 227 are components (for example, ROM, RAM, and AL) having a function of outputting data to the internal bus 291.
U), and after storing data in these output registers, the above-described bus driver is driven.

In addition, the program counter 261 stores the program ROM 26
This is for addressing 3. The address of the program ROM 263 is specified by the address output from the program counter 261, and the corresponding program is read. The read program is temporarily stored in the instruction register 265 and then supplied to the decoder 251.

The decoder 251 includes an output register selection circuit 253 and an off circuit.
255. The output register selection circuit 253 decodes the output of the instruction register 265 to select one of the three bus drivers 211 to 215.
Create B and C. These selection signals are signals that become logic “1” when the corresponding bus driver is driven, and are supplied to the bus control circuit 231.

The OFF circuit 255 creates an OFF signal whose logic becomes “0” when switching the driving state of the bus driver. Assuming that data transmission by each of the bus drivers 211 to 217 corresponds to one cycle of the operation clock signal, for example, an OFF signal whose logic is set to “0” for a predetermined time from the rise of the operation clock signal is created. I do.

The bus control circuit 231 controls the output of the drive signal so that the logic of the drive signal supplied to all the bus drivers 211 to 217 does not become “0”. Bus control circuit 23
1 has four AND gates 241, 243, 245, 247 and a NOR gate 249.

The selection signal A output from the output register selection circuit 253 is input to one input terminal of the AND gate 241, and the off signal output from the off circuit 255 is input to the other input terminal. Similarly, the selection signal B is input to one input terminal of the AND gate 243, and the OFF signal is input to the other input terminal. And Gate 245
The selection signal C is input to one of the input terminals, and the OFF signal is input to the other input terminal.

The output of the NOR gate 249 is input to one input terminal of the AND gate 247, and the OFF signal is input to the other input terminal. Three selection signals A, B, and C are input to three input terminals of the NOR gate 249, respectively. When all the logics are "0", the output logic of the NOR gate 249 becomes "1".

Further, the output of the AND gate 241 is supplied to the bus driver 211 as a drive signal A. The drive signal A has a logic “1” only when the logic of the selection signal A output from the output register selection circuit 253 is “1” and the logic of the off signal output from the off circuit 255 is not “0”. This is the signal. Similarly, the output of the AND gate 243 is supplied to the bus driver 213 as a drive signal B, the output of the AND gate 245 is supplied to the bus driver 215 as a drive signal C, and the output of the AND gate 247 is supplied to the bus driver 217 as a drive signal H.
Supplied to

When all the logics of the three selection signals A, B, and C are “0”, the output logic of the NOR gate 249 becomes “1”, so that all the logics of the three drive signals A, B, and C become “1”. When it becomes "0", the logic of the drive signal H becomes "1".

In this way, any one of the bus drivers 211 to 217 is constantly driven, and the data held in the corresponding output registers 221 to 227 is transmitted to the internal bus 291.

The data sent to the internal bus 291 is
Each of the 275 is supplied and taken together. For example, the input register 271 receives data supplied from the internal bus 291 by the internal inverter 281. Similarly,
Input register 273 receives data by inverter 283, and input register 275 receives data by inverter 285.

FIG. 3 shows the operation timing of the embodiment. In the figure, "clock" indicates an operation clock signal, and each component operates in synchronization with the operation clock signal. “Output register selection” is the output register selection circuit 253
, The output state of the selection signal A, the output state of the selection signal B, the selection state of the selection scent C, and the shaded portions of the selection signals A and B. , C are not output. Further, “OFF signal” indicates a signal output from the OFF circuit 255, and “drive signals A, B, C, H” indicate signals output from the AND gates 241, 243, 245, and 247, respectively.

As shown in FIG. 3, in synchronism with the rise of the operation clock signal, the operation of generating the selection signal by the output register selection circuit 253 and the operation of generating the off signal by the off circuit 255 are performed. The OFF signal has a logic “0” for a predetermined time after the operation clock signal rises, and all drive signals
The logic of A, B, C, H is "0" only during this short time.

Therefore, two or more of the bus drivers 211 to 217 are not driven at the same time, and an excessive current flows through the CMOS in the two bus drivers having different output logics and an element due to heat generated by the excessive current. Degradation can be prevented.

When all the logics of the three drive signals A, B, and C are “0” and the output terminals of the three bus drivers 211, 213, and 215 are in a high impedance state, the drive signal H output from the AND gate 247 is output. Is supplied to the bus driver 217, and the contents of the output register 227 are sent to the internal bus 291.

Therefore, in each cycle of the operation clock signal, any one of the four bus drivers 211 to 217 is always driven, and the input terminals of the inverters 281 to 285 in the input register are in the open state for a long time. Thus, it is possible to prevent an excessive current from flowing through the pMOSFET and the nMOSFET constituting the CMOS and prevent the element from deteriorating due to heat generated by the excessive current.

In particular, in an LSI that combines the analog processing unit and the DSP as described above, noise generated by the occurrence of excessive current in the DSP is amplified by the analog processing unit. Can be realized.

In the above-described embodiment of the present invention, the control of the internal bus in the DSP has been described. However, the control of the internal bus in another processor such as a microprocessor or the system in the case where these processors are connected to the system bus is described. The present invention can be applied to bus control.

In the embodiment, when the logics of the three selection signals A, B, and C are all "0", the logic of the drive signal H is set to "1" and the contents of the output register 227 are sent to the internal bus 291. However, the output registers 221-225 are controlled by the bus driver 217.
May be selected. In this case, since the purpose is not to put the internal bus 291 into the released state, the content of the data to be transmitted may be any.

Furthermore, in the embodiment, the drive signal H is generated by determining the logic of the three selection signals A, B, and C by the NOR gate 249, but the three selection signals A are output by the decoding operation of the output register selection circuit 253. , B and C may be generated as a selection signal H whose logic becomes “1” when all the logics are “0”, and input to one end of the AND gate 247.

〔The invention's effect〕

As described above, according to the first aspect of the present invention, the second bus driver that transmits data when the determination unit determines that all of the plurality of first bus drivers that transmit data are not driven. To prevent the receiving end of the data receiving means, which receives data with the complementary MOS, from being left open for a long time.
In this case, an increase in power consumption and deterioration of the element due to heat generation can be prevented.

According to the second aspect of the present invention, a plurality of bus drivers are driven one at a time, data is sent to the bus via the driven one bus driver, and the off signal output from the off signal output means is output. In a state where a drive signal is supplied to a certain bus driver by a signal, it is prohibited to supply the drive signal to the next bus driver to be driven, and two bus drivers whose switching is successively driven are simultaneously driven. In other words, by preventing the simultaneous driving of the two bus drivers at the time of switching, it is possible to prevent an increase in power consumption in the complementary MOS on the data output side and deterioration of the element due to heat generation.

[Brief description of the drawings]

 FIG. 1 is a block diagram of the principle of the invention described in claim 1, FIG. 2 is a configuration diagram of an embodiment of the invention described in claim 1, FIG. 3 is an operation timing diagram of the embodiment, and FIG. FIG. 5 is an explanatory diagram of a CMOS inverter. In the figure, 110 and 150 are buses, 111 is data receiving means, 121 is a first bus driver, 131 is a judging means, 141 is a second bus driver, 151 is a bus driver, 161 is a switching signal creating means, and 171 is a driving signal control means. , 211,213,215,217 are bus drivers, 221,223,225,227 are output registers, 231 is a bus control circuit, 241,243,245,247 is an AND gate, 249 is a NOR gate, 251 is a decoder, 253 is an output register selection circuit, 253 is an off circuit, 261 is a program counter, and 263 is a program. ROM, 265 is an instruction register, 271,273,275 are input registers, 281,283,285 are inverters, and 291 is an internal bus.

Claims (2)

(57) [Claims] A data supplied through a bus is supplied to a complementary MO.
Data receiving means received by S, a plurality of first bus drivers for sending data to the bus according to the drive signals supplied to each, and a determination that all of the plurality of drive signals are not supplied And a second bus driver that sends data to the bus when all of the plurality of drive signals have not been supplied, based on the determination result of the determination unit. A bus control method characterized by the following. 2. A plurality of bus drivers for transmitting data to a bus by a complementary MOS in response to a drive signal, and signal periods for the plurality of bus drivers are allocated in a time-series manner. A selection signal is assigned to each of the remaining bus drivers except for one of the bus drivers, and during any signal period in the time series, at a time, the selection signal is temporarily assigned to the remaining bus drivers. One is selected, a selection signal at a first signal level is output during a signal period corresponding to the selection (hereinafter, referred to as a selection signal period), and a bus driver that is not selected outputs the selection signal during the selection signal period. Signal generating means for outputting a non-selection signal at a second signal level during the period, and a signal period start time of the signal period in the time series regardless of whether the selection signal is output by the selecting signal generating means. The first signal level from the time when the predetermined time has elapsed to the time before the signal period end time by the predetermined time, and the predetermined time from the signal period end time in each signal period. An off signal output unit that outputs an off signal at a second signal level from a previous time to a lapse of a predetermined time from the signal period start time of the next signal period of the signal period; A drive signal is supplied to the bus driver corresponding to the selection signal during the selection signal period in response to the selection signal output from the signal generation means and the off signal output from the off signal output means, and any of the signals not selected is selected. And supplying a drive signal to one of the plurality of bus drivers in response to a non-selection signal and an off signal during the selection signal period also generated for the bus driver. Bus control system, characterized in that which is configured by providing a bus driver control unit that.