JP2569759B2 - Nonvolatile random access semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile random access semiconductor memory, and more particularly to a non-volatile random access semiconductor memory which can hold data for a long time and is used as a storage element for a computer capable of rewriting data. The present invention relates to a nonvolatile random access semiconductor memory.

[Conventional technology]

Conventionally, various configurations of this type of semiconductor memory have been announced, but all require a large number of elements for the configuration of the semiconductor memory, or the process of storing information from the random access memory to the nonvolatile storage element and On the contrary, there is a disadvantage that the process of reading back the information stored in the nonvolatile storage element to the random access memory is complicated and difficult to use.

[Problems to be solved by the invention]

The present invention has been proposed in view of the above-mentioned problems of the related art, and has a small number of elements and a random access mode.
Storing information from the memory to the nonvolatile storage element and randomly accessing the information stored in the nonvolatile storage element
An object of the present invention is to provide a nonvolatile random access semiconductor memory which can be performed in a short time without requiring a complicated process in a process of reading back to a memory.

The present invention provides a dynamic random access memory having a smaller number of elements compared to a static random access memory.
By adding a nonvolatile storage element for data storage / reading to the access memory, it has an original content of realizing a nonvolatile random access semiconductor memory with a minimum number of elements.

[Means for solving the problem]

A nonvolatile random access semiconductor memory according to the present invention comprises a random number of a field effect transistor for address selection in which a drain is a digit line, a gate is an address selection signal line, and a capacitance element is connected between a source and a reference voltage. An access memory, having a floating gate type nonvolatile semiconductor memory element in which a control gate and a source are connected and a drain is connected to a voltage supply source, wherein the source and the floating gate type of the random access memory are A non-volatile random access semiconductor memory connected to the source of the non-volatile semiconductor storage element, wherein logic information stored in the floating gate type non-volatile storage element is read into the random access memory; The address selection transistor when conducting The digit line and the voltage supply are brought to a first logic level, and then the address selection transistor is turned off, and then the voltage supply is brought to a second logic level. is there.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a nonvolatile memory element used in an embodiment of the present invention.
Has an N-type drain region 2 and an N-type source region 3, and further has a silicon oxide film 4 and a control gate 6 thereon. In the silicon oxide film 4, a floating gate 5 for charge storage is provided. A portion 7 is a portion where the drain region 2 and the floating gate 5 overlap, and is a particularly thin silicon oxide film.

Figure 2 is a diagram showing the characteristics of the nonvolatile memory device shown in FIG. 1, the horizontal axis represents the potential V _CG of the control gate and the vertical axis to the drain and grounding the source of the nonvolatile memory element It shows the current flowing between the drain and source when a constant voltage is applied. In FIG. 1, when the control gate 6 is grounded and a high voltage is applied to the drain 2, a strong electric field is generated in the thin oxide film portion 7 from the drain 2 to the floating gate 5, and holes are generated in the floating gate 5. Is injected into. As a result, an inversion layer is easily formed on the surface of the silicon substrate 1, and as shown by the curve 21 in FIG. 2, even when the control gate voltage _VCG becomes zero, the current I _R
Flows, that is, the threshold voltage becomes negative. This is referred to as erasing, for example. On the other hand, the state opposite to erasing, that is, writing, can be realized by applying a high voltage to the control gate 6 and grounding the drain 2. That is, by taking the above-described potential relationship, a strong electric field is generated from the floating gate 5 toward the drain 2 in the thin oxide film portion 7, and electrons are injected into the floating gate.
Is hardly inverted, and the threshold voltage becomes a high positive value as shown by a curve 22 in FIG. When stored data is read out of the nonvolatile memory element applies a low positive voltage V _R than the threshold voltage after writing to the control gate as shown in Figure 2. If the nonvolatile memory element is in the erased state, it conducts and the control gate
Applied also can be obtained a current of I _R and, in a state of non-conduction If in written state. Specifically, in the present invention, when +4 V is applied to the source and the control gate of the nonvolatile memory element and the drain is set to 0 V in the read-back state, the nonvolatile memory element conducts and the source and the control gate become conductive in the erased state. The potential becomes 0 V, which is the same potential as the drain. In the write state, the nonvolatile memory element is non-conductive, and the potentials of the source and control gate maintain 4V.

The nonvolatile memory element described above is, for example, Electronics
An example applied to an EEPROM (Electrically Erasable Programmable Read Only Memory) is known from the publication February 28, 1980, pp. 113-117.

FIG. 3 shows a nonvolatile random access memory according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of an access / semiconductor memory. In FIG. 3, the present embodiment considers a case where the nonvolatile random access semiconductor memory has a 2-bit configuration. Each memory is connected to a digit line DL, and each memory is configured as follows. The first memory is a drain to the digit lines DL, a gate X decoder output, a source connected to the address selection IGFETMa _i connected to the output point V _i of the memory, a control gate and a source connected in common to V _i The non-volatile semiconductor memory element Mc _i having a drain connected to the write signal V _W and a capacitor C _i connecting one to V _i and the other to V _S (0V).
And The other one-bit memory is similarly constituted by storage elements Ma _j , Mb _j , and C _j .

 Next, the operation of the embodiment will be described.

4 and 5 show voltage supply sources V _CC , V _W and digit line voltage V _DL , X decoder output X _i , for explaining one embodiment of FIG.
6 is a timing chart of X _j and output points V _i , V _j of each memory. 4 and 5, t ₁ and t ₂ are the read state periods of the random access memory, t ₃ , t ₄ , t ₅ , and t ₆ are the write state periods of the random access memory, and t ₉ is the random access memory. storage period information from the access memory to the nonvolatile memory element, t ₁₁ is cut-off period of the voltage supply means _{V CC, t 12, t 13} ,
t _14, t ₁₅ shows a readback to time information stored in the nonvolatile memory element in the random access memory. First, the read / write operation of the random access memory will be described. Since both the storage elements Mc _i and Mc _j are set to “off”, they operate in the same manner as a dynamic RAM (random access memory) that is generally widely used. The detailed description is omitted here, but the outline is as follows. Capacitive element C _i, IGFETMa _i or M for selecting the amount of charge stored in C _j
aj is turned “on” to change the digit line potential _VDL, and the amount of this potential change is read by a sense amplifier to read information (presence or absence of charge). Write operation corresponds to the write signal.
_VDL is set and a potential of 4 V or 0 V is stored in the capacitance elements C _i and C _j (t _{1 to} t ₆ ). At this time, the memory is selected at the “High” level of the X decoder output. For example, when X _i = “High”, the IG is selected.
FETMa _i is "on" to select a memory element Mc _i, capacitive element C _i.

Next storage period t the connection points in ₉ of information from the random access memory to the nonvolatile memory element operates as follows. First, it is assumed that both X _i and X _j are set to 0 V, and at this time, the output points V _i and V _j hold 4 V and 0 V, respectively. Next, V _W is increased from 0V to 2
Changing to 0V to the drain in the nonvolatile memory element Mc _i + 20V, the potential difference between the applied + 4V to the source and the control gate drain and the control gate becomes 16V, allowing erasing the above potential difference 17V storage elements M
C _i is not erased, and V _TM (threshold voltage of the nonvolatile memory element) holds + 6V. On the other hand, the storage element Mc
_{In j} , since the drain becomes +20 V and the control gate and the source both become 0 V, the potential difference between the drain and the control gate becomes 20 V, erasing is realized, and _VTM changes from +6 to -6 V.

When in this manner is changed to 20V and V _W from 0V, the memory information 0V to hold, perform either operation of the nonvolatile memory element or not to erase collectively erased in response to 4V.
After the storage of the information in the nonvolatile memory element is completed in this way, even if the voltage supply means is dropped and cut off and the random access memory cannot hold the information, Information is stored and retained. This state period of cut-off period t ₁₁ of the voltage supply means.

Next, the information stored in the nonvolatile storage element is
Think about the period t ₁₂ ~t ₁₅ read back to the access memory. At the same time as the voltage source V _CC recovers from 0 V to 5 V, first, V _W rises from 0 V to 5 V, and then X _i and X _j are both 5 V from 0 V.
Stand up to V. Next, when the 5V digit line voltage V _DL from 0V, the output point V _i, V _j are both charged from 0V to 4V C _i, charge is stored in the C _j. Then X _i, and to 0V X _j both from 5V IGFETMa
_i, and to "off" Ma _j, the output V _i, after separation in the circuit of V _j from the digit lines DL, which is connected to V _W from 5V when the 0V non-conductive is a storage element Mc _i V _i holds 4V but, V _j which are connected to the storage element Mc _j is the passing state is discharged to 0V from 4V by the current path from the source to the drain of the Mc _j.

V _i is 4V by such a series of read-back operation, V _j is 0V
And V _i and V _j coincide with the potential of the memory output point before being stored in the nonvolatile storage element. Thus, the information stored in the nonvolatile storage element is read back to the random access memory. As described above, according to the present invention, information can be easily stored in and read back from the non-volatile storage element, and the number of elements to be configured is small.

The Mc _i, collective writing of Mc _j is, 0V to V _S prior to storing
The voltage V _i , V _j is increased to a high voltage via the capacitance elements C _i , C _j to generate a potential difference between the control gate and the drain. At this time, since the data at each memory output point may be destroyed at the time of writing, it is necessary to hold the data in a separate latch circuit. After the writing is completed, the data is written from the latch circuit to the output point of the memory.

FIG. 6 is a circuit diagram showing another embodiment of the present invention. In FIG. 2, when the drain signals of the nonvolatile memory elements Mc _i and Mc _j are set to V _CW and V _{CW is set} to 5 V in the read / write state of the random access memory, the write of the nonvolatile memory element is performed at 0 V _VTM. This is advantageous in that the writing time can be reduced. On the other hand, in one embodiment of the present invention, writing requires _VTM to be +6 V or more.

〔The invention's effect〕

As described above, the present invention has an effect that the number of constituent elements of the nonvolatile random access semiconductor memory can be reduced and the operation of storing and reading back information can be easily performed.

[Brief description of the drawings]

1 is a sectional view showing a nonvolatile memory element used in an embodiment of the present invention, FIG. 2 is a view showing characteristics of the nonvolatile memory element in FIG. 1, and FIG. 3 is an embodiment of the present invention. Circuit diagram showing a nonvolatile random access semiconductor memory according to the fourth,
FIG. 5 is a timing chart for explaining the operation of the circuit of one embodiment of the present invention, and FIG. 6 is a circuit diagram showing a nonvolatile random access semiconductor memory according to another embodiment of the present invention. Ma _i , Ma _j address selection IGFETs, Mc _i , Mc _j ... Nonvolatile semiconductor memory elements, C _i , C _j .

Claims (2)

(57) [Claims] A random access memory comprising an address selection field effect transistor having a drain connected to a digit line, a gate connected to an address selection signal line, a capacitor connected between a source and a reference voltage, and a control gate. And a source connected to the floating gate type nonvolatile semiconductor storage element having a drain connected to a voltage supply source, and the source of the random access memory and the source of the floating gate type nonvolatile semiconductor storage element. And a nonvolatile random access semiconductor memory connected to the floating gate type nonvolatile memory element, wherein when reading the logical information stored in the floating gate type nonvolatile memory element into the random access memory, the address selecting transistor The digit line and the power supply A non-volatile random access semiconductor memory, wherein the voltage source is set to a second logic level after the source is set to a first logic level and then the address selection transistor is turned off. . 2. A random access device comprising a field effect transistor and a capacitor between a digit line and a voltage supply.
In a nonvolatile random access semiconductor memory in which a memory and a floating gate type nonvolatile storage element are connected in series, when reading information stored in the nonvolatile storage element back to the random access memory, After the field effect transistor is turned on to charge the capacitance to the first logic level applied to the digit line and the power supply, the field effect transistor is turned off before the second voltage is applied to the voltage supply. A non-volatile random-access memory characterized by supplying a logic level potential of
Access / semiconductor memory.