JP2570107B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit in digital radio communication using a multilevel quadrature amplitude modulation system.

[0002]

2. Description of the Related Art Conventionally, in digital radio communication in which data is transmitted using a multilevel quadrature amplitude modulation system, a synchronization signal is periodically inserted into a data string to be transmitted, and the reception side detects the synchronization signal and transmits the signal. A method of detecting a frame, which is a unit of, has been proposed. FIG. 3 is a block diagram of a conventional frame synchronization circuit that performs frame detection by such a method.

[0003] Reference numeral 11 denotes a multiplying unit, on the receiving side of which a carrier wave is detected by a detector (not shown) and a complex baseband signal sample-quantized by an A / D converter of a demodulator (not shown) is inputted. The amplitude of the complex baseband signal is calculated. Numeral 12 denotes a synthesizing unit for adding amplitude data of three consecutive symbols (three data) sequentially output from the multiplying unit 11, and 12a denotes an amplitude data of 1 in the synthesizing unit 12.
A delay circuit for delaying the output of the delay circuit 12a by one symbol,
12c is the output of the delay circuits 12a and 12b and the multiplication unit 11
An adder 13 for adding the amplitude data output from the synthesizing unit 12, and a determining unit 13 for detecting a synchronization signal based on the output of the synthesizing unit 12 and a preset threshold value.

[0004] The synchronization signal inserted into the transmission data in this method has the maximum amplitude that the data can take,
It is inserted in three consecutive symbols. Next, the operation of such a frame synchronization circuit will be described. The multiplication unit 11
By multiplying the input complex baseband signal by a signal generated in the multiplier 11 and having a complex conjugate thereof (for example, a-bi is a complex conjugate for a complex function represented by a + bi), the complex baseband signal is multiplied. The amplitude of the band signal is calculated for each symbol and output to the combining unit 12.

[0005] Then, the synthesizing unit 12 adds the amplitude data of three consecutive symbols sequentially output from the multiplying unit 11. That is, the input amplitude data is delayed by the symbol interval T by the delay circuit 12a in the synthesis unit 12, and the result is further delayed by the symbol interval T by the delay circuit 12b. Then, 1 from the delay circuit 12a is output.
The amplitude data before the symbol, the amplitude data two symbols before from the delay circuit 12b, and the current amplitude data from the multiplication unit 11 are added by the adder 12c, and the added data is output to the determination unit 13.

Next, the determination section 13 compares the addition data output from the synthesis section 12 with a preset threshold value to determine whether or not the signal is a synchronization signal. If the signal is determined to be a signal, a frame detection signal is output. That is, since the synchronization signal has the maximum amplitude that the data signal can take and the data signal has a random amplitude, the synchronization signal can be detected from the result of adding the amplitude data. Further, the output of the synthesizing unit 12 is added for each frame interval, and an average is obtained, whereby the accuracy of detection can be improved. (For details, see Sunaga and Sanbe: Characteristics of 16QAM modem for land mobile communication, IEICE Transactions B-II Vol. J73-B-II No. 1 pp.
(See 1-9)

[0007]

The conventional frame synchronization circuit is configured as described above, and the synchronization signal is detected using the signal amplitude data as it is. If the intensity fluctuates randomly, there is a problem that the amplitude of the received data fluctuates and a synchronization signal cannot be detected. An object of the present invention is to provide a frame synchronization circuit capable of establishing stable frame synchronization even if a reception level fluctuates due to fading generated in a propagation path.

[0008]

SUMMARY OF THE INVENTION The present invention provides a method for receiving
Between two consecutive baseband signals from the subband signal
A correlation section for calculating correlation data, and sequentially output from the correlation section
Combined by adding N-1 continuous data
A combining unit for outputting data, and a
Set in advance based on the synthesized data and the synchronization signal before modulation.
And a determination unit for comparing with the determined reference combined data to detect a synchronization signal. Also, the correlation unit (1)
Is a delay circuit (1a) for delaying the input complex baseband signal by one symbol, and dividing the complex baseband signal delayed by one symbol by the delay circuit by one symbol by the currently input complex baseband signal. The synthesizing unit (2) receives the correlation data output from the correlation unit and delays it by one symbol by the delay circuit (2).
a), an adder (2b) for adding the correlation data one symbol before and delayed by the delay circuit to the current correlation data
It consists of and.

[0009]

According to the present invention, correlation data between two consecutive signals is calculated from a signal input by the correlation unit, and a predetermined number of continuous correlation data sequentially output from the correlation unit is calculated by the synthesis unit. They are added and averaged. Then, the determination section determines whether or not the signal is a synchronization signal based on the combined data output from the combining section and the preset reference combined data, and outputs a frame detection signal when the signal is determined to be a synchronization signal.

[0010]

FIG. 1 is a block diagram of a frame synchronization circuit showing one embodiment of the present invention, FIG. 2A is a diagram showing an example of an arrangement of synchronization signals on the transmission side, and FIG. FIG. 3A is a diagram showing a complex baseband signal obtained on the receiving side by transmitting the signal of FIG. In FIG. 1, reference numeral 1 denotes a correlator for calculating correlation data between two consecutive complex baseband signals from an input complex baseband signal, and 1a denotes a complex baseband signal input to the The delay circuit 1b for delaying by the symbol is a divider that calculates the correlation data by dividing the complex baseband signal one symbol before output from the delay circuit 1a by the current complex baseband signal.

Reference numeral 2 denotes a synthesizing unit for performing complex addition of two consecutive correlation data output from the correlator 1 and averaging them, and outputting the resultant data as synthesized data. A delay circuit for delaying one symbol,
2b is an adder for adding the correlation data one symbol before output from the delay circuit 2a and the current correlation data output from the correlation unit 1, and 3 is a preset combination with the synthesized data output from the synthesis unit 2. This is a determination unit that compares the reference combined data to determine whether the data is a synchronization signal.

In FIG. 2, Di is a complex data signal (i = 1, 2,...) Generated from transmission data by an external circuit (not shown) in order to perform transmission by multi-level quadrature amplitude modulation.
..), Ai is a complex synchronization signal similarly generated from the synchronization signal in the transmission data, and Sj is a result of multilevel quadrature amplitude modulation performed on the complex data signal Di and the complex synchronization signal Ai. The obtained complex baseband signal (j =
1, 2,...).

Next, the operation of such a frame synchronization circuit will be described. The correlation unit 1 performs two consecutive complex baseband signals Sj from the input complex baseband signal Sj.
The correlation data between them is calculated as follows and output to the synthesis unit 2. First, the delay circuit 1a in the correlation unit 1 delays the complex baseband signal Sj by the symbol interval T. Next, the divider 1b calculates the correlation data by dividing the complex baseband signal Sn-1 one symbol before input to the delay circuit 1a and delayed by the current complex baseband signal Sn as in the following equation. I do.

Cn = Sn-1 / Sn (1) where Cn is correlation data.

The synthesizing unit 2 performs complex addition on two consecutive correlation data Cn sequentially output from the correlating unit 1 and averages them, and uses this synthesized data as synthesized data as a determination unit 3.
Output to That is, the delay circuit 2a in the synthesis unit 2
The correlation data Cn is delayed by the symbol interval T. Then, the adder 2b performs a complex addition of the correlation data Cn-1 one symbol before output from the delay circuit 2a and the current correlation data Cn output from the correlation unit 1 as in the following equation.

Yn = Cn-1 + Cn (2) where Yn is synthetic data.

Next, the judging unit 3 compares the synthesized data Yn output from the synthesizing unit 2 with reference synthesized data (reference vector) set in advance as shown in the following equation to judge whether or not it is a synchronization signal. . R = (A1 / A2) + (A2 / A3) (3) where R is reference combined data. That is, the reference combined data R is a complex synchronization signal A as shown in FIG.
1, A2, and A3 are obtained by performing the same calculations as Expressions (1) and (2).

If the difference between the combined data Yn and the reference combined data R is smaller than a preset range, the complex baseband signals Sn-2, Sn at this time are determined.
It determines that n-1 and Sn are synchronous signals and outputs a frame detection signal. By performing such a determination for each symbol of the complex baseband signal Sn, the position of the synchronization signal can be detected.

Therefore, it is considered that the degree of the effect of fading is not so different between two consecutive received signals. Therefore, by taking a correlation between two consecutive received signals, the influence of the reception level fluctuation due to fading can be reduced. The synchronization signal can be detected without receiving it.

Although the embodiment of FIG. 1 has been described with respect to a case where three consecutive synchronization signals are inserted in one frame, the same applies to the case where N consecutive synchronization signals are inserted. (N-1) pieces of correlation data Cn, which is a predetermined number of
By comparing with, the frame synchronization can be detected.

[0021]

According to the present invention, since a frame is detected by calculating a correlation between two consecutive signals, a stable frame synchronization is established even if the reception level fluctuates due to fading generated on the propagation path. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame synchronization circuit showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an arrangement of synchronization signals on a transmission side and a diagram illustrating a complex baseband signal obtained on a reception side.

FIG. 3 is a block diagram of a conventional frame synchronization circuit.

[Explanation of symbols]

 Reference Signs List 1 correlation unit 1a delay circuit 1b divider 2 synthesis unit 2a delay circuit 2b adder 3 determination unit

Claims (2)

(57) [Claims] 1. A continuous N having a correlation with each other
This signal is transmitted by modulating a signal sequence into which synchronization signals are periodically inserted.
Used for communication to send, the receiving side detects the synchronization signal
In a frame synchronization circuit that performs frame detection, two consecutive baseband signals are received from a received baseband signal.
A correlation unit for calculating correlation data between the AND signals, and N-1 consecutive correlations sequentially output from the correlation unit.
A combining section for adding the data and outputting the combined data, and a synchronizing signal before modulation with the combined data output from the combining section.
With reference synthetic data set in advance based on the
A frame synchronization circuit comprising: a determination unit for comparing and detecting a synchronization signal. 2. The communication system according to claim 1, wherein the correlating unit converts the input complex baseband signal into one
And a delay circuit that delays
Input the complex baseband signal one symbol before
And a divider for dividing by the complex baseband signal
The synthesizing unit calculates the correlation data output from the correlation unit.
A delay circuit for inputting and delaying one symbol, and this delay
One-symbol previous correlation data delayed by the circuit and the current phase
And an adder for adding the related data.
Frame synchronization circuit.