JP2570296B2 - Charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a CCD (charge coupled device).
The present invention relates to a charge transfer device such as an image sensor.

[Summary of the Invention]

According to the present invention, in a charge transfer device, a clock voltage whose rising and falling times are slower than a clock voltage applied to a last bit transfer unit is applied to a bit transfer unit in a transfer register unit preceding the last bit transfer unit. The dynamic range of the transfer unit can be greatly increased.

[Conventional technology]

In the CCD image sensor, a two-phase driving horizontal transfer register is configured as shown in FIG. That is,
For example, a plurality of transfer electrodes (3) are arranged and formed in a transfer direction on a silicon semiconductor substrate (1) via an insulating film (2).
Adjacent electrodes (3) are connected to each other to form a multi-bit charge transfer section (4) including a transfer section and a storage section.
[(4 ₁ ), (4 ₂ ), (4 ₃ )}] are formed, and the electrodes (3) of one and the other transfer parts (4) are commonly connected to each other, and the fifth electrode is connected to the fifth electrode. clock voltages phi _H1 and phi _H2 of the same waveform shown in FIG. given, the clock voltage phi _H1 and phi
Driven by _H2 . The subsequent transfer of the last bit (4 _1), by forming a gate electrode (5) via an insulating film on a substrate (1) (2). A horizontal read gate section (6) is formed.

[Problems to be solved by the invention]

In the horizontal transfer register section, the dynamic range of the transfer section (4 ₁ ) of the last bit is different from the transfer sections (4 ₂ ), (4 ₃ ), and ‥‥ of the other bits, and is different from that of the read gate section (6). It is determined by the potential difference between the potential and the storage section in the last bit transfer section (4 ₁ ). For this reason, conventionally, when the last bit transfer section (4 ₁ ) does not rise completely during the transfer from the preceding bit transfer section (4 ₂ ) to the last bit transfer section (4 ₁ ) (one point in the potential diagram of FIG. 6). (State indicated by chain line (7)) Pre-stage bit transfer unit (4 ₂ )
When a large signal charge (8) is transferred from the transfer gate (6), the charge (8 ') that cannot be completely accumulated in the transfer section (4 ₁ ) flows out beyond the read gate section (6). In other words, the transfer unit (4 ₁ ) for the last bit can store only signal charges smaller than the dynamic range obtained in principle. Further, in recent years, the amplitude of the horizontal transfer clock voltage has become smaller with the trend of low voltage power supply, so that the dynamic range of the last bit transfer section (4 ₁ ) has become insufficient.

Methods for increasing the dynamic range of the last bit transfer unit include (i) increasing the amplitude of the horizontal clock voltage,
(Ii) A method of increasing the channel length and channel width of the storage unit of the last bit transfer unit is considered. But,
The method (i) goes against the goal of reducing the required minimum amplitude of the horizontal clock voltage. In the method (ii), since the transfer from the last bit transfer section (4 ₁ ) to the read gate section (6) is deteriorated, it is necessary to lower the potential by setting the bias of the horizontal clock voltage to the negative side. But,
When the potential becomes shallow, a contradiction occurs that the dynamic range becomes small.

In view of the above, the present invention can increase the dynamic range of the last bit transfer unit without increasing the amplitude of the clock voltage or without increasing the channel length and channel width of the storage unit of the last bit transfer unit. A charge transfer device such as a CCD image sensor is provided.

[Means for solving the problem]

According to the present invention, in a transfer register section of a charge transfer device such as a CCD image sensor, a clock voltage supplied to a bit transfer section (4 ₂ ) preceding a final bit transfer section (4 ₁ ) is supplied to a final bit transfer section (4 ₁ ). Also provides a clock voltage with a slow rise and fall.

[Action]

Preceding bit transfer portion (4 _2), by which also the clock voltage applied to the last bit transfer section (4 ₁₎ gives the slow clock voltages rise and fall, the last bit transmitted from the preceding stage bit transfer section (4 ₂₎ parts during (4 ₁₎ of the signal charge to the transfer, the last bit transfer section (4 ₁₎ by the to the signal charges accumulated in the phenomenon decreases exiting beyond reading gate portion (6), resulting in a final The dynamic range of the bit transfer unit increases.

〔Example〕

Hereinafter, an example of a CCD image sensor according to the present invention will be described with reference to FIG. 1 and FIG.

FIG. 1 shows a two-phase driven horizontal transfer register section in a CCD image sensor. As in FIG. 4, for example, a plurality of transfer electrodes (for example, a silicon semiconductor substrate (1) are interposed via an insulating film (2)). 3) are arranged in the transfer direction, and the adjacent electrodes (3) are connected to each other to form a multi-bit charge transfer section (4) including a transfer section and a storage section.
[(4 ₁ ), (4 ₂ ), (4 ₃ )}] are formed, and the electrodes (3) of _every other transfer section (4 ₁ ), (4 ₃ ), (4 ₅ )} are formed. ) And every other transfer section (4 ₂ ), (4 ₄ ),
(4 ₆ ) The electrodes (3) of (1) are commonly connected to each other
t ₁ and t ₂ is derived. Transfer of the last bit (4 ₁₎ horizontal readout gate portion obtained by forming a gate electrode (5) through an insulating film (2) on the substrate (1) in the subsequent stage of (6) is provided.

Thus, in this embodiment, the terminal t ₁ and the final bit transfer section (4 ₁₎ of the electrodes (3) of the connection point and the transfer portion of the bits of the other one every other (4 _3), (4 ₅ ) ‥‥ electrode (3)
Common connections points interposing a series resistor R _S1 clocked voltage phi _H1 to the terminal t _1, the terminal t ₂ and transfer of the other every other bit (4 _2), (4 _4), ( 4 ₆₎ to the terminal t ₂ and through inserting a series resistor R _S2 between the common connection point of ‥‥ electrode (3) to clock voltage phi _H2. That is, when electrons are used as signal charges, the electrode (3) of the final bit transfer section (4 ₁ ) is provided on the electrode (3) of FIG.
As shown in FIG. 2, a clock voltage φ _H1 having a fast rising and falling time is applied, and the electrodes (3) of every other transfer section (4 ₃ ) and (4 ₅ )} on the other side are applied to FIG. As shown in the figure, a clock voltage φ _H1 ′ whose rising and falling is slower than that of φ _H1 is given by the series resistor R _S1 . Further, each transfer unit every other of the other (4 _2), (4 _4), phi a series resistor R _S2 similarly as shown in FIG. 2 C to the electrode (3) of (4 _{6) H1}
The clock voltage φ _H2 ′ whose falling and rising is slower than the rising and falling of the clock is supplied. Here, the series resistances R _S1 and R _S2 are electrode capacitances (substrate (1) and electrode (3)).
Capacitance between capacitance between is connected to the connected electrodes and the terminal t ₂ to the terminal t ₁ electrode) varies due transfer efficiency of the horizontal shift register section, for example, 10Ω longitudinal is good.

According to such a configuration, when transferring preceding bit transfer section (4 ₂₎ from the signal charge final bit transfer section (4 _1), in front of the bit transfer section (4 _2), the last bit transfer section (4 ₁₎ by providing the rising and falling slow clock voltage .phi.H ₂ 'than the clock voltages .phi.H ₁ to give the final bit transfer section (4 ₁₎ rises preceding bit transfer portion of the clock voltage .phi.H ₁ of (4 ₂₎ clock The voltage becomes earlier than the fall of the voltage φH ₂ ′, and the potential in the last bit transfer section to be stored in the last bit transfer section (4 ₁ ) shifts from the transfer state to the storage state earlier, so that the signal charges are read out by the read gate section ( The phenomenon that the dynamic range cannot be obtained because the dynamic range exceeds 6) is reduced.

That is, it is possible to increase or to increase the amplitude of the clock voltages, or the last bit transfer section (4 ₁₎ without expanding the channel length and channel width of the storage portion of the dynamic range of the last bit transfer unit.

Also, in this example, by inserting series resistors R _S1 and R _S2 in the electrodes other than the electrode of the last bit, the transfer unit (4 ₂ ),
(4 ₄ ), (4 ₆ ) ‥‥ electrodes and transfer sections (4 ₃ ), (4 ₅ ),
(4 ₇₎ can be made the same load ‥‥ electrode.

FIG. 3 shows another example of the present invention. In this example, a resistor R _S2 is inserted only in the electrode (3) of the preceding bit transfer section (4 ₂ ), and is applied to the preceding bit transfer section (4 ₂ ). The falling of the clock voltage φ _H2 ′ is configured to be relatively slower than the rising of the clock voltage φ _H1 applied to the final bit transfer section (4 ₁ ). Also in this configuration, it is possible to increase the dynamic range of the last bit transfer unit as in the above example.
In the above example, the present invention is applied to a CCD image sensor using electrons as signal charges. However, the present invention is also applicable to a CCD image sensor using holes as signal charges. In this case, when the clock voltage falls, the potential of the transfer section is in an accumulation state, and the phase of the clock voltage is opposite to that of FIG. 2, and therefore, the final bit transfer section (4 ₂ ) eggplant to provide a relatively slowly rising clock voltage from the falling edge of the clock voltage applied to the bit transfer section (4 _1).

Accordingly, the amplitude of the clock voltage applied to the horizontal register section is reduced in accordance with the trend toward low voltage power supply.
It is suitable for application to a CCD image sensor.

〔The invention's effect〕

According to the present invention, by configuring the transfer register unit to apply a clock voltage that rises and falls slower than the clock voltage applied to the final bit transfer unit to the bit transfer unit preceding the final bit transfer unit,
The dynamic range of the last bit transfer unit can be greatly increased without increasing the amplitude of the clock voltage or expanding the channel length and channel width of the storage unit of the last bit transfer unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a horizontal transfer register section of a CCD image sensor according to the present invention, FIGS. 2A to 2C are clock voltage waveform diagrams according to the present invention, and FIG. 3 shows another example of the present invention. 4 and 5 are a configuration diagram of a horizontal transfer register section of a conventional CCD image sensor and a clock voltage waveform diagram thereof, and FIG. 6 is a potential diagram for explaining a conventional example. (1) is a semiconductor substrate, (2) is an insulating film, (3) is a transfer electrode, (4) [(4 ₁ ), (4 ₂ ), (4 ₃ )}] is a transfer section,
R _S1 and R _S2 are resistors.

Claims (1)

(57) [Claims] 1. A charge transfer device according to claim 1, wherein a clock voltage which rises and falls slower than a clock voltage applied to said last bit transfer unit is applied to a bit transfer unit preceding said last bit transfer unit in said transfer register unit. apparatus.