JP2570331B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] According to the present invention, when an electrode layer is formed by lamination through an insulating layer, traps are reduced in the insulating layer and traps are less likely to occur. The present invention relates to a semiconductor device and a method of manufacturing the same.

[Prior art] For nonvolatile memories such as EPROM and E ² ROM, for example,
A floating gate electrode is formed on the surface of a silicon semiconductor substrate via an insulating layer of a silicon oxide film, and a control gate electrode is formed on the floating gate electrode via an insulating layer of a silicon oxide film. I have.

In such a semiconductor device, traps are likely to be induced due to damage such as dry etching performed during the manufacturing process, for example, and traps are likely to be induced in the insulating layer. comes to, EPROM, in the E ² ROM or the like is as charge retention characteristics of the data is deteriorated, it is difficult to improve the reliability of the memory.

[Problems to be Solved by the Invention] The present invention has been made in view of the above points. For example, traps are generated in an insulating layer around an electrode layer such as a semiconductor substrate of an EPROM or E ² PROM and a floating gate electrode. A semiconductor device in which the reliability of operation characteristics is reliably obtained by reducing the number of traps and making it difficult for traps to be induced;
It is another object of the present invention to provide a method for manufacturing such a semiconductor device.

[Means for Solving the Problems] That is, in the semiconductor device according to the present invention, when the electrode layer is formed on the surface of the semiconductor substrate via an insulating layer of an oxide film, the insulating layer Is formed in a three-layer structure in which a nitride layer is formed on both sides of the oxide film. For this purpose, after the oxide film layer is formed, a nitrogen-based reaction such as NH ₃ is performed. Rapid heating treatment in a gas to form a nitroxide layer on both surfaces of the oxide film, and form an electrode layer on a three-layer insulating layer having a nitroxide layer formed on both surfaces. Things.

[Operation] For example, if an EPROM and an E ² PROM are configured in this manner,
An oxide film between the floating gate electrode and the semiconductor substrate and an outer peripheral portion between the control gate gate electrode and the floating gate electrode are surrounded by an insulating layer having a three-layer structure in which a nitroxide layer is formed on both surfaces of the oxide film. As a result, the state where the number of traps is small and the state where the trap hardly occurs is brought about. Therefore, for example, the data charge retention characteristics are set stably, and the reliability of the operation characteristics of a semiconductor device such as an EPROM or an E ² PROM is effectively improved. The insulating layer having the three-layer structure as described above can be easily obtained by a rapid heating process in a nitrogen atmosphere of the oxide film layer portion. Such a semiconductor device is designed so that stable characteristics are set. It can be easily manufactured.

Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional structure of one storage element portion in an EPORM according to an embodiment of the present invention. In a P-well region portion of a silicon substrate 11, a drain region 12 is formed.
And a source region 13 are formed. An insulating layer serving as a tunnel oxide film is formed on the surface of the silicon substrate 11.
A floating gate electrode 15 made of polysilicon is formed with the interposition of. A control gate electrode 17 also made of polysilicon is further formed on the floating gate electrode 15 with an insulating layer 16 interposed therebetween, and the insulating layer 18 is formed so as to surround the floating gate electrode 15 and the control gate electrode 17. Is formed.

Here, each of the insulating layers 14, 16 and 18 is made of silicon oxide (SiO ₂ ) obtained by heat treatment in an oxygen atmosphere.
And silicon oxide films 141, 161 and 181.
181 and 181 are formed on both surfaces of a nitroxide layer (nitride oxide film) 142, 162 and 182, respectively, so that these insulating layers 14, 16 and 18 each have a three-layer structure. Is what it is.

On the silicon substrate 11, a BPSG layer 20 is formed so as to cover the above-mentioned electrode portion, and through the BPSG layer 20, a metal wiring 21 made of aluminum is formed from the drain 12 and the source 13 respectively. 22 have been taken out. 23 is passivation for protection.

FIG. 2 shows one of the above semiconductor devices, particularly EPROM.
The manufacturing process of one memory cell portion is sequentially shown. First, as shown in FIG. 2A, a field oxide film region is formed by a so-called LOCOS method in a P well formation region of a silicon substrate 11, An oxide film of SiO _{2 with} a thickness of 200 to 500 mm on such a silicon substrate 11
Form 31. On this oxide film 31, 1000 to 20
A silicon nitride (Si ₃ N ₄ ) layer 32 of 00 ° was formed, and the pattern shape was set by photolithography and etching. And this silicon nitride layer
Boron ions are implanted into the silicon substrate 11 using the mask 32 as a mask to form a P ⁺ channel stopper region 33. Further, in a steam at 1000 ° C., a field oxide of 0.5 to 1.5 μm as shown in FIG. The film 34 was formed.

The oxide film 31 and the silicon nitride layer 32 are removed in this state. In this state, a gate oxide film 35 of a silicon oxide film of 200 to 500 ° is formed as shown in FIG. 2C.

After the gate oxide film 35 is thus formed, the semiconductor substrate 11 is set in a nitrogen-based gas atmosphere and rapidly heated to thereby form the gate oxide film 35 as shown in FIG.
The nitroxide layers 351 and 352 are formed on both sides of the substrate.

Here, a method of forming the gate oxide film 35 having the nitroxide layers 351 and 352 formed on both surfaces will be described in detail. FIG. 3 shows a flow of a method of forming the gate oxide film 35 on the surface of the silicon substrate 11. First, the silicon substrate 11 is set in a processing chamber. A first step 51 of evacuation is performed. Then, when the processing chamber is evacuated to a vacuum state, a second step 53 for introducing a reaction gas such as H ₂ or HCl into the chamber is performed, and the temperature is raised by a third step 53, A poor-quality natural oxide film formed on the surface of the silicon substrate 11 in the air or by chemical treatment is removed. For example, in this step 53, a heat treatment is performed at 1150 ° C. for 60 seconds, and the temperature is lowered in a fourth step 54.

When the temperature in the chamber is reduced in this way, the inside of the chamber is evacuated and reduced in a fifth step 55, and O ₂ (oxygen) or O ₂ and HCl (hydrochloric acid gas) are introduced into the chamber in a sixth step 56. ) Is introduced. When the silicon substrate 11 in the chamber is set in an oxygen atmosphere in this manner, the temperature of the silicon substrate 11 in the chamber is increased in a seventh step 57, and the gate oxide film 35 is formed on the surface of the silicon substrate 11. A silicon oxide film is formed. Here, this process
The temperature raising process in 57 uses a heat source such as a halogen lamp or an arc lamp so that the temperature is rapidly raised, and a silicon oxide film is formed by rapidly oxidizing the surface of the silicon substrate 11. That is what we are trying to do.

When the gate oxide film of the silicon oxide film is formed on the surface of the silicon substrate 11 in this manner, the temperature in the chamber is lowered in an eighth step 58, and the chamber is evacuated and reduced in a ninth step 59. .

In the next tenth step 60, NH ₃ which is a nitrogen-based reaction gas is introduced into the chamber evacuated and evacuated,
In the eleventh step 61, the temperature of the silicon substrate 11 is rapidly increased by the rapid heating means using the halogen lamp or the arc lamp in a state in which the reaction gas is introduced, so that rapid nitriding (RTN) is performed. This nitriding step is performed by, for example, 115
Performed at 0 ° C. for 30 seconds.

After the nitriding step is performed in this manner, the temperature is reduced in a twelfth step 62, and nitrogen is introduced into the chamber in a thirteenth step 63 to remove the silicon substrate 11.

FIG. 4 shows a schematic configuration of an apparatus for performing the above-described processing.
11 is inserted and supported. Gas inlets 66 and 67 are formed in the chamber 65,
N ₂ is introduced from 66, and a reaction gas such as NH ₃ , O ₂ , H ₂ , Cl or the like is selectively introduced from the inlet 67. A discharge port 68 is further formed in the chamber 65, and the inside of the chamber 65 is selectively evacuated from the discharge port 68 by a vacuum pump (not shown).

A halogen lamp 69 is provided around the outer periphery of the quartz chamber 65.
Is provided. The halogen lamp 69 heats the silicon substrate 11 in the chamber 65 rapidly. Although not shown in detail, the heating temperature is observed by a temperature sensor in the quartz chamber 65, and the halogen lamp 69 is controlled so that the heating temperature is set to the target temperature state. I have to.

That is, as in the tenth step 60, the nitrogen-based reaction gas
By introducing NH ₃ into the chamber 65 and performing rapid nitriding in the next step 61, the gate oxide film 35 having the nitroxide layers 351 and 352 formed on both surfaces is obtained as shown in FIG. 2D. The structure is such that a silicon oxide layer exists between the nitroxide layers 351 and 352. Here, the rapid nitriding (RTN) step in the eleventh step 61 is appropriately performed at 1100 to 1250 ° C. for 30 seconds to 300 seconds. When the state of the nitroxide layer is confirmed by Auger analysis, The state was as shown in the figure. Here, a 105Å silicon oxide film was rapidly heated in NH ₃ at 1150 ° C to perform rapid nitriding (RTN).
In this case, it was confirmed that by adjusting the heating time, an oxide film layer having a three-layer structure having a nitroxide layer on both surfaces was formed. It has been confirmed that a similar three-layer structure can be obtained even when the thickness of the silicon oxide film is further increased. In such a case, the heat treatment temperature is further increased and the It is necessary to lengthen the time of the nitriding treatment by heating. In this figure, the interface is on the interface side between the gate oxide film 35 and the silicon substrate 11.

If the gate oxide film 35 having the nitroxide layers 351 and 352 on both surfaces is formed in this manner,
As shown in FIG. 2E, an N ⁺ type first polysilicon layer 36 is formed.
An oxide film layer 37 of silicon oxide is formed on the polysilicon layer 36 by thermal oxidation as shown in FIG. 2F. And
This oxide film layer 37 is subjected to rapid nitriding similarly to the case of the gate oxide film 35 so that the nitroxide layers 371 and 372 are formed on both surfaces thereof as shown in FIG. 2G.

After the oxide film 37 having the nitroxide layers 371 and 372 formed on both sides in this manner, the second polysilicon layer 38 having a thickness of 3000 to 5000 ° is formed thereon as shown in FIG. To form Then, in this state, the second polysilicon layer 38, the oxide film layer 37,
A portion of the first polysilicon layer 36 is etched away so that, for example, a floating gate and a control gate in the EPROM are cut out by the first and second polysilicon layers 36 and 38. And
As shown in FIG. 2I, a thermal oxide film 39 is formed on the outer peripheral portion of these gate groups, and as shown in FIG. Oxide layers 391 and 392 are formed. Then, a semiconductor device as shown in FIG. 1 is formed by forming a source, a drain, an interlayer insulating layer of BPSG, an aluminum wiring layer, and the like.

FIG. 6 shows that traps are reduced when the silicon oxide film layer has a three-layer structure having a nitroxide layer on both sides. This evaluation is based on the MOS diode structure and the FN current is used to evaluate the silicon oxide film. This is a measurement of the change in the gate voltage by injecting electrons into the inside, and a state in which the change in the gate voltage Vg is small means that the number of electrons or holes trapped in the silicon oxide film is small. become. That is, when the rapid nitriding time is 10 seconds and when the rapid nitriding time is 10 seconds and 30 seconds, the number of traps is sufficiently small.

It is considered that the cause of the decrease in the number of traps is that the strain bond, which is considered to be the cause of the trap of Si—O, is relaxed with the rapid progress of nitriding. That, in the case of only the silicon oxide film is one in which the stray bond distorted in the vicinity of the interface Si-SiO ₂ is present, formed on the nitrogen oxide film near the interface of the amount that by performing rapid nitriding It is considered that this reduces the strain at the interface and reduces the number of traps.

Therefore, with such a three-layer structure, for example, EPRO
If the gate oxide film layer and other insulating layers of the M and E ² PROMs are formed, the deterioration of the charge retention state will not be observed, and the threshold voltage will not be reduced even if data writing and erasing are repeated. This is a state that does not decrease.

FIG. 7 shows a short channel, for example, an N-channel MO.
In this embodiment, an S transistor is formed, and an insulating layer 72 made of a silicon oxide film formed on a silicon substrate 71 is provided on both surfaces.
22 is formed in a three-layer structure. Then, an electrode 73 made of polysilicon is formed on the insulating layer 72, and the outer periphery of the electrode 73 is formed on the insulating layer 74 made of an oxide film.
The insulating layer 74 also has a three-layer structure having nitroxide layers 741 and 742 on both sides.

That is, when composing the MOS transistors in this manner, Gm of deterioration due to hot electrons, and the change of V _T is a both very small state, good operation characteristics is now obtained.

[Effects of the Invention] As described above, in the semiconductor device according to the present invention,
An insulating film with few traps is formed, and an insulating film in which traps are unlikely to be formed is formed.For example, in a EPROM, an E ² PROM, etc., a decrease in threshold voltage is suppressed, and writing and erasing are performed. The operation characteristics are effectively improved, and the threshold level is stabilized when a MOS transistor is formed. Such an insulating film can be easily and effectively formed by a nitriding treatment by rapid heating using a halogen lamp, an arc lamp, or the like.

[Brief description of the drawings]

FIG. 1 is a view showing a cross-sectional structure of one storage element portion of an EPROM which is an example of a semiconductor device according to an embodiment of the present invention, and FIGS. FIG. 3 is a configuration diagram illustrating an example of a processing apparatus used in the process of forming an insulating film in the above manufacturing process. FIG. 5 is a curve diagram showing the result of Auger analysis of the insulating film portion. Figure 6 shows the gate voltage in relation to the rapid nitriding time.
FIG. 7 is a diagram showing a relationship between Vg and an electron injection amount, and FIG. 7 is a diagram showing a cross-sectional configuration of an N-channel MOS transistor according to another embodiment of the present invention. 11 ... silicon substrate, 14, 16, 18, ... insulating layer, 141, 1
61, 181: Silicon oxide film, 142, 143, 162, 163, 18
2,183 ... Nitride oxide layer, 15 ... Floating gate, 17 ... Control gate, 35,37,39 ...
Gate oxide films, 351, 352, 371, 372, 391, 392... Nitroxide layers, 36, 38... First and second polysilicon layers.

Claims (3)

(57) [Claims] A first oxide film formed on the semiconductor substrate; a floating gate electrode formed on the oxide film; a second oxide film formed on the floating gate electrode; And a control gate electrode formed on the second oxide film to form a non-volatile memory, wherein the first and second oxide films have a three-layer structure in which a nitroxide layer is formed on both surfaces thereof. A semiconductor device having a structure. 2. The semiconductor device according to claim 1, further comprising a nitroxide layer formed on both surfaces of the oxide film around the control gate electrode. A step of forming an oxide film layer on the surface of the semiconductor substrate; setting the semiconductor substrate on which the oxide film layer is formed in a nitrogen-based reaction gas atmosphere; Forming a three-layer insulating layer by rapidly heating for two seconds to form a nitroxide layer on both surfaces of the oxide film layer; and forming an electrode layer on the insulating layer. Manufacturing method of a semiconductor device.