JP2570919B2 - Integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit in which an input voltage is prevented from exceeding a power supply voltage to prevent fluctuations in characteristics and malfunctions.

[0002]

2. Description of the Related Art An integrated circuit is an integrated circuit having a plurality of functions. In this case, the voltage level of the input signal may be different in each circuit unit. For example, switch S
Circuit for detecting the on-off of W ₁₁ is shown in FIG. Here, the voltage V ₁₁ of the external power supply, for example, a battery voltage 12V in automotive. Further, the voltage V ₂₁ is the input voltage to the right of the integrated circuit 100 of the broken line in the figure, the voltage V _CC is the power supply voltage of the integrated circuit 100 (= 5V). FIG. 8 shows the structure of the integrated circuit 100 in FIG. Diode D ₁₁ in FIG 7 is formed by the P ⁺ layer (P type diffusion layer) 12 serving as an input terminal provided on the N substrate (N-type silicon substrate) 11 and its N substrate 11. The P ⁺ layer 12 is a first circuit unit, for example,
The inverter 13 is connected. Further, a P ⁺ layer 14 serving as another input terminal is provided on the N substrate 11 adjacent to the P ⁺ layer 12. The P ⁺ layer 14 is connected to an inverting input terminal of a comparator 15 as a second circuit unit. The comparison voltage V _ref of the formula is entered through the P ⁺ layer 14 which supply voltage V _CC is divided by resistors R21, R22 to the inverting input terminal of the comparator 15. _Vref = _Vcc × R21 / (R21 + R22) The output of an amplifier (not shown) is input to the non-inverting input terminal of the comparator 15.

[0003]

In this case, the N substrate 11
A parasitic transistor 16 having a PNP structure, which is an unintended transistor, is constituted by the P ⁺ layer 12 provided on the substrate and the adjacent P ⁺ layer 14. Then, the voltage V ₁₁ power supply voltage V
_When it becomes higher than _CC, the emitter of the parasitic transistor 16
The base is biased in the forward direction, and the P ⁺
Substrate 11 flows current I _D11 (the aforementioned diode D _11). As a result, the parasitic transistor 16 becomes conductive, the P ⁺ layer 12 and the P ⁺ layer 14 and becomes conductive, the external power source → the external resistor R11 → the P ⁺ layer 12 → N substrate 11 → P of the voltage V ₁₁
Unintended parasitic current I on the path from ⁺ layer 14 to resistor R21
_P will flow in. This parasitic current I _P changes the comparison voltage V _ref of the comparator 15 to a voltage (I _P × R21 × R22).
/ (R21 + R22)). That is, the threshold voltage of the comparator 15 increases, and the integrated circuit 10 connected to the comparator 15
There is a problem that the characteristics at 0 may fluctuate or malfunction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to prevent interference in a circuit portion without causing the above-mentioned parasitic current to flow and to prevent characteristic fluctuation. Another object is to provide an integrated circuit capable of preventing malfunction.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; and a first conductive region formed in common with one of the conductive regions connected to a power supply.
A and the second PN junction diode, the first circuit portion in which the first PN junction diode is inserted in parallel between the power source and the first input line, said second PN junction diode first 2 and a second circuit section inserted in parallel between the input line and the power supply.
In an integrated circuit which is higher than the power supply voltage fed to the second circuit portion through the resistor is introduced, said first circuit portion of the input voltage is the first PN junction diode
To ensure that the voltage does not exceed the
From the connection point between the resistor and the first PN junction diode
By bypassing the current through the resistor,
Causing the input voltage to rise to the high voltage
And a bypass circuit for lowering the power supply voltage .

[0006]

In the integrated circuit, the resistor and the first P are connected via a resistor so that the input voltage of the first circuit does not exceed the power supply voltage.
A bypass circuit is provided to bypass the input current from the connection point with the N-junction diode . So this bypass
The operation of the circuit controls the current flowing through the resistor,
Input terminal voltage forward biases the first PN junction diode
Even if the voltage exceeds the voltage to conduct.
Due to the voltage drop at the resistor, the potential at the connection point becomes the first PN junction
Do not exceed the voltage at which the diode is forward biased and turned on
So that it is kept.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to specific embodiments. FIG. 1 shows a CMOS (C) as an integrated circuit according to the present invention.
omplementary Metal Oxide Semiconductor: Complementary MO
S) is a circuit diagram showing the integrated circuit 10. T1 and T2 are p-channel MOS field effect transistors (p-ch MO
S3), and T3 is an n-channel MOS field effect transistor (n-ch MOSFET). R1,
R2 is a resistor provided inside the CMOS integrated circuit 10, and R3 is an external resistor provided outside the CMOS integrated circuit 10. Hereinafter, T1, T2, and T3 are simply referred to as transistors. Transistor T1 has source S1 side at power supply voltage V _CC
And the gate G1 side is connected to the gate G2 side of the transistor T2. The gate G1 side of the transistor T1 is connected to the drain D1 side, and is grounded via the resistor R1. Further, the substrate B1 of the transistor T1 is connected to the power supply voltage V _CC. Transistor T2
The source side S2 voltage V ₁ of the external power source through the external resistor R3 is powered. The drain D2 side of the transistor T2 is connected to the gate G3 side of the transistor T3 and is grounded via the resistor R2. The substrate B2 of the transistor T2 is connected to the power supply voltage V _CC. The side of the drain D3 of the transistor T3 is connected to the side of the source S2 of the transistor T2, and is also connected to an inverter circuit (input circuit), which is a first circuit (not shown) at the subsequent stage. The source S3 side and the substrate B3 side of the transistor T3 are grounded.

Next, the operation will be described. When the power supply voltage V _CC to the sources S1 of the transistor T1 is fed the substrate B1 side becomes the power supply voltage V _CC and the same potential, low because the source S1- gate voltage of the gate G1 side than the power supply voltage V _CC of the transistor T1 G1 is forward biased, and the transistor T1 is turned on, so that the source S1 and the drain D1
Current starts to flow in between. Then, the potential V ₃ of the drain D1 of the transistor T1 begins to rise by the resistor R1.
_Assuming that the power supply voltage V _CC is 5 V, the potential V ₃ is equilibrated at 3.5 V and is constant by appropriately setting the value of the resistor R 1. That is, the gate G2 of the transistor T2
The potential on the side is also constant at 3.5V.

Here, the voltage V ₁ of the external power supply is equal to the power supply voltage V
Is lower than the voltage V _a to be described later is lower than _CC transistors T2, T3 are both turned off, the voltage V ₁ of the said external power source is a voltage V ₂ of the input terminal of the CMOS integrated circuit 10 as it is (V ₁ = V ₂ ). Then, the voltage V ₁ is higher, the source S2- gate G2 between voltage threshold voltage of the transistor T2 V _TP (= 1.0V) than the larger voltage V
_{When the} voltage exceeds _a (= 4.5 V), the transistor T2 is turned on. Then, the transistor T2 is turned on, and a current starts to flow between the source S2 and the drain D2. Then, the potential V ₄ of the drain D2 of the transistor T2 resistance R
Start rising by 2. When the potential V ₄ is the source S3- gate G3 between voltage of the transistor T3 is higher than the threshold voltage V _TP (= 1.0V) transistor T3
Is also turned on. Thus, the transistors T2, T
3 are both turned on, the CM is connected via an external resistor R3.
The current I starts to flow into the input terminal of the OS integrated circuit 10. The current I causes the CMOS integrated circuit 10
Voltage V ₂ of the input terminal voltage than the voltage V ₁ (I × R3)
Only lower. When the value of the resistor R2 is equal to the value of the resistor R1, when the voltage V ₂ of the input terminal becomes if equal to the supply voltage V _CC, the potential V ₄ becomes 3.5 V, while the gate G3- source S3 of the transistor T3 Becomes extremely deep, and the transistor T3 is completely turned on.
Therefore, the voltage V ₂ at the input terminal does not rise above the power supply voltage V _CC. Thus the voltage V ₂ of the input terminal of the CMOS integrated circuit 10 exceeds the voltage V _a, so that asymptotically approaches the power supply voltage V _CC. The voltage V ₁ is, for example, a battery voltage of 12 V in an automobile, and its maximum voltage V _1max = 16 V
It is.

As a design example, transistors T1, T2,
The value of W / L (gate width / gate length) of T3 is 2
5, 25, and 106, and the resistance values of the resistors R1, R2, and R3 are respectively 100 KΩ, 100 KΩ, and 10 KΩ. Then, as illustrated the relationship between the voltage V ₂ for the voltages V ₁ in FIG. 2, has been conventionally the voltage V ₂ when the voltages V ₁ exceeds the supply voltage V _CC exceeds the supply voltage V _CC, the in CMOS integrated circuit 10 of the invention, voltage V ₂ be exceeded voltages V ₁ a power supply voltage V _CC never exceed the supply voltage V _CC. That is,
In the CMOS integrated circuit 10 of the present invention, the above-described parasitic current I
_{Since P} does not flow, variation in characteristics or malfunction is prevented.

Next, as another embodiment, the CMOS integrated circuit 20 has a circuit configuration as shown in FIG. That is, C
When there are two or more inputs to the MOS integrated circuit 20,
For each input channel, a circuit composed of transistors T2 'and T3' and resistors R2 'and R3' (a circuit indicated by a chain line in FIG. 3) is added. The transistor T1 and the resistor R1 can be commonly used for each channel. The operation of each channel of the CMOS integrated circuit 20 of this embodiment is the same as that of the above-described embodiment, and a description thereof will be omitted.

Next, as another embodiment, the CMOS integrated circuit 30 has a circuit configuration as shown in FIG. That is, the resistors R _A and R _B are substituted for the resistors R 1 and the transistors T 1 in the CMOS integrated circuit 10 of FIG.
Then, the value gate potential V ₃ of the transistor T2 is calculated by the following equation is constant. V ₃ = V _CC × R _A / (R _A + R _B ) As a design example, the resistances R _A and R _B are each 70 KΩ, 3
Set to 0KΩ. Here, it is assumed that the power supply voltage V _CC = 5V and the threshold voltage V _TP of the transistor T2 is 1.0V. Then, the gate potential V ₃ of the transistor T2 becomes 3.5
V and the voltage V _a of the transistor T2 begins to flow current turned on becomes 4.5V. CMOS of this embodiment
The operation of the integrated circuit 30 is the same as that of the above-described embodiment, and a description thereof will be omitted.

Next, as another embodiment, the CMOS integrated circuit 40 has a circuit configuration as shown in FIG. That is, the circuit configuration is such that the resistor R2 and the transistor T3 are eliminated from the CMOS integrated circuit 10 of FIG. Transistor T2 begins to conduct at a voltage V ₂ is 4.5V input terminals, as the voltage V ₂ increases, the source - bias between the gate becomes deeper, the source - the voltage drop between the drain gradually decreases. Therefore, increase in the voltage V ₂ is suppressed. FIG. 6 shows FIG.
Is a characteristic diagram showing the relationship between the voltage V ₂ for the voltages V ₁ in the circuit of. In this characteristic diagram, the voltage V ₁ is the power supply voltage V
_This shows that the slope of the curve after exceeding _CC is larger than the slope in the circuit of FIG. The CMOS of the present embodiment
In order to prevent the variation or malfunction of the characteristics of the integrated circuit 40,
After the voltages V ₁ exceeds the supply voltage V _CC, it must be used in the range in which the voltage V ₂ does not exceed the power supply voltage V _CC. Then, since the range of voltages V ₁ to be V ₂ ≦ V _CC is narrow CMOS integrated circuit 40 of the present embodiment uses will be limited from CMOS integrated circuit 10 of FIG.

[0014]

According to the present invention, the input voltage of the first circuit portion in the integrated circuit forward biases the first PN junction diode.
A bypass circuit that bypasses the input current so that the voltage does not exceed the voltage at which conduction occurs .
The current through the resistor is controlled, and therefore the voltage drop across the resistor.
The bottom is controlled. As a result, the voltage at the input terminal of the resistor
1 PN junction diode is forward-biased and turned on.
Voltage, the input voltage of the first circuit remains at the first PN junction
Do not exceed the voltage at which the diode is forward biased and turned on.
And not. As a result, the first PN junction diode becomes conductive.
The first PN junction diode and the second
Parasitic transistor composed of a PN junction diode
Does not conduct. Therefore, the parasitic current is
The operation of the second circuit is
Said that it becomes unstable due to the signal voltage to the first circuit
Is prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a CMOS integrated circuit according to a specific embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a relationship between an external power supply voltage and an input voltage to an integrated circuit according to the embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the CMOS integrated circuit according to the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the CMOS integrated circuit according to the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the CMOS integrated circuit according to the present invention.

FIG. 6 is a characteristic diagram showing a relationship between an input voltage to an integrated circuit and a voltage of an external power supply according to the embodiment of FIG. 5 in comparison with the embodiment of FIG. 1;

FIG. 7 is a conventional CMO for detecting on / off of a switch.
FIG. 2 is a circuit diagram illustrating an S integrated circuit.

FIG. 8 is a diagram showing a structure of a CMOS integrated circuit according to FIG. 7;

[Explanation of symbols]

10-CMOS integrated circuit V _{CC -power} supply voltage V _{1 -voltage of} external power supply V ₂ -input voltage T1, T2-p-channel field-effect transistor (transistor) T3-n-channel field-effect transistor (transistor) R1, R2-resistance R3 −External resistance

Claims (5)

(57) [Claims] 1. A semiconductor substrate, first and second PN junction diodes formed in common with one conductive region connected to a power supply on the semiconductor substrate, and the first PN junction diode is a first PN junction diode . A first circuit portion inserted in parallel between an input line and the power supply, and a second circuit in which the second PN junction diode is inserted in parallel between a second input line and the power supply And the first circuit unit includes
In an integrated circuit which is higher than the power supply voltage is introduced via a resistor, the input voltage of said first circuit portion is the first PN junction die
Do not exceed the voltage at which the diode is forward biased and turned on
Connection between the resistor and the first PN junction diode
From the point by bypassing the current through the resistor
A voltage drop across the resistor to raise the input voltage to the high
Having a bypass circuit that lowers the voltage
Integrated circuit characterized. 2. The method according to claim 1, wherein the bypass circuit is connected to a reference voltage and the connection.
The first to use the difference from the voltage at the continuation point as the bias voltage
A reference circuit, wherein the reference voltage is
Is the sum of the bias voltage and the first PN junction diode.
Voltage is lower than the voltage that makes the circuit forward-biased and conducts.
The integration circuit according to claim 1, wherein the voltage is a voltage.
Road. 3. The circuit according to claim 1, wherein the bypass circuit is connected to the first transformer.
Connected to the connection point in parallel with the
A voltage proportional to the current flowing through the first transistor circuit
A second transistor circuit for setting a bias voltage;
Increase the bypass current to reduce the voltage drop across the resistor.
3. The integration circuit according to claim 2, wherein the integration time is improved.
Road. 4. The power supply according to claim 1, wherein the bypass circuit is connected to the power supply.
Self-powered according to the current flowing through its own transistor.
The threshold voltage of the first transistor circuit is
Third transistor having a threshold voltage substantially equal to the voltage
Circuit, and the control terminal of the third transistor circuit
The voltage is used as the reference voltage.
The integrated circuit according to claim 2 or 3. 5. The second circuit is a comparator,
The second input line receives a reference voltage of a comparator.
Claim 1 to Claim Any of item 4
An integrated circuit according to claim 1.