JP2570933B2 - Synchronous clock generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous clock generator for synchronizing a high frequency input clock signal with an externally supplied asynchronous trigger signal and outputting the same.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a conventional synchronous clock generator, and FIG. 9 is a waveform diagram for explaining the operation of the synchronous clock generator of FIG . The clock signal CK generated by the high-frequency clock generating circuit 102 in FIG. 8 are respectively supplied to the clock input terminal A of the clock input terminal A and a frequency divider 104 of the counter 103, also to the trigger input terminal B of the counter 103 A trigger signal TR asynchronous with the clock signal CK is supplied as a counter enable signal from a trigger signal source (not shown) via a trigger signal input terminal 100.

[0003] Counter 103 begins to count the number of immediately after the H of the trigger signal TR falling t ₁ to L frequency clock signal, when the count number reaches a predetermined value, for example 3 count, counter 103 min Circumference enable signal D
E is generated and supplied to the enable signal input terminal B of the frequency divider 104.

The frequency divider 104 has an enable signal input terminal B
Starts the frequency division of the high frequency clock signal CK in response to the frequency division enable signal DE supplied to the output clock signal CK, for example, every four cycles of the high frequency clock signal CK.
Generates Kout. Thus, the synchronous clock output terminal 10
1 trigger signal TR is substantially the output clock signal CKout the synchronization is taken can be obtained from.

[0005]

In THE INVENTION It is an object of the conventional synchronous clock generating device as described above, as shown in FIG. 9, the output clock signal if the falling t ₁ of the trigger signal TR changes within a range T shown by a dotted line CKout will occur at the same timing. Therefore, in order to increase the synchronization accuracy of the output clock signal CKout, the frequency of the high frequency clock signal CK must be increased. Thus, the synchronization accuracy is represented by the period of the high-frequency clock.

For example , when it is desired to obtain synchronization accuracy with a deviation of 1 ns (nanosecond), a 1 GHz high frequency clock signal CK
It is necessary to use a high frequency clock signal of 1 GHz.
It is extremely difficult to increase to z since there are problems such as generation of noise and unnecessary radiation inside. Also, the 1 GHz clock signal generation circuit and the frequency divider
It is impossible to construct a general CMOS circuit, and a special technique such as an ultra-high-speed bipolar technique is required, resulting in an extremely high manufacturing cost.

The present invention is also an asynchronous trigger signal in any timing is supplied to the reference clock signal as a reference, substantially is only shifted but a certain amount of time from the falling of the asynchronous trigger signal Thus, an output clock signal is generated. This point will be described in more detail with reference to FIG.

[0008] In FIG. 7, CK is a clock signal supplied from the clock generation circuit, the trigger signal TR1, the falling t ₁₁ to the shall not a viable <br/> at H level of the clock signal CK. Output clock signal CK1 this time is output after being shifted by a predetermined time t ₁ from the falling t ₁₁ of the trigger signal TR1.

[0009] On the other hand, the trigger signal TR2 is, the falling t
₁₂ and shall may arise from at L level of the clock signal CK
I do. At this time, the output clock signal CK2 is the trigger signal T
Substantially is output after being shifted by a constant time t ₂ from the falling t ₁₂ of R2.

It is an object of the present invention that the phase relationship between the clock signal CK and the trigger signal is as shown by TR1 and TR2 in FIG.
In even in the very conditions such as, it is substantially shifted by a predetermined time t from the fall of the trigger signal (i.e. t ≒
t _1, t ≒ t ₂₎ output device for generating a clock signal, generating in particular without jitter using a high frequency clock signal generator, such as say output clock signal is suppressed to about the maximum ± 1 ns and 1GHz It is another object of the present invention to provide a synchronous clock generator capable of performing the above.

[0011]

Means for Solving the Problems According to the first basic invention of the present application,
Such a synchronous clock generator cascades a plurality of delay elements.
The clock signal is
To generate a plurality of delayed clock signals sequentially delayed
Extended clock signal generation circuit and corresponding to each of the above clock signals
A corresponding clock signal and the clock signal
Input signal acting as an asynchronous trigger signal to
Supplied and activated by the asynchronous input signal.
Then, the output state changes in response to the clock signal.
Multiple flip-flops and the above asynchronous input signal
After each flip-flop is activated, the clock
Flip whose output state first changes in response to the
A clock that detects the clock signal supplied to the flop
Detection circuit, and responds to the output signal of the clock detection circuit.
To the flip-flop whose output state first changed
Supplied clock signal or after this clock signal
Select and output another desired clock signal following or preceding
A clock selection circuit for outputting as a clock signal;
The output signal of the clock detection circuit is applied to each of the flip-flops.
And the output state of each of the flip-flops
Return means for maintaining.

In the first basic invention, the clock detection is performed.
Predetermined clock signal is selected in response to output circuit output signal
When selected, the delay following this selected clock signal.
The clock signal is applied to the delay element that generates the delayed clock signal.
In order to prevent transmission, the clock detection circuit
A forbidden path can be provided between the output and each delay element.
You.

A synchronous clock according to a second basic invention of the present application
The generator is configured by cascading a plurality of delay elements,
Multiple clocks sequentially delayed with respect to the input clock signal
Delay clock signal generation circuit for generating a delay clock signal
And the corresponding clock signal
Clock input terminal to which the lock signal is supplied.
Input signal that is asynchronous with respect to the
Or reset terminal, data input terminal, and data output
Has a terminal and is activated by the asynchronous input signal.
Then, the output state changes in response to the clock signal.
A plurality of flip-flops and the plurality of flip-flops
A clock signal that is temporally adjacent to the
Generated at each data output terminal of two flip-flops
When a level change occurs between the output signals, the level changes.
Output signal is detected, and the output signal is
Input terminal of the flip-flop at the previous stage of the flip-flop
To maintain the state of the two flip-flops
A plurality of logic circuits, and outputs of the plurality of logic circuits
The input clock signal or the plurality of delay clock signals and
Is supplied, based on the output signal of the logic circuit.
Input clock signal or multiple delayed clock signals
Output clock by selecting one of the two clock signals.
And a clock selection circuit for outputting as a clock signal.
I have.

In the second basic invention, the logic circuit
Between the clock and each delayed clock signal generation circuit
From the circuit that generates the clock signal selected by the circuit
Change of the output state of the delay element
A forbidden path can be provided for blocking.

[0015]

According to each basic invention of the present application having the above configuration,
According to this, a clock input asynchronously with respect to a clock signal is used.
For rigger signals, i.e. asynchronous input signals, at most
Equivalent to the delay time per stage of each connected delay element
Output clock signal can be generated with the deviation
For example, using a high frequency clock signal such as 1 Ghz
1 ns or less for the asynchronous input signal without using
The output clock signal can be generated by the deviation of.

In each of the above basic inventions, a prohibited path is set.
Delays following the selected predetermined clock signal
The clock signal is prevented from being generated and the flip-flop
The operating speed of the flip varies, and a certain flip
The flop responds to the clock signal supplied to it.
Even if the operation speed is delayed, this particular flip-flop
Is the delayed clock following the selected clock signal
Undesirable responses to signals are prevented.

[0017]

FIG. 1 is a block diagram of a first embodiment of a synchronous clock generator according to the present invention. In the figure, 10, 11, 1
Reference numerals 2, 13, and 14 are cascade-connected delay elements, where each delay element is constituted by an AND circuit composed of a semiconductor element having a substantially constant delay time of, for example, 1 ns. A delay clock generation circuit is constituted by cascade-connected delay elements.

Reference numeral 2 denotes an input terminal to which a basic clock signal is supplied from a basic clock signal source (not shown). The clock signal CK0 supplied to the input terminal 2 is a first stage delay element 1
0 to the first input (non-inverting input) of the delay element 1
A second input of 0 (inverted input) is grounded. Each output of the delay elements 10 to 14 is connected to a first input (non-inverting input) of a delay element of the next stage, and the output of each of the delay elements 10 to 14 is a clock signal CK delayed by a predetermined time.
1, CK2, CK3, CK4 and CK5 are generated.

In this embodiment, reference numerals 20, 21, 22, 23, and 24 denote edge-triggered D flip-flops. The clock input T of the first-stage flip-flop 20 has a non-delayed basic clock signal supplied to the input terminal 2. CK0 is supplied, and each clock input T of the flip-flops 21 to 24 is supplied.
The clock signal CK delayed by the delay elements 10 to 13
1~CK4 is subjected fed respectively. In addition, each flip
The reset input R of the flop 20-24 trigger signal TR supplied asynchronously to the trigger signal input terminal 1 with respect to the clock signal is subjected fed as asynchronous input signal.

Reference numerals 30, 31, 32, 33, and 34 denote AND circuits, and these AND circuits are flip-flops 20 to
After the trigger signal is supplied to 24 and the reset is released, a set detection circuit for detecting the flip-flop set first is configured. A first input (inverted input) of the AND circuit 30 has an output Q of the first-stage flip-flop 20.
0 is supplied to the first input (inverted input) of the AND circuit 31
Is supplied with the output Q1 of the second-stage flip-flop 21, the first input (inverted input) of the AND circuit 32 is supplied with the output Q2 of the third-stage flip-flop 22, and the first input of the AND circuit 33 is supplied. (Inverted input)
The output Q3 of the flop 23 is supplied, and the first input (inverted input) of the AND circuit 34 is the fifth flip-flop 2
4 outputs Q4 are provided.

The output Q1 of the second-stage flip-flop 21 is supplied to the second input (non-inverting input) of the AND circuit 30, and the third input is supplied to the second input (non-inverting input) of the AND circuit 31. The output Q2 of the flip-flop 22 is supplied, the output Q3 of the fourth flip-flop 23 is supplied to the second input (non-inverting input) of the AND circuit 32, and the second input (non-inverting input) of the AND circuit 33 is provided. ) Is supplied with the output Q4 of the fifth flip-flop 24, and the AND circuit 3
The second input (inverting input) of 4 is grounded in this example.

The output (a) of the AND circuit 30 is a feedback path 3
0R, the data is fed back to the data input D of the flip-flop 20.
Connected to input (inverted input). Similarly, the output (B) of the AND circuit 31 is fed back to the data input D of the flip-flop 21 via the feedback path 31R.
It is connected to the second input (inverting input) of the delay element 12 via 1I.

The output (C) of the AND circuit 32 is the feedback path 3
2R, the data is fed back to the data input D of the flip-flop 22, and the second path of the delay element 13
The output (d) of the AND circuit 33 is fed back to the data input D of the flip-flop 23 via the feedback path 33R, and the second input of the delay element 14 via the inhibition path 33I. (Inverting input). The output (e) of the AND circuit 34 is fed back to the data input D of the flip-flop 24 via the feedback path 34R, and is connected to the second input of the next delay element of the delay clock generation circuit as required.

Reference numerals 40, 41, 42, and 43 denote AND circuits.
These AND circuit after reset of the flip-flop 20 to 24 is released, and Configure the clock signal selection circuitry of <br/> order to select the desired clock signal. The two inputs of the AND circuit 40 are the outputs (A) of the AND circuit 30
The delay clock signal CK1 of the delay element 10 is supplied, and the two inputs of the AND circuit 41 are supplied with the output (B) of the AND circuit 31 and the delay clock signal CK2 of the delay element 11, respectively. The output (c) of the AND circuit 32 and the delayed clock signal CK3 of the delay element 12 are supplied to the two inputs, respectively.

The two inputs of the AND circuit 43 are supplied with the output (d) of the AND circuit 33 and the delayed clock signal CK4 of the delay element 13, respectively. AND circuit 40-4
The outputs (a) to (d) of the OR circuit 3 are supplied to a multi-input OR circuit 50, and the output of the OR circuit 50 is supplied to a synchronous clock output terminal 3 that outputs a clock signal synchronized with a trigger signal.

FIG. 2 shows the operation of the synchronous clock generator of FIG.
This will be described with reference to FIG. FIG. 2 shows an IC constituting the device of FIG.
Operating speed of each element in the flip-flop 20
24 is a diagram illustrating the operation assuming a case where there is no variation in the recovery times (time from when the reset is released to when the clock can be fetched) from 24 to 24.

TR is an asynchronous trigger signal supplied from a trigger signal source (not shown) to the trigger signal input terminal 1;
CK0 is a basic clock signal supplied from a clock signal source (not shown) to the clock signal input terminal 2;
1, CK2, CK3, and CK4 are delay elements 10, 11, 1
2 and 13 are delayed clock signals appearing at respective outputs. As the flip-flops 20 to 24, an edge-triggered D flip-flop is used in the embodiment, and the clock signal T
When R is falls, acting as a storage circuit for storing captures reversal (D bar) content of the data supplied to the data input D.

[0028] Until but Ri falling of the trigger signal TR appear
Indicates that each flip-flop is held in reset and
Reset of each flip-flop is released in the down t _1. Clock signal CK supplied to clock input T of flip-flop 20 and flip-flop 21
Since 0 and CK1 fall before reset release by the trigger signal TR, these flip-flops 20 and 21 are not set, and their outputs Q0 and Q1 are at L (low level).

On the other hand, at t ₁₂ , flip flop 2
The clock signal CK3 supplied to the clock input T of the flip-flop 23, 24 with the clock signal CK2 and t ₁₂ after being supplied to the second clock input T, the fall of CK4 is after reset by the trigger signal TR from these flip-flops 22 to 24 is set, its output Q2, Q3, Q4, respectively clock signal
It goes to H (high level) in response to the falling edges of CK2, CK3, and CK4 .

As a result, the output (A) of the AND circuit 30 becomes L when Q0 = L and Q1 = L ,
Of the AND circuit 32 becomes H at _t121 by Q1 = L and Q2 = H , and the output (C ) of the AND circuit 32 is Q2 = H, Q
3 = H by L, the output of the A-end circuit 33 (d) is Q3 =
When H and Q4 = H, the output becomes L, and the output (b) becomes H.
First delay clock came edge from H to L is found to be CK2 after the reset release of the flip-flop according to the trigger signal TR by Rukoto.

In this case, the outputs of the AND circuits 30 to 34 are fed back to the data inputs D of the corresponding flip-flops 20 to 24. Thereby, flip flop 2
0 is the next falling t of the basic clock signal CK0.
₂ to H, and the other flip-flops 21 to 24 remain in the previous state even when the next delayed clock signals CK1 to CK4 enter, that is, the output Q of the flip-flop 21.
Only 1 is kept at L, and outputs Q2-Q4 of flip-flops 22-24 are kept at H. That is, Q
0 = H, Q1 = L, Q2 = H, Q3 = H, Q4 = H. As a result, only the output (B) of the AND circuit 31 is kept at H.

The output (b) turns on the AND circuit 41, and only the clock signal CK2 outputs the output (b) of the AND circuit 41.
This output (b) is sent to the synchronous clock output terminal 3 via the OR circuit 50 . Thus, a series of the clock signal CK2 is synchronized to the selected trigger signal TR
It is output as an output clock signal CKout. Since the AND circuits 40, 42, and 43 are off, it goes without saying that the outputs (a), (c), and (d) are all L.

[0033] As described above, after the reset of the flip-flop has been released by the trigger signal TR, the first H
Is detected as CK2, and in this embodiment, as described above, a series of output clock signals CKout in which the delayed clock signal CK2 is synchronized with the trigger signal TR as described above. Is output from the output terminal 3.

The H output (B) of the AND circuit 31 is supplied to the second input (inverted input) of the delay element 12 via the inhibition path 31I, inhibits the delay element 12, and the clock signal advances to the delay element 13. To block. For this reason, C
K3 and CK4 become L, regardless of the state of the AND circuits 32 and 33 (actually, these AND circuits 32 and 3
3 are both turned off), and the outputs (c) and (d) of the AND circuits 42 and 43 both become L. Therefore, the output clock signal CKout corresponding to the clock CK2 is generated at the output terminal 3 as described above. Therefore, the output clock signal CK
The jitter of out falls within the delay time of the delay elements 10 to 14, and it is easy to set the delay time of each delay element to about 1 ns.
without having to use high frequencies like z
Easily jitter can be suppressed within 1ns.

The trigger signal TR is supplied to the input terminal 1 again.
Then, during the existence period of the trigger signal (in this embodiment, H
In the meantime, all flip-flops are reset once
The output Q0 to Q4 of each flip-flop becomes L
A series of output clocks based on the delayed clock signal CK2.
The lock signal CKout temporarily stops. The trigger signal TR
When falling, the same operation as described above causes
Synchronizes the closest delayed clock signal to the above trigger signal again
Clock signal, and select the selected clock signal.
Output a series of output clock signals CKout based on the clock signal
Generated from terminal 3.

As assumed above, if there is no variation in the operating speed of each element in the IC, the inhibition paths 30I to 33
I is not particularly necessary, but if the operating speed of each element in the IC described below varies,
３３33I becomes effective, and the output of an erroneous clock signal is prevented.

FIG. 3 shows the operation speed of each flip-flop in the circuit of FIG. 1, specifically, the recovery time of each flip-flop (the time required until a clock can be taken after reset release). FIG. 9 is a waveform diagram illustrating an operation when there is variation.

[0038] In this example, the recovery time of the flip-flop 23 is slower than that of the other flip-flop, after a falling edge of the trigger signal TR is supplied to the trigger signal input terminal 1 at t _1, the first delay when the falling edge of the clock signal CK3 arrives (time t _13), the flip-flop 23 assumes a state where it was not possible to incorporate this delay clock signal CK3.

It is assumed that the prohibited paths 30I to 33I do not exist. After the trigger signal TR is supplied, a flip-flop 22 is set and the output Q2 by falling t ₁₂ of the delayed clock signal CK2 becomes H. Flip-flop 23 is slow recovery time as described above, it is not set on the falling edge t ₁₃ of the delayed clock signal CK3. The flip-flop 24 is the falling t ₁₄ of the delayed clock signal CK4.
And the output Q4 becomes H.

Thus, immediately after the first falling of each of the delayed clock signals CK2 to CK4 after the trigger signal TR is supplied, Q0 = L, Q1 = L, Q2 = H,
Q3 = L and Q4 = H. Thereby, the AND circuit 3
0 is off, the AND circuit 31 is on, the AND circuit 32 is off, the AND circuit 33 is on, and the AND circuit 34 is off. The output (d) of the circuit 33 also becomes H.
The outputs of the AND circuits 30 to 34 are output from the respective feedback paths 30R to 34.
R is fed back to the data input D of the corresponding flip-flop 20 to 24, and the output Q of the flip-flop 20
Except for changing 0 from L to H, the output of each AND circuit is held in the previous state, and Q0 = H, Q1 = L, Q2 = H, Q
3 = L and Q4 = H.

As a result, the AND circuits 41 and 43 are both turned on, and the output (b) of the delayed clock signal CK2 is output.
Then, an output (d) (shown by a dotted line) based on the delayed clock signal CK4 is output from the synchronous clock output terminal 3 via the OR circuit 50. Therefore, the synchronous clock signal CKout generated at the output terminal 3 is the sum of the output corresponding to the output (b) indicated by the solid line and the output corresponding to the output (d) indicated by the dotted line, and has a width (To). It becomes longer than the regular clock signal width (T _C ). Prohibited paths 30I, 33
I is for preventing such a situation from occurring.

[0042] As described above, the output Q2 of the flip-flop 22 in response to the first falling at t ₁₂ of the delayed clock signal CK2 becomes H, the output of the AND circuit 31 (b) becomes H. The output (b) is supplied to the second input (inverted input) of the delay element 12 via the inhibition path 31I to turn off the delay element 12 and inhibit the clock signal from appearing after the output of the delay element 12. .

Since the output (A) of the AND circuit 30 supplied to the second input of the delay element 11 is L, the delay element 11 is turned on, and the clock signal advances through the delay element 11 and is delayed. The clock signal CK2 appears. Thus, the output terminal 3 is connected to the delayed clock signal CK2 regardless of the variation of the recovery time of each flip-flop.
Only a series of output clock signal CKout that corresponds to occur.

In the embodiment of FIG. 1, after the trigger signal TR is supplied to the input terminal 1 and the reset of each flip-flop is released, the first falling clock signal CK2 falls.
Is detected and stored by the flip-flop 22, and the delayed clock signal CK2 is selected to output the clock signal CKou.
The signal was output from the output terminal 3 as t. However, when the frequency of the clock signal becomes high to some extent, delay falling into Thus the flip-flop 22 of the clock signal CK 2 is set, the output of the AND circuit 31 whose output Q2 is turned H (b) is H rise of the delayed clock signal CK2 arrives before the (t ₂₂ of FIG. 2), the output signal (b) of this for the aND circuit 41, thus synchronous clock signal CKout generated in the output terminal 3 via the OR circuit 50 May be smaller than the regular width _Tc . Alternatively, in some cases, it is desirable to select the delayed clock signal CK3 next to the delayed clock signal CK2 and to output this as the output clock signal CKout in order to prevent malfunction.
The device shown in FIG. 4 is suitable for such a purpose.

Embodiment 2 In the second embodiment of the synchronous clock generator of the present invention shown in FIG. 4, the second input (inverted input) of the delay element 11 is grounded, and the forbidden path 30I is connected to the delay element. 12, the forbidden path 31I is connected to the second input of the delay element 13, and the forbidden path 32I is connected to the second input of the delay element 14. The output of the AND circuit 30 and the delayed clock signal CK2 are supplied to the input of the AND circuit 40, and the output of the AND circuit 31 and the delayed clock signal CK3 are supplied to the input of the AND circuit 41. The output of the AND circuit 32 and the delayed clock signal CK4 are supplied to the input of the AND circuit 42, and the output (d) of the AND circuit 33 and the delayed clock signal C are supplied to the input of the AND circuit 43.
K5 is supplied. Other structures and connection relations are the same as those of the embodiment of FIG.

The operation of the embodiment shown in FIG. 4 will be described again with reference to FIG . Asynchronous trigger signal T to trigger signal input terminal 1
After R is supplied, a flip-flop 22 at the first falling t ₁₂ of the delayed clock signal CK2 is set, its output Q2 becomes H. This AND circuit 31 is output at t ₁₂₁ is turned on (b) becomes H, the AND circuit 41 is not the delayed clock signal CK2, a set of output clock signal selects a delay clock signal CK3 CKout
From the output terminal 3 is output as. Prohibited paths 30I-3
The operation of 2I is the same as that of the embodiment of FIG. 1, and in this case, the output (B) at the H level of the AND circuit 31 is the prohibited path.
Is supplied to the second input of the delay element 13 through 31I, it prevents the appearing delay clock CK4 to the output of the delay element 13. Also in this embodiment , such as 1 GHz
The jitter of the output clock signal CKout can easily suppress it within 1ns without using a high clock signal.

In the embodiment of FIG. 1, flip-flop 2
Depending on the operation speed of the AND circuits 30 to 34 and the level change speed of each of the delayed clock signals CK1 to CK4, two inputs of the AND circuits 30 to 33 may change at the same time. Describing in detail about this again with reference to FIG. 2, the output Q2 of the flip-flop 22 in response to the fall of the delayed clock signal CK2 at t ₁₂ is H
, And the output of the AND circuit 31 becomes H at t ₁₂₁ .

[0048] In this case, the flip-flop 22, when the operation speed of the AND circuit 31 is fast, the delay clock signal CK2
Rising t of output falling t ₁₂ and the AND circuit 31 (b)
₁₂₁ and occurs at substantially the same time, the second AND circuit 41
One of the inputs may spike is generated in the output together momentarily becomes H (b), the spike may be output from the sync clock output terminal 3 via the OR circuit 50 undesirably . As described above, in the embodiment of FIG.
One input of the AND circuit 41 is connected to the output of the AND circuit 31.
(B) is supplied, and the other input is the delayed clock signal C
A clock signal CK3 further delayed than K2 is supplied.
Therefore, the AND circuit 41 is connected to the unwanted spy as described above.
Is prevented from occurring.

(Embodiment 3) When the frequency of the clock signal is low and it is not necessary to adopt the configuration shown in FIG. 4, it is desirable to use the third embodiment having the structure shown in FIG. In the embodiment of FIG.
The same reference numerals are given to the same parts as those of the embodiment, and the description is omitted. In the embodiment of FIG. 5, a delay element 9 is additionally provided before the delay element 10, and the basic clock signal CK is provided.
0 is supplied to a first input (non-inverting input) of the delay element 9, and a second input (inverting input) of the delay element 9 is grounded. The outputs of the delay elements 9 to 14 are clock signals CK <b> 1 to CK <b> 1 delayed by a fixed time (for example, 1 ns).
CK6 occurs.

The non-delayed basic clock signal CK0 is supplied to one input of an AND circuit 40, and the delayed clock signal C
K1 to CK5 are supplied to the respective clock input terminals T of the flip-flops 20 to 24, and the AND circuits 41 to
44 to one input. Delayed clock signal CK
6 is supplied to a delay element and an AND circuit (not shown) at the next stage as required.

The outputs of the AND circuits 30 to 34 are fed back to the data inputs D of the flip-flops 20 to 24 via the feedback paths 30R to 34R, and are prohibited paths 30I to 3R.
Via 4I, it is supplied to each second input (inverted input) of the feedback elements 10 to 14. Outputs of the AND circuits 40 to 44 are supplied to an OR circuit 50.

FIG. 6 shows the operation of the synchronous clock generator of FIG.
This will be described with reference to FIG. Also in this embodiment, the output Q2 with the flip-flop 22 at the falling T ₁₂ of the delayed clock signal CK3 to the first occurrence is set after the falling t ₁ of the trigger signal TR becomes H. At this time, flip
Since the output Q1 of the flop 21 is L, the AND circuit 3
1 is turned on, its output (b) becomes H, and the AND circuit 41 is turned on. Since the other input of the AND circuit 41 is supplied delayed clock signal CK1, the output of the AND circuit 41 at the rising edge t ₂ of CK1 (b) becomes H, the corresponding from the sync clock output terminal 3 to the clock signal CK1
A series of output clock signal CKout occurs that.

[0053] In this case, the delay clock signal CK1 is a timing earlier t ₀₂ than the falling t ₁₂ of the delayed clock signal CK3 which is first detected after the falling t ₁ of the trigger signal TR
And the output of the AND circuit 31
When (b) goes high, the clock signal CK1 has already gone low.
Therefore, as in the embodiment of FIG.
Does not change at the same time to cause a spike in the output. By slightly changing the circuit connection,
An output clock signal CKout corresponding to the clock signals CK0 and CK2 can also be extracted.

The outputs of AND circuits 30 to 34 are connected to feedback path 3
Flip flop 20 through 0R-34R
24, and AND circuit 3
The purpose of supplying the outputs 0 to 34 to the second inputs (inverted inputs) of the delay elements 10 to 14 via the inhibition paths 30I to 34I is the same as that of each embodiment shown in FIGS. In this embodiment, the H output of the AND circuit 31 is supplied to the second input of the delay element 11 to prevent the delayed clock signal from being transmitted to a stage subsequent to the delay element 11.

In each embodiment of the present invention, the trigger signal TR is input to the reset terminal R of the flip-flop and the Q output is used.
The logic can also be configured to use the bar output. In short, after the trigger signal is supplied, the delay clock at which the change first appears is detected, returned to the flip-flop via the feedback path and stored, and the delay clock or a desired delay clock before and after the delay clock is selected. The present invention can be realized by configuring the logic to output the data. Also, cascade delay circuits 10 to 14 or 9
Needless to say, the number of stages of the flip-flops 20 to 24 and the flip-flops 20 to 24 can be freely changed by design.

[0056]

Synchronizing signal generating apparatus of the present invention as described in the foregoing generates a delay clock sequentially delayed by using a plurality of simple logic elements such as AND circuits, the occurrence of an asynchronous trigger signal since it is used to select the desired delayed clock as a reference, since the jitter is the delay time per stage delay element, a high-frequency such as 1GH _Z
Without using the clock generation circuit of the number, it is possible to generate a clock synchronized with the timing to high precision for the trigger signal.

Therefore, a high-precision synchronous clock generation circuit can be configured at low cost, can be widely applied to interfaces between systems having different basic operation clocks, and there is no fear of large high-frequency noise or unnecessary radiation. It can be used safely in horizontal and vertical synchronization circuits of various image processing units such as digital copiers. Further, when the device of the present invention is integrated into a IC, no special wafer process is required, and ± 1 n
An apparatus having a jitter of about s can be easily configured.

The trigger signal TR is supplied to the input terminal 1.
The output clock signal CKout stops temporarily.
The clock signal selected in response to the previous trigger signal
Output clock signal CKout already generated based on
And the clock signal selected in response to the next trigger signal
Generated on the basis of the output clock signal CKout and a sure real
Can be distinguished.

Further, once a desired clock signal is selected, a prohibition path for preventing a clock signal from being transmitted to a delay element for generating a delayed clock signal subsequent to the selected clock signal is provided for each logic circuit. By providing between the output and the delay element, even if there is a slight variation in the operation speed of each element constituting the synchronous clock generator of the present invention, the operation can be performed accurately regardless of the variation, and the trigger signal can be accurately output. A desired clock signal synchronized with the clock signal can be generated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a synchronous clock generator according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the device of FIG. 1 when there is no variation in the operation speed of each element in the device of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the device of FIG. 1 when the operating speed of each element in the device of FIG. 1 varies;

FIG. 4 is a configuration diagram of a second embodiment of the synchronous clock generator of the present invention.

FIG. 5 is a configuration diagram of a third embodiment of the synchronous clock generator of the present invention.

FIG. 6 is a timing chart for explaining the operation of the synchronous clock generator of FIG. 5;

FIG. 7 is a waveform chart for explaining an object of the present invention.

FIG. 8 is a block diagram of a conventional synchronous clock generator.

FIG. 9 is a timing chart for explaining the operation of the conventional synchronous clock generator of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Trigger signal input terminal 2 Clock signal input terminal 3 Synchronous clock output terminal 10-14 Delay element 20-24 Flip flop 30-34 AND circuit 40-43 AND circuit 50 OR circuit 30R-34R Feedback path 30I-33I Prohibited path

Continuation of the front page (72) Inventor Junji Mano 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Kita Itami Works (56) References JP-A-60-158718 (JP, A) JP-A-63- 202129 (JP, A) JP-A-1-115215 (JP, A) JP-B-63-41466 (JP, B1)

Claims (7)

(57) [Claims] 1. A cascade connection of a plurality of delay elements.
The clock signal that has been successively delayed with respect to the input clock signal.
Clock signal generation to generate the number of delayed clock signals
Circuit and a corresponding clock provided for each of the above clock signals.
Clock signal and an input signal that is asynchronous with respect to the clock signal.
Supplied and activated by the asynchronous input signal.
Then, the output state changes in response to the clock signal.
Each flip-flop is activated by a plurality of flip-flops and the asynchronous input signal.
First, output in response to the above clock signal
Clock supplied to the flip-flop whose state has changed.
A clock detection circuit for detecting a clock signal; and
The clock supplied to the flip-flop whose output state has changed
Select the lock signal and output it as the output clock signal
A clock selection circuit and an output signal of the clock detection circuit.
And the output state of each of the flip-flops
Feedback means for maintaining the output clock signal synchronized with the asynchronous input signal.
Synchronous clock generator that generates a signal. 2. A cascade connection of a plurality of delay elements.
The clock signal that has been successively delayed with respect to the input clock signal.
Clock signal generation to generate the number of delayed clock signals
Circuit and a corresponding clock provided for each of the above clock signals.
Clock signal and an input signal that is asynchronous with respect to the clock signal.
Supplied and activated by the asynchronous input signal.
Then, the output state changes in response to the clock signal.
Each flip-flop is activated by a plurality of flip-flops and the asynchronous input signal.
First, output in response to the above clock signal
Clock supplied to the flip-flop whose state has changed.
A clock detection circuit for detecting a clock signal; and
The clock supplied to the flip-flop whose output state has changed
Select and output another clock signal following the lock signal
A clock selection circuit for outputting a clock signal, and an output signal of the clock detection circuit for each of the flip-flops.
And the output state of each of the flip-flops
Feedback means for maintaining the output clock signal synchronized with the asynchronous input signal.
Synchronous clock generator that generates a signal. 3. A delay circuit comprising a plurality of delay elements connected in cascade.
The clock signal that has been successively delayed with respect to the input clock signal.
Clock signal generation to generate the number of delayed clock signals
Circuit and a corresponding clock provided for each of the above clock signals.
Clock signal and an input signal that is asynchronous with respect to the clock signal.
Supplied and activated by the asynchronous input signal.
Then, the output state changes in response to the clock signal.
Each flip-flop is activated by a plurality of flip-flops and the asynchronous input signal.
First, output in response to the above clock signal
Clock supplied to the flip-flop whose state has changed.
A clock detection circuit for detecting a clock signal; and
The clock supplied to the flip-flop whose output state has changed
Select and output another clock signal that precedes the lock signal
A clock selection circuit for outputting a clock signal, and an output signal of the clock detection circuit for each of the flip-flops.
And the output state of each of the flip-flops
Feedback means for maintaining the output clock signal synchronized with the asynchronous input signal.
Synchronous clock generator that generates a signal. 4. In response to an output signal of a clock detection circuit.
When a predetermined clock signal is selected, the selected clock signal is selected.
Delay to generate a delayed clock signal following the clock signal
To prevent the clock signal from being transmitted to the device
Between the output of the clock detection circuit and each delay element.
Wherein the first and second parts are provided.
Is a synchronous clock generator according to 3. 5. A delay circuit comprising a plurality of delay elements connected in cascade.
The clock signal that has been successively delayed with respect to the input clock signal.
Clock signal generation to generate the number of delayed clock signals
Circuit and a corresponding clock provided for the clock signal.
Clock input terminal to which the clock signal is supplied and the clock
Set or input signal supplied asynchronous to the signal
Are the reset terminal, data input terminal, and data output terminal
And after being activated by the asynchronous input signal,
A plurality of outputs that change the state of the output in response to the clock signal
And a temporally adjacent one of the plurality of flip-flops
Each of the two flip-flops to which the clock signal is supplied
A level change occurs between the output signals generated at the data output terminals.
When this occurs, the output signal whose level has changed is detected and
Of the preceding flip-flop of the two flip-flops
It is supplied to the data input terminal of the flop to
A plurality of logic circuits for maintaining a flip-flop state , outputs of the plurality of logic circuits and the input clock signal or
Is supplied with a plurality of delayed clock signals and
Based on the output signal of the
Any one of a number of delayed clock signals
Select the signal to be output as the output clock signal.
And an output clock signal synchronized with the asynchronous input signal.
Synchronous clock generator that generates a signal. 6. A logic circuit and each delayed clock signal generation circuit
Between the clock selected by the clock selection circuit
The output of the delay element located after the circuit that generates the signal
Prohibition path that prevents the state of force from changing
The synchronous clock generator according to claim 5, wherein: 7. A delay clock signal generating circuit comprising:
The delay element has two inputs, one of which is supplied to the input.
When the signal to be applied is at the first level, it is applied to the other input.
Generates an output signal delayed by a predetermined time
And the signal supplied to the one input is at the second level
Sometimes, the level of the signal supplied to the other input
Is a logic element that generates a constant level output signal regardless of
Rannahli, the first record in the one input of each logic element
Connected to the bell point or the output of the logic circuit.
The synchronous clock generator according to claim 5, wherein: