Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP2571082B2 - Transmission line length measuring device - Google Patents
[go: Go Back, main page]

JP2571082B2 - Transmission line length measuring device - Google Patents

Transmission line length measuring device

Info

Publication number
JP2571082B2
JP2571082B2 JP30932687A JP30932687A JP2571082B2 JP 2571082 B2 JP2571082 B2 JP 2571082B2 JP 30932687 A JP30932687 A JP 30932687A JP 30932687 A JP30932687 A JP 30932687A JP 2571082 B2 JP2571082 B2 JP 2571082B2
Authority
JP
Japan
Prior art keywords
transmission line
phase difference
timing
line length
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP30932687A
Other languages
Japanese (ja)
Other versions
JPH01150877A (en
Inventor
泰一 尾辻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP30932687A priority Critical patent/JP2571082B2/en
Publication of JPH01150877A publication Critical patent/JPH01150877A/en
Application granted granted Critical
Publication of JP2571082B2 publication Critical patent/JP2571082B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Locating Faults (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、遠端開放の伝送線路にパルスを送出して得
られる反射波形から伝送線路長を測定する伝送線路長測
定装置に関し、特に複数の試験ピンを有する集積回路試
験装置等において、該試験ピンに対応して設置された試
験パタン出力/試験結果判定回路から、被試験回路の入
出力ピンに至る伝送線路長の高精度測定等に適した伝送
線路長測定装置に関する。
Description: BACKGROUND OF THE INVENTION The present invention relates to a transmission line length measuring device for measuring a transmission line length from a reflected waveform obtained by transmitting a pulse to a transmission line having an open end, and more particularly to a plurality of transmission line length measuring devices. In an integrated circuit test device having test pins of the type described above, it is used for highly accurate measurement of the transmission line length from the test pattern output / test result judgment circuit installed corresponding to the test pins to the input / output pins of the circuit under test. The present invention relates to a suitable transmission line length measuring device.

(従来の技術) 集積回路試験装置の試験タイミング精度を維持するた
めに必要なタイミング補正においては、集積回路試験装
置の試験ピンに対応して設置された試験パタン出力/試
験結果判定回路から被試験回路の入出力ピンに至る伝送
線路長の、試験ピン間ばらつきによって生ずるタイミン
グ誤差を補正することが主要な処理項目の1つとなって
いる。従来においてはこのような伝送線路長の測定にお
いて、第4図に示す従来技術の一例の如く、出力タイミ
ングを高精度、高時間分解能で遅延制御できる基準タイ
ミング発生回路RTGを用意し、前記被試験回路1の入出
力ピン2を未接続として該伝送線路3の端点を開放した
状態で、試験パルス発生回路DRから試験パルスを送出す
ることによって得られる反射波形の第1の立上りエッジ
aの中間レベルを試験結果判定回路SDのしきい値レベル
入力RVに設定し、該立上りエッジaの立上り予測タイミ
ングの近傍で基準タイミングを2分法等に従って移動さ
せ、移動の都度基準タイミングパルスと反射パルスの第
1の立上りエッジaとの位相差を試験結果判定回路SDで
検出し、位相差ゼロとなったときの基準タイミング発生
回路RTGの遅延設定値から該第1の立上りエッジaのタ
イミングTaを求め、続いて前記反射波形の第2の立上り
エッジbの中間レベルを試験結果判定回路SDのしきい値
レベル入力RVに設定し、上述したのと同様の操作で該第
2の立上りエッジbのタイミングTbを求め、(Tb−Ta)
/2を計算して該伝送線路長の伝搬遅延時間を計測してい
た。
(Prior Art) In the timing correction necessary to maintain the test timing accuracy of the integrated circuit test apparatus, the test target is output from a test pattern output / test result determination circuit installed corresponding to the test pin of the integrated circuit test apparatus. One of the main processing items is to correct a timing error caused by variation between test pins in a transmission line length to an input / output pin of a circuit. Conventionally, in such a measurement of the transmission line length, a reference timing generating circuit RTG capable of delay control of the output timing with high accuracy and high time resolution is prepared as in an example of the prior art shown in FIG. The intermediate level of the first rising edge a of the reflected waveform obtained by transmitting the test pulse from the test pulse generating circuit DR with the input / output pin 2 of the circuit 1 not connected and the end point of the transmission line 3 opened. Is set as the threshold level input RV of the test result determination circuit SD, and the reference timing is moved in accordance with the bisection method or the like near the rising prediction timing of the rising edge a. 1 is detected by the test result determination circuit SD, and the phase difference from the reference timing generation circuit RTG when the phase difference becomes zero is determined from the delay set value of the reference timing generation circuit RTG. The timing Ta of the rising edge a is determined, and then the intermediate level of the second rising edge b of the reflection waveform is set as the threshold level input RV of the test result determination circuit SD, and the same operation as described above is performed. The timing Tb of the second rising edge b is obtained, and (Tb−Ta)
/ 2 was calculated to measure the propagation delay time of the transmission line length.

(発明が解決しようとする問題点) 前述の如く従来技術では、高精度な測定には、高精
度,高時間分解能で遅延制御ができる基準タイミング発
生回路が必要となり測定器が高価になること、2分法等
でのタイミング測定ゆえ一度の測定に複数回の基準タイ
ミング設定・スキュー検出動作が必要となり測定に時間
がかかる、などの問題を有していた。
(Problems to be Solved by the Invention) As described above, in the prior art, a high-accuracy measurement requires a reference timing generating circuit capable of performing delay control with high accuracy and high time resolution, and the measuring instrument becomes expensive. Since the timing measurement is performed by the bisection method or the like, a plurality of reference timing setting / skew detection operations are required for one measurement, so that there is a problem that the measurement takes time.

(問題点を解決するための手段) 本発明は従来の問題点を解決し、短時間でかつ高精
度,高時間分解能の測定が可能で、しかも回路構成の単
純な伝送線路長測定装置を実現するもので、遠端開放の
伝送線路にパルスを送出して得られる反射波形なら伝送
線路長を測定する伝送線路長測定装置において、一定の
繰り返し周期を有する反射波、及び該反射波とは繰り返
し周期がわずかに異なるタイミング比較パルス信号を共
通の被測定入力信号とし、該被測定入力信号しきい値の
制御が可能で、かつ該被測定入力信号間の思想極性に応
じて論理レベルが変化する位相差情報信号を出力する、
独立した2つの位相差検出回路と、該2つの位相差検出
回路の位相差情報信号が一致していない間のみ、前記タ
イミング比較パルス信号の分岐信号を通過させるゲート
回路と、該ゲート回路の出力信号パルス数を計数するカ
ウントとを備えてなることを特徴とする伝送線路長測定
装置を要旨とする。
(Means for Solving the Problems) The present invention solves the conventional problems and realizes a transmission line length measuring apparatus which can measure in a short time, with high accuracy and high time resolution, and has a simple circuit configuration. In a transmission line length measuring device that measures a transmission line length if a reflected waveform is obtained by sending a pulse to a transmission line that is open at the far end, a reflected wave having a constant repetition period, and the reflected wave are repeated. A timing comparison pulse signal having a slightly different period is used as a common input signal to be measured, the threshold value of the input signal to be measured can be controlled, and the logic level changes in accordance with the ideological polarity between the input signals to be measured. Output a phase difference information signal,
Two independent phase difference detection circuits, a gate circuit that passes the branch signal of the timing comparison pulse signal only while the phase difference information signals of the two phase difference detection circuits do not match, and an output of the gate circuit A transmission line length measuring device, comprising: a count for counting the number of signal pulses.

(作用) 本発明の伝送線路長測定装置は反射で生ずる階段状の
立上りエッジの、第1の立上りエッジのタイミングと第
2の立上りエッジのタイミングを個々に、該反射波とは
わずかに異なる繰り返しレートを有するタイミング比較
パルスの立上りエッジのタイミングと、位相差検出回路
で直接比較し、両者の比較結果(位相差情報)の簡単な
ディジタル処理によって伝送線路長(伝搬遅延時間)を
高精度に測定することができる。測定精度は位相差検出
回路の時間分解能とタイミング比較の繰り返しレートの
安定度によってほとんど決まり、測定時間分解能は反射
波とタイミング比較パルス信号の繰り返しレート差で決
まるため、容易に高精度,高時間分解能化が実現でき、
高精度,高時間分解能な基準タイミング信号発生器や複
雑な発振制御回路を必要としない。
(Operation) The transmission line length measuring apparatus of the present invention repeats the timing of the first rising edge and the timing of the second rising edge of the step-like rising edge generated by reflection individually, slightly different from the reflected wave. Directly compares the rising edge timing of the timing comparison pulse with a rate with the phase difference detection circuit, and measures the transmission line length (propagation delay time) with high precision by simple digital processing of the comparison result (phase difference information) of the two. can do. The measurement accuracy is mostly determined by the time resolution of the phase difference detection circuit and the stability of the repetition rate of the timing comparison, and the measurement time resolution is determined by the repetition rate difference between the reflected wave and the timing comparison pulse signal. Can be realized,
There is no need for a high-accuracy, high-time-resolution reference timing signal generator or complicated oscillation control circuit.

(実施例) 以下図面に基づき、本発明の実施例について説明す
る。なお、実施例は一つの例示であって、本発明の精神
を逸脱しない範囲で種々の変更あるいは改良を行いうる
ことは言うまでもない。
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. The embodiment is merely an example, and it goes without saying that various changes or improvements can be made without departing from the spirit of the present invention.

第1図に本発明の基本回路構成の一実施例を示す。伝
搬遅延時間Tの線路長を有する伝送線路3の遠端を開放
して得られる反射波RFの階段状の立上りエッジにおいて
第1の立上りエッジをa、第2の立上りエッジをbとす
る。前記第1及び第2の立上りエッジa,bには2Tだけタ
イミングのずれがある。入力信号のしきい値制御が可能
な位相差検出回路S1,S2が設置されており、位相差検出
回路S1は前記第1の立上りエッジaとタイミング比較パ
ルスPRの立上りエッジの位相差を比較すべく、両信号が
被測定入力信号として被測定信号入力端子T1,T1′に加
えられ、入力信号しきい値を決める基準レベル入力R11,
R12に各々第1の立上りエッジaの中間レベル、タイミ
ング比較パルスPRの中間レベルを設定する。同様に位相
差検出回路S2は前記第2の立上りエッジbとタイミング
比較パルスPRの立上りエッジの位相差を比較すべく、両
信号が被測定入力信号として被測定信号入力端子T2,
T2′に加えられ、入力信号しきい値を決める基準レベル
入力R21,R22に各々第2の立上りエッジbの中間レベ
ル,タイミング比較パルスPRの中間レベルを設定する。
位相差検出回路S1,S2は、タイミング比較パルスPRのタ
イミングが他方のタイミングに比べて遅れているとき
に、正の位相ずれ情報としてハイレベルを出力し、逆の
場合は負の位相ずれ情報としてローレベルを出力するNR
Z(Non−Return to Zero)の位相差情報信号OUT+1,OUT
+2をそれぞれ出力する。位相差情報信号OUT+1とOUT
+2はEX−ORゲート4によって排他論理和がとられ、更
にタイミング比較パルスPRとEX−ORゲート4の出力信号
EORはANDゲート5によって論理積がとられ、EX−ORゲー
ト4の出力EORがハイのときのみタイミング比較パルスP
RがANDゲート5から出力される。ANDゲート5の出力信
号ANDはカウンタ6のクロック端子CKに入力され、パル
ス数が計数される。
FIG. 1 shows an embodiment of the basic circuit configuration of the present invention. In the stepped rising edge of the reflected wave RF obtained by opening the far end of the transmission line 3 having the line length of the propagation delay time T, the first rising edge is a, and the second rising edge is b. The first and second rising edges a and b have a timing shift of 2T. Phase difference detection circuits S1 and S2 capable of controlling the threshold value of the input signal are provided. The phase difference detection circuit S1 compares the phase difference between the first rising edge a and the rising edge of the timing comparison pulse PR. For this purpose, both signals are applied as input signals to be measured to signal input terminals to be measured T 1 and T 1 ′, and reference level inputs R 11 and R 11 for determining an input signal threshold value.
The intermediate level of the first rising edge a and the intermediate level of the timing comparison pulse PR are set in R12. Similarly, in order to compare the phase difference between the second rising edge b and the rising edge of the timing comparison pulse PR, the phase difference detection circuit S2 determines that the two signals are input signals to be measured as signal input terminals T 2 ,
The intermediate level of the second rising edge b and the intermediate level of the timing comparison pulse PR are set to reference level inputs R21 and R22 which are added to T 2 'and determine the threshold value of the input signal.
The phase difference detection circuits S1 and S2 output a high level as positive phase shift information when the timing of the timing comparison pulse PR is delayed compared with the other timing, and as the negative phase shift information when the timing is opposite, NR that outputs low level
Z (Non-Return to Zero) phase difference information signal OUT + 1, OUT
+2 is output. Phase difference information signal OUT + 1 and OUT
+2 is exclusive-ORed by the EX-OR gate 4, and the timing comparison pulse PR and the output signal of the EX-OR gate 4
EOR is ANDed by the AND gate 5, and the timing comparison pulse P is output only when the output EOR of the EX-OR gate 4 is high.
R is output from the AND gate 5. The output signal AND of the AND gate 5 is input to the clock terminal CK of the counter 6, and the number of pulses is counted.

第2図は本発明の動作原理を説明するタイムチャート
である。反射波RFの繰り返しレートをf1,周期をT1
し、反射波RFとわずかに異なる繰り返しレートf1−Δf
と周期T1+ΔTにタイミング比較パルスPRを設定する。
反射波RFの第1の立上りエッジaとタイミング比較パル
スPRの立上りエッジの位相差を、反射波RFの第1の立上
りエッジa毎に位相差検出回路S1で、反射波RFの第2の
立上りエッジbとタイミング比較パルスPRの立上りの位
相差を反射波PFの第2の立上りエッジb毎に位相差検出
回路S2で各々検出し、第1及び第2の立上りエッジa,b
がタイミング比較パルスPRの立上りエッジよりもタイミ
ングが早いときのみ、位相差情報信号OUT+1,OUT+2と
して正の位相差を示すNRZのハイレベルがそれぞれ連続
して出力される。例えば、タイミング比較パルスPRのデ
ィューティレシオが50%であれば、位相差情報信号OUT
+1、及びOUT+2としてNRZのハイレベル信号が、T1
(T1+ΔT)/2ΔTを満す時間それぞれ連続して出力さ
れ、この時間内に出力されるタイミング比較パルスPRの
繰り返し回数Noは No=T1/2ΔT となる。従ってNoを求めれば時間分解能ΔTが次式のよ
うに求まる。
FIG. 2 is a time chart for explaining the operation principle of the present invention. The repetition rate of the reflected wave RF is f 1 and the period is T 1, and the repetition rate f 1 −Δf slightly different from the reflected wave RF
And the timing comparison pulse PR is set to the period T 1 + ΔT.
The phase difference between the first rising edge a of the reflected wave RF and the rising edge of the timing comparison pulse PR is determined by the phase difference detection circuit S1 for each first rising edge a of the reflected wave RF. A phase difference between the edge b and the rising edge of the timing comparison pulse PR is detected by the phase difference detection circuit S2 for each second rising edge b of the reflected wave PF, and the first and second rising edges a and b are detected.
Only when the timing is earlier than the rising edge of the timing comparison pulse PR, the NRZ high level indicating a positive phase difference is continuously output as the phase difference information signals OUT + 1 and OUT + 2. For example, if the duty ratio of the timing comparison pulse PR is 50%, the phase difference information signal OUT
+1, and OUT + 2 NRZ high-level signal of a, T 1 ·
Times satisfying (T 1 + ΔT) / 2ΔT are continuously output, and the number of repetitions No of the timing comparison pulse PR output within this time is No = T 1 / 2ΔT. Therefore, if No is determined, the time resolution ΔT is determined as in the following equation.

ΔT=T1/2No 第1図の基本回路構成において、第1及び第2の立上
りエッジa,bの入力しきい値を決める基準レベルR11,R21
のいずれかを反射波RFのハイレベル以上に設定すること
により、その位相差情報出力を常にローレベルに固定で
き、従って他方の位相差情報出力がハイレベルの間、タ
イミング比較パルスPRをカウンタで計数でき、繰り返し
回数Noが求まる。次に改めて基準レベレR11,R21を第1
及び第2の立上りエッジa,bの中間レベルに等しく設定
しなおすと、第1及び第2の立上りエッジa,bのタイミ
ングのずれに応じて位相差情報信号OUT+1とOUT+2の
出力タイミングにずれができる。位相差情報信号OUT+
1とOUT+2のいずれか一方だけがハイレベルのとき
に、カウンタ6はタイミング比較パルスPRを計数し、位
相差情報信号OUT+1,OUT+2の1周期内のタイミング比
較パルスPRの繰り返し計数回路Nと上式に示したΔTか
ら第1及び第2の立上りエッジa,b間のタイミング差2T
は 2T=N・ΔT/2 と計算でき、従って測定すべき伝送線路の伝搬遅延時間
Tは、 T=N・ΔT/4 で求まる。
ΔT = T 1 / 2No In the basic circuit configuration of FIG. 1, reference levels R11 and R21 for determining input threshold values of the first and second rising edges a and b.
By setting either of them to be higher than the high level of the reflected wave RF, the phase difference information output can always be fixed to the low level. Therefore, while the other phase difference information output is at the high level, the timing comparison pulse PR is output by the counter. It can be counted and the number of repetitions No is obtained. Next, the reference level R11 and R21 are first again
And the second rising edges a and b are set equal to the intermediate level, the output timings of the phase difference information signals OUT + 1 and OUT + 2 are shifted in accordance with the timing shift of the first and second rising edges a and b. it can. Phase difference information signal OUT +
When only one of OUT1 and OUT + 2 is at the high level, the counter 6 counts the timing comparison pulse PR, and the counter N and the repetition counting circuit N of the timing comparison pulse PR within one cycle of the phase difference information signals OUT + 1 and OUT + 2. The timing difference 2T between the first and second rising edges a and b from ΔT shown in FIG.
Can be calculated as 2T = N ・ ΔT / 2, so that the propagation delay time T of the transmission line to be measured can be obtained by T = N ・ ΔT / 4.

繰り返しレートは周期の逆数に等しいことから、反射
波RFとタイミング比較パルスPRの繰り返しレートの差分
Δfは以下のように表せる。
Since the repetition rate is equal to the reciprocal of the period, the difference Δf between the repetition rate of the reflected wave RF and the timing comparison pulse PR can be expressed as follows.

Δf=ΔT・f1 2/(ΔT.f1+1) 上式より、例えば被測定パルスの繰り返しレートが50
MHzであるとき、測定時間分解能ΔTとして1ps±0.001p
sを必要とする場合にはΔfを2499.875±2.5Hz程度に設
定すればよい。繰り返しレートは信号源としてシンセサ
イザを用いれば容易に1Hz程度の分解能と1×10-11/分
程度の短期安定度が得られることから、容易に高時間分
解能化が実現できる。
Δf = ΔT · f 1 2 /(ΔT.f 1 +1) From the above equation, for example, the repetition rate of the pulse to be measured is 50
When MHz, 1ps ± 0.001p as measurement time resolution ΔT
If s is required, Δf may be set to about 2499.875 ± 2.5 Hz. When a synthesizer is used as a signal source, the repetition rate can easily achieve a resolution of about 1 Hz and a short-term stability of about 1 × 10 −11 / minute, so that a high time resolution can be easily realized.

測定精度を支配する要因としてはタイミング比較パル
スPRの繰り返しレートの安定度と位相え差検出回路S1,S
2の検出分解能が考えられる。繰り返しレートの安定度
は上述したようにシンセサイザを用いることにより十分
得られる。
Factors governing the measurement accuracy include the stability of the repetition rate of the timing comparison pulse PR and the phase difference detection circuits S1, S
A detection resolution of 2 is possible. The stability of the repetition rate can be sufficiently obtained by using a synthesizer as described above.

位相差検出回路としては、第3図(a)に示すような
回路(特許出願中)を適用することにより、高分解能化
が実現できる。また、第3図(b)は第3図(a)に示
した回路の動作原理を説明するタイムチャートである。
これは被測定パルスP1とタイミング比較パルスPRを別個
にレベル規格化回路LV1,LV2で論理レベルを規格化し、
規格化された両信号の差分を差動増幅回路D1で直接増幅
し、増幅信号D±をデータ入力として、被測定パルスP1
の立上りエッジをもとにストローブパルス生成回路SBG
で生成したストローブパルスSBでラッチ回路L1にデータ
を取り込むものである。増幅信号D±は被測定パルスP
1,タイミング比較パルスPRのタイミングずれが生じてい
る間だけ、論理レベルがローもしくはハイに遷移し、そ
れ以外は中間レベルとなるので、ラッチ回路L1に与える
データ入力の極性を適当に選べば、被測定パルスP1の立
上りタイミングがタイミング比較パルスPRのそれより早
いとき、即ち正の位相ずれのときだけ、ラッチ回路L1の
出力Qにハイレベルを出力させることができる。検出分
解能は差動増幅回路の過渡応答時の増幅率と全回路を構
成するトランジスタのスイッチング速度で決まり、高速
Siバイポーラプロセス技術を用いることにより数psの時
間分解能が容易に実現できる。従って、測定時間分解能
と時間精度がともにpsオーダの伝送線路長測定装置が本
発明によって実現できる。
By applying a circuit (patent pending) as shown in FIG. 3 (a) as the phase difference detection circuit, high resolution can be realized. FIG. 3B is a time chart for explaining the operation principle of the circuit shown in FIG. 3A.
This is to standardize the logic level of the measured pulse P1 and the timing comparison pulse PR separately with the level normalization circuits LV1 and LV2,
The difference between the standardized signals is directly amplified by the differential amplifier circuit D1, and the amplified signal D
Pulse generator SBG based on the rising edge of
The data is taken into the latch circuit L1 by the strobe pulse SB generated in step (1). The amplified signal D ± is the measured pulse P
1.The logic level shifts to low or high only during the timing shift of the timing comparison pulse PR, and the logic level changes to an intermediate level otherwise, so if the polarity of the data input given to the latch circuit L1 is appropriately selected, Only when the rising timing of the measured pulse P1 is earlier than that of the timing comparison pulse PR, that is, when there is a positive phase shift, the output Q of the latch circuit L1 can be made to output a high level. The detection resolution is determined by the amplification factor during the transient response of the differential amplifier circuit and the switching speed of the transistors that make up the entire circuit.
Time resolution of several ps can be easily realized by using Si bipolar process technology. Therefore, a transmission line length measuring device having both the measurement time resolution and the time accuracy on the order of ps can be realized by the present invention.

(発明の効果) 以上の説明から明らかな如く、本発明によれば、遠端
開放の伝送線路にパルスを送出して得られる反射波形か
ら伝送線路長を測定する伝送線路長測定装置において、
一定の繰り返し周期を有する反射波、及び該反射波とは
繰り返し周期がわずかに異なるタイミング比較パルス信
号を共通の被測定入力信号とし、該被測定入力信号しき
い値の制御が可能で、かつ該被測定入力信号間の位相極
性に応じて論理レベルが変化する位相差情報信号を出力
する、独立した2つの位相差検出回路と、該2つの位相
差検出回路の位相差情報信号が一致していない間のみ、
前記タイミング比較パルス信号の分岐信号を通過させる
ゲート回路と、該ゲート回路の出力信号パルス数を計数
するカウントとを備えることにより、従来のように高精
度,高時間分解能な基準タイミング信号発生器や複雑な
発振制御回路を必要とせず、短時間で高精度かつ高時間
分解能な伝送線路長(伝搬遅延時間)の測定を実現する
ことができる。
(Effects of the Invention) As is apparent from the above description, according to the present invention, in a transmission line length measuring apparatus for measuring a transmission line length from a reflected waveform obtained by transmitting a pulse to a transmission line open at the far end,
A reflected wave having a constant repetition period, and a timing comparison pulse signal whose repetition period is slightly different from the reflected wave are used as a common input signal to be measured, and the threshold value of the input signal to be measured can be controlled, and Two independent phase difference detection circuits that output a phase difference information signal whose logic level changes in accordance with the phase polarity between the input signals to be measured, and the phase difference information signals of the two phase difference detection circuits match. Only during the absence
By providing a gate circuit for passing the branch signal of the timing comparison pulse signal and a count for counting the number of output signal pulses of the gate circuit, a reference timing signal generator having high accuracy and high time resolution as in the related art can be provided. The measurement of the transmission line length (propagation delay time) with high accuracy and high time resolution can be realized in a short time without requiring a complicated oscillation control circuit.

【図面の簡単な説明】 第1図は本発明における伝送線路長測定装置の基本回路
構成の一実施例を示す機能ブロック図、第2図は本発明
における伝送線路長測定装置の動作原理を示すタイムチ
ャート、第3図(a)及び(b)は本発明の一構成要素
である位相差検出回路に適用可能な回路構成の一実施例
を示す回路ブロック図及び同回路のタイムチャート、第
4図は従来技術の一実施例を示す機能ブロック図であ
る。 1……被試験回路、2……入出力ピン、3……伝送線
路、4……EX−ORゲート、5……ANDゲート、6……カ
ウンタ、T……伝搬遅延時間、DR……試験パルス発生回
路、RF……反射波、a……第1の立上りエッジ、b……
第2の立上りエッジ、PR……タイミング比較パルス、S
1,S2……位相差検出回路、R11,R12,R21,R22……入力信
号基準レベル、OUT+1,OUT+2……位相差情報信号、EO
R……EX−ORゲートの出力、AND……ANDゲートの出力、C
K……クロック入力端子、LV1,LV2……レベル規格化回
路、D1……差動増幅回路、D±……差動増幅信号、SBG
……ストローブパルス生成回路、SB……ストローブパル
ス、L1……ラッチ回路、Q……ラッチ回路出力信号、RT
G……基準タイミング信号発生回路、SD……試験結果判
定回路、RV……しきい値レベル入力。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional block diagram showing one embodiment of a basic circuit configuration of a transmission line length measuring device according to the present invention, and FIG. 2 shows an operation principle of the transmission line length measuring device according to the present invention. FIGS. 3 (a) and 3 (b) are a circuit block diagram showing an embodiment of a circuit configuration applicable to a phase difference detection circuit which is one component of the present invention, and FIGS. FIG. 1 is a functional block diagram showing one embodiment of the prior art. 1 ... circuit under test, 2 ... input / output pins, 3 ... transmission line, 4 ... EX-OR gate, 5 ... AND gate, 6 ... counter, T ... propagation delay time, DR ... test Pulse generating circuit, RF: reflected wave, a: first rising edge, b:
2nd rising edge, PR: timing comparison pulse, S
1, S2: phase difference detection circuit, R11, R12, R21, R22: input signal reference level, OUT + 1, OUT + 2: phase difference information signal, EO
R: Output of EX-OR gate, AND: Output of AND gate, C
K: Clock input terminal, LV1, LV2: Level normalizing circuit, D1: Differential amplifier circuit, D ±: Differential amplified signal, SBG
…… Strobe pulse generation circuit, SB …… Strobe pulse, L1… Latch circuit, Q… Latch circuit output signal, RT
G: Reference timing signal generation circuit, SD: Test result judgment circuit, RV: Threshold level input.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】遠端開放の伝送線路にパルスを送出して得
られる反射波形から伝送線路長を測定する伝送線路長測
定装置において、一定の繰り返し周期を有する反射波、
及び該反射波とは繰り返し周期がわずかに異なるタイミ
ング比較パルス信号を共通の被測定入力信号とし、該被
測定入力信号しきい値の制御が可能で、かつ該被測定入
力信号間の位相極性に応じて論理レベルが変化する位相
差情報信号を出力する、独立した2つの位相差検出回路
と、該2つの位相差検出回路の位相差情報信号が一致し
ていない間のみ、前記タイミング比較パルス信号の分岐
信号を通過させるゲート回路と、該ゲート回路の出力信
号パルス数を計数するカウントとを備えてなることを特
徴とする伝送線路長測定装置。
A transmission line length measuring device for measuring a transmission line length from a reflection waveform obtained by transmitting a pulse to a transmission line having an open end, wherein a reflected wave having a constant repetition period;
And a timing comparison pulse signal whose repetition cycle is slightly different from the reflected wave is used as a common input signal to be measured, the threshold value of the input signal to be measured can be controlled, and the phase polarity between the input signals to be measured is Two independent phase difference detection circuits for outputting a phase difference information signal whose logic level changes according to the timing comparison pulse signal only when the phase difference information signals of the two phase difference detection circuits do not match. A transmission line length measuring device, comprising: a gate circuit for passing the branch signal of the above; and a count for counting the number of output signal pulses of the gate circuit.
JP30932687A 1987-12-07 1987-12-07 Transmission line length measuring device Expired - Lifetime JP2571082B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30932687A JP2571082B2 (en) 1987-12-07 1987-12-07 Transmission line length measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30932687A JP2571082B2 (en) 1987-12-07 1987-12-07 Transmission line length measuring device

Publications (2)

Publication Number Publication Date
JPH01150877A JPH01150877A (en) 1989-06-13
JP2571082B2 true JP2571082B2 (en) 1997-01-16

Family

ID=17991669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30932687A Expired - Lifetime JP2571082B2 (en) 1987-12-07 1987-12-07 Transmission line length measuring device

Country Status (1)

Country Link
JP (1) JP2571082B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5321632A (en) * 1991-02-26 1994-06-14 Nippon Telegraph And Telephone Corporation Method and apparatus for measuring the length of a transmission line in accordance with a reflected waveform
ES2459622T3 (en) * 2008-12-03 2014-05-12 Abb Research Ltd. Procedure and system for measuring the length of a power line
WO2026083586A1 (en) * 2024-10-18 2026-04-23 Ntt株式会社 Communication delay measurement device and communication delay measurement method

Also Published As

Publication number Publication date
JPH01150877A (en) 1989-06-13

Similar Documents

Publication Publication Date Title
US8988081B2 (en) Determining propagation delay
JPH04320982A (en) Semiconductor electronic circuit
JPH08297177A (en) Time interval measurement circuit
EP0909957A2 (en) Measuring signals in a tester system
EP1148340B1 (en) All digital built-in self-test circuit for phase-locked loops
JP2571082B2 (en) Transmission line length measuring device
US6349267B1 (en) Rise and fall time measurement circuit
US6944099B1 (en) Precise time period measurement
JPH0342810B2 (en)
JPS6199415A (en) Frequency counter device
US5754063A (en) Method and apparatus to measure internal node timing
JP3516778B2 (en) Frequency measurement method for semiconductor test equipment
JP2853752B2 (en) Transmission line length measuring device
KR101100756B1 (en) Skew coincidence output circuit
EP0053487B1 (en) Test apparatus for signal timing measurement
EP1226447A2 (en) High resolution skew detection apparatus and method
CN219799775U (en) Receiving and transmitting integrated time measurement circuit
JP2947178B2 (en) Clock skew judgment circuit
JP2591849B2 (en) Test circuit
JPH0566236A (en) Skew detecting circuit
EP0122984A1 (en) Time measuring circuit
KR200273009Y1 (en) High precision test pattern generator
JPH01143978A (en) Delay time measuring circuit
JPH06138261A (en) Time interval measuring device
SU1709234A1 (en) Digital phasemeter

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071024

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081024

Year of fee payment: 12

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081024

Year of fee payment: 12