JP2571389B2 - Stacked hybrid integrated circuit components - Google Patents
Stacked hybrid integrated circuit componentsInfo
- Publication number
- JP2571389B2 JP2571389B2 JP62221028A JP22102887A JP2571389B2 JP 2571389 B2 JP2571389 B2 JP 2571389B2 JP 62221028 A JP62221028 A JP 62221028A JP 22102887 A JP22102887 A JP 22102887A JP 2571389 B2 JP2571389 B2 JP 2571389B2
- Authority
- JP
- Japan
- Prior art keywords
- laminated
- integrated circuit
- component
- hybrid integrated
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000003990 capacitor Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 10
- 239000000696 magnetic material Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000000919 ceramic Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910000859 α-Fe Inorganic materials 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Coils Or Transformers For Communication (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、積層体よりなる基板上に半導体部品を設け
てなる積層型混成集積回路部品に関する。Description: TECHNICAL FIELD The present invention relates to a laminated hybrid integrated circuit component in which a semiconductor component is provided on a substrate made of a laminate.
（従来の技術） 従来の半導体集積回路部品は、例えば第12図において
ベアチップ搭載型のものについて示すように、セラミッ
クあるいは樹脂でなる基板１上にベアチップ２を実装
し、リード線３により端子４とベアチップ２とを接続し
てなる。そして、周辺回路を構成するインダクタやコン
デンサ等は、この半導体集積回路部品を搭載するプリン
ト基板（図示せず）に別に実装している。なお、５はベ
アチップ２やリード線３を覆うように設けられた保護体
であり、セラミックにより作成したカバーをガラス等で
接着することにより、あるいは樹脂をモールドする等の
手段により設けられたものである。(Prior Art) As a conventional semiconductor integrated circuit component, a bare chip 2 is mounted on a substrate 1 made of ceramic or resin, as shown in FIG. It is connected to the bare chip 2. The inductors and capacitors constituting the peripheral circuit are separately mounted on a printed circuit board (not shown) on which the semiconductor integrated circuit components are mounted. Reference numeral 5 denotes a protective body provided so as to cover the bare chip 2 and the lead wire 3 and is provided by bonding a cover made of ceramic with glass or the like, or by molding resin. is there.
上記構成以外に、従来の半導体集積回路部品として、
例えば特開昭59−178768号公報において開示されている
ように、コンデンサネットワークを内蔵する積層誘電体
基板上に集積回路チップを取付け、モールド等により被
覆したものがある。In addition to the above configuration, as a conventional semiconductor integrated circuit component,
For example, as disclosed in JP-A-59-178768, an integrated circuit chip is mounted on a laminated dielectric substrate having a built-in capacitor network and covered with a mold or the like.
（発明が解決しようとする問題点） このように、従来の半導体集積回路部品においては、
基板１はセラミックあるいは樹脂により構成され、ベア
チップを実装し、保護する役目しか有していないため、
周辺回路等を構成するインダクタやコンデンサ等を該プ
リント基板上に実装する必要があり、このため、高密度
化を要求する需要に対しては十分に満足できない場合が
あった。(Problems to be Solved by the Invention) As described above, in the conventional semiconductor integrated circuit component,
Since the substrate 1 is made of ceramic or resin, and has only a role of mounting and protecting a bare chip,
It is necessary to mount an inductor, a capacitor, and the like that constitute a peripheral circuit and the like on the printed circuit board. Therefore, there is a case where the demand for high density is not sufficiently satisfied.
また、特開昭59−178768号公報において開示されてい
るものにおいては、回路構成上、インダクタやトランス
を必要とする場合、チップ部品としてのインダクタ等を
基板上に搭載することが必要となり、高密度化、小形化
の面において不十分であった。In the circuit disclosed in JP-A-59-178768, when an inductor or a transformer is required in the circuit configuration, it is necessary to mount an inductor or the like as a chip component on a substrate. It was insufficient in terms of density and miniaturization.
本発明の目的は、回路構成上、インダクタやトランス
を必要とする場合においても、高密度化、小形化が達成
できる構成の積層型混成集積回路部品を提供することに
ある。An object of the present invention is to provide a laminated hybrid integrated circuit component having a configuration that can achieve high density and downsizing even when an inductor or a transformer is required in the circuit configuration.
（問題点を解決するための手段） 本発明は、上記目的を達成するため、電気絶縁性磁性
体層とコイル形成用導電体層とを積層した積層部品と、
誘電体層とコンデンサ電極用導電体層を積層した積層部
品とを一体に重畳した積層体により基板を構成し、該基
板上に半導体部品を設けたことを特徴とする。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a laminated component in which an electrically insulating magnetic layer and a coil-forming conductor layer are laminated,
A substrate is constituted by a laminate in which a dielectric component and a laminate component in which a capacitor electrode conductor layer is laminated are integrally superposed, and a semiconductor component is provided on the substrate.
（作用） 本発明においては、積層体内にLC部品が一体に内蔵さ
れ、その上に半導体部品が設けられるため、Ｌ素子、Ｃ
素子が縦並びに重ねられると共に、半導体部品も縦並び
に重ねられて高密度化、小形化が達成され、さらにイン
ダクタを必要とする回路構成においても、インダクタを
別部品として基板に搭載する必要がなく、高密度化、小
形化が達成される。(Function) In the present invention, since the LC component is integrally built in the laminate and the semiconductor component is provided thereon, the L element, the C
As the elements are stacked vertically, the semiconductor components are also stacked vertically, achieving high density and miniaturization, and even in a circuit configuration requiring an inductor, there is no need to mount the inductor as a separate component on the board, High density and miniaturization are achieved.
（実施例） 以下本発明の詳細を図面により説明する。第１図ない
し第４図はボンディング型（積層型混成集積回路部品を
搭載する別のプリント基板上の導電パターンに半田付け
等により接続される端子4Aを、積層体よりなる基板の裏
面側へ曲成してなる型）の積層型混成集積回路部品に本
発明を適用した一実施例であり、該実施例の積層体より
なる基板６は、コイルを内部に形成した積層部品6Aと、
コンデンサを内部に形成した積層部品6Bとを、一体焼成
あるいは接着等により一体に重ねて構成している。ま
た、第１図ないし第４図において、第12図と同じ符号は
同じ構成部材を示す。(Example) Hereinafter, the details of the present invention will be described with reference to the drawings. FIGS. 1 to 4 show a bonding type (a terminal 4A connected by soldering or the like to a conductive pattern on another printed circuit board on which a laminated hybrid integrated circuit component is mounted is bent toward the back side of a substrate made of a laminated body. This is an embodiment in which the present invention is applied to a laminated hybrid integrated circuit component of the type described above. The substrate 6 made of the laminated body of this embodiment includes a laminated component 6A having a coil formed therein,
A multilayer component 6B having a capacitor formed therein is integrally laminated by integral firing or bonding. 1 to 4, the same reference numerals as those in FIG. 12 denote the same components.
コイルを形成した積層部品6Aは、半導体部品を支持
し、保護するという基板としての役目のみならず、イン
ダクタをも構成し（トランスを構成する場合もあ
る。）、第２図および第３図に示すように、絶縁性磁性
体であるフェライト７内にコイル状の導電体８を形成し
てなるもので、そのコイル状導電体８の一端を端子4Aの
１つに接続し、他端を別の端子4Aの１つに接続してい
る。このような構造は、電気絶縁性の高い磁性フェライ
ト粉をペースト化し、また、コイル形成用の金属粉をバ
インダーによりペースト化し、これらのペーストを印刷
法により交互に印刷することにより積層し、焼成する
か、あるいはシート状磁性体７と導電体８として金属箔
パターンとを交互に接着し積層する（特開昭60−176207
号）か、もしくは積層後に高温焼成する（特開昭60−17
6208号）等の工程により製造される。また、コンデンサ
を形成した積層部品6Bは、第２図および第４図に示すよ
うに、前記と同様の工程により、誘電体９と導電体10と
を交互に形成し、導電体10は１つおきに１つの端子4Aに
共通に接続し、残りの導電体10を別の端子4Aに共通に接
続してなる。The laminated component 6A in which the coil is formed not only serves as a substrate for supporting and protecting the semiconductor component but also constitutes an inductor (in some cases, constitutes a transformer), and is shown in FIGS. 2 and 3. As shown, a coil-shaped conductor 8 is formed in a ferrite 7 which is an insulating magnetic material. One end of the coil-shaped conductor 8 is connected to one of the terminals 4A, and the other end is separated. Connected to one of the terminals 4A. In such a structure, a magnetic ferrite powder having a high electrical insulation property is converted into a paste, and a metal powder for forming a coil is converted into a paste with a binder. Alternatively, a sheet-like magnetic body 7 and a metal foil pattern as a conductor 8 are alternately bonded and laminated (Japanese Patent Laid-Open No. 60-176207).
No.) or baking at a high temperature after lamination (JP-A-60-17)
No. 6208). In addition, as shown in FIGS. 2 and 4, the laminated component 6B on which the capacitor is formed is formed by alternately forming the dielectrics 9 and the conductors 10 by the same process as described above. Every other terminal is commonly connected to one terminal 4A, and the remaining conductors 10 are commonly connected to another terminal 4A.
第５図は、端子４の導電パターンとの接続部を水平に
外側に曲成してなるフラットパッケージ型のものに本発
明を適用した例であり、積層体よりなる基板６は前記同
様の積層部品6A,6Bを一体に積層して構成されたもので
ある。FIG. 5 shows an example in which the present invention is applied to a flat package type in which a connection portion of a terminal 4 with a conductive pattern is bent horizontally outward. The components 6A and 6B are integrally laminated.
本発明の構造は、上述のようなチップ搭載型の積層型
混成集積回路部品のみならず、第６図および第７図に示
すように、半導体集積回路部品11をはんだ付けし、搭載
したボンディング型の積層型混成集積回路部品にも適用
できる。すなわち、半導体集積回路部品11を搭載した積
層体よりなる基板６として前述のコイル、コンデンサを
それぞれ構成した積層部品6A,6Bの積層体を用いること
ができる。The structure of the present invention is not limited to the above-described chip-mounted laminated hybrid integrated circuit component, but also, as shown in FIGS. 6 and 7, the semiconductor integrated circuit component 11 is soldered and mounted. Of the present invention can also be applied to the laminated hybrid integrated circuit parts of the above. That is, as the substrate 6 composed of the laminated body on which the semiconductor integrated circuit component 11 is mounted, a laminated body of the laminated parts 6A and 6B each constituting the above-described coil and capacitor can be used.
第８図はさらに本発明の応用例を示すもので、片面実
装型の積層型混成集積回路部品について示している。こ
の応用例においては、前記基板６の表面にベアチップ
２、チップダイオード12、タンタルコンデンサ13および
チップトランジスタ14等を実装してなり、主表面（表面
および／または裏面）にはこれら実装部品の配線パター
ンと共に抵抗パターン（図示せず）を印刷により形成し
ている。FIG. 8 further shows an application example of the present invention, showing a single-sided mounting type laminated hybrid integrated circuit component. In this application example, a bare chip 2, a chip diode 12, a tantalum capacitor 13, a chip transistor 14, and the like are mounted on the surface of the substrate 6, and the wiring pattern of these mounted components is provided on the main surface (front and / or back). At the same time, a resistance pattern (not shown) is formed by printing.
さらに、第９図および第10図は両面実装型の積層型混
成集積回路部品に関する本発明の応用例であり、前記積
層体よりなる基板６の表面にベアチップ２を実装し、裏
面に前記チップダイオード12、タンタルコンデンサ13お
よびチップトランジスタ14等を実装してなり、かつ主表
面（表面および／または裏面）にはこれら実装部品の配
線パターンと共に抵抗パターン（図示せず）を印刷によ
り形成したものである。9 and 10 show an application example of the present invention relating to a double-sided type laminated hybrid integrated circuit component, in which a bare chip 2 is mounted on the surface of a substrate 6 made of the laminated body, and the chip diode is mounted on the back surface. 12, a tantalum capacitor 13, a chip transistor 14, etc. are mounted, and a resistance pattern (not shown) is formed on the main surface (front surface and / or back surface) together with a wiring pattern of these mounted components by printing. .
また、第11図は、積層型混成集積回路部品に形成され
る周辺回路の一例を示すもので、L,Cはそれぞれ前記積
層部品6A,6Bに形成されるインダクタおよびコンデンサ
（ただし、前記の例と異なり、インダクタおよびコンデ
ンサが複数個ずつ形成される。）であり、Ｒは積層体よ
りなる基板６の主表面（表面および／または裏面）にこ
れら実装部品用の配線パターンと共に形成された抵抗パ
ターン、C+は基板上に実装されたチップ状の電解コンデ
ンサ、14はチップトランジスタである。FIG. 11 shows an example of a peripheral circuit formed on the laminated hybrid integrated circuit component. L and C are inductors and capacitors formed on the laminated components 6A and 6B, respectively. R is a resistance pattern formed on the main surface (front surface and / or back surface) of the substrate 6 made of a laminate together with the wiring patterns for these mounted components. , C + denotes a chip-shaped electrolytic capacitor mounted on a substrate, and 14 denotes a chip transistor.
本発明において、積層部品6A,6Bは、複数重ねて一体
化したものとして構成することも可能である。また、特
に図示しないが、積層部品上に搭載する半導体部品およ
び／またはその他の部品（抵抗層を含む）の接続部分以
外の導体パターン（回路パターン）および抵抗層をガラ
ス層等により絶縁、保護する場合もある。In the present invention, the multilayer components 6A and 6B may be configured as a plurality of integrated components. Although not particularly shown, a conductor pattern (circuit pattern) and a resistance layer other than a connection portion of a semiconductor component and / or other components (including a resistance layer) mounted on the laminated component are insulated and protected by a glass layer or the like. In some cases.
（発明の効果） 以上述べたように、本発明においては、半導体部品を
搭載する基板をコンデンサのみならずインダクタあるい
はトランスとして利用できる構成としたので、IC等の半
導体部品とその周辺のＬ、Ｃ混成回路を一体に構成で
き、従来品のように、インダクタ等を別部品として基板
に実装する必要がなく、従来品より高密度化、小形化が
達成できる。(Effects of the Invention) As described above, in the present invention, the substrate on which the semiconductor component is mounted is configured to be used not only as a capacitor but also as an inductor or a transformer. The hybrid circuit can be integrally formed, and it is not necessary to mount an inductor or the like as a separate component on the substrate as in the conventional product, and it is possible to achieve higher density and smaller size than the conventional product.
第１図は本発明によるベアチップ搭載型の積層型混成集
積回路部品の一実施例を示す斜視図、第２図は該実施例
の断面図、第３図および第４図はそれぞれ該実施例のコ
イル形成部分、コンデンサ形成部分を示す平面図、第５
図は本発明によるベアチップ搭載型の積層型混成集積回
路部品の他の例を示す斜視図、第６図および第７図はフ
ラット半導体部品を搭載した本発明による積層型混成集
積回路部品の例をそれぞれ示す斜視図、第８図はベアチ
ップを搭載した本発明による片面実装型の積層型混成集
積回路部品の応用例を示す斜視図、第９図はベアチップ
を搭載した本発明による両面実装型の積層型混成集積回
路部品の応用例を示す斜視図、第10図は第９図の側面
図、第11図は本発明を適用した回路の一例を示す回路
図、第12図は従来の半導体集積回路部品を示す斜視図で
ある。FIG. 1 is a perspective view showing an embodiment of a laminated hybrid integrated circuit component mounted on a bare chip according to the present invention, FIG. 2 is a cross-sectional view of the embodiment, and FIGS. 5 is a plan view showing a coil forming portion and a capacitor forming portion, and FIG.
FIG. 6 is a perspective view showing another example of a laminated hybrid integrated circuit component of a bare chip mounting type according to the present invention. FIGS. 6 and 7 show examples of a laminated hybrid integrated circuit component according to the present invention mounted with flat semiconductor components. FIG. 8 is a perspective view showing an application example of a single-sided mounting type laminated hybrid integrated circuit component according to the present invention having a bare chip mounted thereon, and FIG. 9 is a double-sided mounting type laminating according to the present invention having a bare chip mounted thereon. FIG. 10 is a side view of FIG. 9, FIG. 11 is a circuit diagram showing an example of a circuit to which the present invention is applied, and FIG. 12 is a conventional semiconductor integrated circuit. It is a perspective view which shows a component.
Claims (1)
層とを積層した積層部品と、誘電体層とコンデンサ電極
用導電体層を積層した積層部品とを一体に重畳した積層
体により基板を構成し、該基板上に半導体部品を設けた
ことを特徴とする積層型混成集積回路部品。1. A laminate in which a laminated component in which an electrically insulating magnetic material layer and a conductor layer for coil formation are laminated, and a laminated component in which a dielectric layer and a conductor layer for a capacitor electrode are laminated are integrally superposed. A laminated hybrid integrated circuit component comprising a substrate and a semiconductor component provided on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62221028A JP2571389B2 (en) | 1987-09-03 | 1987-09-03 | Stacked hybrid integrated circuit components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62221028A JP2571389B2 (en) | 1987-09-03 | 1987-09-03 | Stacked hybrid integrated circuit components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6464240A JPS6464240A (en) | 1989-03-10 |
| JP2571389B2 true JP2571389B2 (en) | 1997-01-16 |
Family
ID=16760354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62221028A Expired - Lifetime JP2571389B2 (en) | 1987-09-03 | 1987-09-03 | Stacked hybrid integrated circuit components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2571389B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555532U (en) * | 1991-12-24 | 1993-07-23 | 太陽誘電株式会社 | Multilayer LC filter |
| WO2007049788A1 (en) | 2005-10-28 | 2007-05-03 | Hitachi Metals, Ltd. | Dc-dc converter |
| CN121312327A (en) * | 2023-06-13 | 2026-01-09 | 株式会社村田制作所 | Electronic circuit devices and their manufacturing methods |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710960A (en) * | 1980-06-24 | 1982-01-20 | Fujitsu Ltd | Semiconductor package |
| JPS58187128A (en) * | 1982-04-26 | 1983-11-01 | 株式会社藤沢製作所 | Mixer for making confectionery |
| JPS5976455A (en) * | 1982-10-26 | 1984-05-01 | Tdk Corp | Hybrid integrated circuit |
| JPS5994856A (en) * | 1982-11-24 | 1984-05-31 | Matsushita Electric Ind Co Ltd | Composite circuit device and mounting method thereof |
| JPS59178768A (en) * | 1983-03-30 | 1984-10-11 | Tdk Corp | Composite component parts |
| JPS60244097A (en) * | 1984-05-18 | 1985-12-03 | ティーディーケイ株式会社 | Hybrid electronic circuit |
| JPS6132785U (en) * | 1984-07-27 | 1986-02-27 | ティーディーケイ株式会社 | Stacked hybrid integrated DC/DC converter |
-
1987
- 1987-09-03 JP JP62221028A patent/JP2571389B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6464240A (en) | 1989-03-10 |
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