JP2573464B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Generally, in a semiconductor memory device of this type, that is, a memory cell of an EEPROM, electrons are injected into a floating gate through an oxide film of about 100 angstroms, which is much thinner than a gate oxide film. The data is rewritten by releasing the data. FIG.
4 is a symbol diagram of a cell transistor constituting such a memory cell. The control gate voltage is V _CG , the drain voltage is V _D , the source voltage is V _S , and the drain current is I.
_Assuming that _D , the drain current _{ID with} respect to the control gate voltage _VCG exhibits characteristics as shown in FIG. In FIG. 15, a curve 11 is a characteristic in an initial state, and a curve 12 is a characteristic when electrons are injected into the floating gate. The threshold voltage is increased by the injection of electrons. Further, a curve 13 shows a characteristic in a state where electrons are emitted from the floating gate, and the threshold voltage is lowered due to the emission of electrons and becomes negative. In a memory cell using such a cell transistor, data “0” and “1” are stored using the characteristics of the curves 12 and 13.

FIG. 16 shows an EEPRO having the cell transistors shown in FIG. 14 arranged in a matrix.
M shows an example of the circuit configuration of the EE which is currently commercially available.
PROM has many such circuit configurations. As shown
A selection MOS transistor ST is connected in series to each cell transistor CT, and one memory cell 14 is composed of two transistors CT and ST.

In the above configuration, when electrons are injected into the floating gate of the cell transistor CT, the gate of the selection transistor ST and the cell transistor C
The high voltages V _G and V _CG are applied to the control gate of T, and the column line 15 is set to 0V. On the other hand, when emitting electrons, the gate of the selection transistor ST and the column line 15 are set to a high voltage, and the control gate of the cell transistor CT is set to 0V. As a result, a high voltage is applied to the drain of the cell transistor CT, and electrons are emitted from the floating gate to the drain.

FIG. 17A is a pattern plan view of a region 16 surrounded by a chain line in the circuit shown in FIG.
FIG. 1 shows a cross-sectional configuration along the line AA ′ in FIG.
This is shown in FIG. 17A and 17B, portions corresponding to those in FIG. 16 are denoted by the same reference numerals, 17 is a source region of the cell transistor CT, 18 is a drain of the cell transistor CT, and 18 of the selection transistor ST. A source region, 19 is a drain region of the selection transistor ST,
20 is a floating gate of the cell transistor CT, 21 is a control gate of the cell transistor CT, and 22 is a selection transistor S.
The gate of T, 23 is a thin oxide film portion, and 24 is a contact portion between the column line 15 and the selection transistor ST.

However, in the above-described configuration, since one memory cell is formed by two transistors,
There is a disadvantage that the memory cell size increases and the chip cost also increases. For this reason, an ultraviolet-erasable nonvolatile semiconductor memory device that can form one memory cell with one transistor, that is, a so-called UVEPROM, has attracted attention. U
In a VEPROM, one memory cell is formed of only one transistor, so that a chip having the same area can obtain twice the capacity of an EEPROM, and a chip having the same memory size (capacity) requires a smaller chip size. E
The penetration rate is higher than EPROM. However, UVE
A PROM requires a large current because a current flows through a channel when electrons are injected into a memory cell, and hot electrons are generated near a drain and injected into a floating gate. For this reason, an external power supply for programming is required. On the other hand, since the above-mentioned EEPROM emits and injects electrons from the floating gate using the tunnel effect, data can be written at a high voltage from a booster circuit provided in the chip. Therefore, there is an advantage that a single power supply of 5 V can be used.

As described above, the EEPROM and the UVEPRO
M has advantages and disadvantages. However, if the memory size of the EEPROM can be reduced to a size similar to that of the UVEPROM and the cost can be reduced, it can be said that it can be used with a single power supply of 5 V, so that it is easy for users to use.

[0008]

As described above, despite the advantage that the conventional EEPROM can be operated with a single power supply, there is a problem that the memory cell size is larger and the cost is higher than the UVEPROM. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a nonvolatile memory capable of reducing the size of a memory cell and reducing the cost while electrically rewriting data. To provide a nonvolatile semiconductor memory device.

[0010]

That is, in the nonvolatile semiconductor memory device according to the first aspect, each of the nonvolatile semiconductor memory devices has a control gate,
The floating gate and between the floating gate and the channel region
Thickness that can cause a tunnel effect
A plurality of cell transformers having an edge film and current paths connected in series
Transistor and a plurality of these cell transistors connected in series.
Connected to one end of the
Selection transistor for selecting cell transistors at once
Memory cell with a selector
Individually select multiple cell transistors selected together
And latch means for latching write data
And the write data latched by the latch means
The cell transformer selected by the selection means based on the
The selection transistor is connected to one end of the current path of the transistor.
Applying a voltage corresponding to the write data via
Injection of electrons into the floating gate via the insulating film
Or write to program by releasing
Means .

[0011] The nonvolatile semiconductor memory device according to claim 2, one
An end is connected to a column line and a gate is connected to a first row line.
Selection transistor and the other end of the selection transistor
Connected in series with the reference potential, each with a control gate, floating
The free gate, and between the floating gate and the channel region
Insulation with thickness enough to cause tunnel effect
A plurality of films, each having a film, and a second row line connected to the control gate.
Memory cell consisting of cell transistors is matrix
Cell array arranged in a shape and each of the above memory cells
Cell Transistor and Selection Transistor Constituting
Through the second row line and the first row line, respectively.
A row decoder for supplying a decode signal to the memory cell;
Means for latching write data for each column of the array
And writing for one row latched by the latch means.
Selected by the row decoder based on the data
By applying a voltage corresponding to the write data to one end of the current path of the cell transistor , the selected cell
Writing means for performing programming by injecting or emitting electrons into the floating gate of the transistor through the insulating film.

According to a third aspect of the present invention, there is provided a nonvolatile semiconductor memory device, wherein one end is connected to a column line and a gate is connected to a first row line; And a control gate, a floating gate, and an insulating film having a thickness capable of causing a tunnel effect provided on the entire surface between the floating gate and the channel region. A memory cell array in which memory cells each including a plurality of cell transistors connected to the second row line are arranged in a matrix ;
Array dividing the memory cell array into a plurality of blocks
Select the split transistor and this array split transistor.
Memo to program by selectively controlling conduction
A column decoder for specifying a block of a recell; a row decoder for supplying a decode signal to the cell transistor and the selection transistor constituting each of the memory cells via the second row line and the first row line, respectively; Above row
A current path of a cell transistor selected by the row decoder in a block specified by the decoder;
Write means for applying a voltage corresponding to the write data to one end of the cell transistor to inject or emit electrons to the floating gate of the selected cell transistor through the insulating film, thereby performing programming . memory
It is characterized in that programming is performed in units of cell blocks .

[0013]

According to the above configuration, since the selection transistor can be shared by a plurality of cell transistors, the memory cell can be formed by almost one cell transistor, and the cell size can be reduced and the cost can be reduced. .

[0014]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a memory cell section and its peripheral circuit section. An output D of a data input circuit 25 is supplied to the gate of an N-channel MOS transistor 26 whose one end is connected to a high voltage power supply Vp. A selection transistor S is connected between the other end of the transistor 26 and a ground point (reference potential).
T and cell transistors CT1 to CT4 are connected in series. A signal X1 for selecting the cell transistors CT1 to CT4 is supplied to the gate of the selection transistor ST, and the control gates of the cell transistors CT1 to CT4 are respectively connected to the cell transistors CT1 to CT4.
Signals W1 to W4 for selecting .about.CT4 are supplied. At the connection point (node N1) between the transistor 26 and the selection transistor ST, "1" level is set at the time of reading.
One end of an N-channel MOS transistor 27, which is controlled to be conductive by a signal R which becomes "0" level at the time of programming, is connected, and the other end of the transistor 27 is connected to an input end of a data detection circuit 28. A P-channel MOS transistor 29 whose gate is connected to the node N2 is connected between the input side node N2 of the data detection circuit 28 and the power supply V.
Are connected as a load at the time of reading.

Here, for convenience, the combination of the selection transistor ST and the cell transistors CT1 to CT4 is referred to as a memory cell. Unlike a general memory cell, this memory cell is composed of four bits (serial connection) in one memory cell. (The number of bits corresponding to the number of cell transistors used), and is equivalent to four conventional memory cells.

Next, the operation of the above configuration will be described. FIG. 2 is a timing chart of each signal at the time of programming in the circuit of FIG. First, the signal R is set to the "0" level to turn off the transistor 27, and at time t0, the signals X1 and W1 to W4 are set to the high voltage level. The thin oxide film of the cell transistor shown (film thickness 100
Electrons are injected into the floating gates of the cell transistors CT1 to CT4 via the 3333. The signals W4 to W1 are sequentially set to 0 V at the next timings t1 to t4. When these signals W1 to W4 are set to 0V, if the data D output from the data input circuit 25 is at "1" level, the transistor 26 is turned on, and the transistor 26 and the selection transistor are switched from the high voltage power supply Vp. A high voltage is applied to the drain of the corresponding cell transistor via ST, and electrons are emitted from the floating gate by the tunnel effect. In FIG. 2, when the signals W3 and W1 are set to 0V, the data D is at the "1" level (time t2 to t3, time t4 to t5).
), The electrons injected into the floating gates of the cell transistors CT3 and CT1 are released. What is important here is not the application of 0 V to the control gate and the application of a high voltage to the drain, but the strength of the electric field in the region where the tunnel effect occurs. Thus, data is selectively programmed in each cell transistor. For example,
Since the cell transistor CT4 does not become an electric field where the tunnel effect occurs in the region where the tunnel effect occurs after the time t1, no electron is exchanged with the floating gate.

Between times t0 and t1, the electrons injected into the floating gates of the cell transistors CT1 to CT4 are:
Between times t1 and t2, between times t2 and t3, and between times t3 and t4
Cell transistors CT1 to CT1 depending on whether data D is at "1" level or "0" level during time t4 to t5.
The program is performed depending on whether or not electrons are emitted from the floating gate of FIG.

At the timing between times t1 and t2, signals X1 and W1 through W3 are set to the high voltage level, and selection transistor ST and cell transistors CT1 through CT2 are set.
3 turns on. At this time, the signal W4 is set to 0 V, and the data D is at the "0" level.
Is off, and no high voltage is applied to the cell transistor CT4, so that the electrons injected into the floating gate of the cell transistor CT4 are not emitted.

At the timing between times t2 and t3, the signals X1 and W1 and W2 are set to the high voltage level, and the selection transistor ST and the cell transistors CT1 and CT3 are set.
2 turns on. At this time, the signal W3 is set to 0 V and the data D is at the "1" level.
Is turned on, and a high voltage is applied to the cell transistor CT3. At this time, since 0 V is applied to the control gate of the cell transistor CT3, the electric field applied to the thin insulating film increases, causing a tunnel effect, and the electrons injected into the floating gate of the cell transistor CT3 are emitted. You. At this time, the transistor 26 and the cell transistor CT
Since the cell transistor CT3 exists between the cell transistor CT4 and the cell transistor CT4, a high voltage is not applied to the cell transistor CT4, and programming is performed only on the cell transistor CT3.

At the timing between times t3 and t4, signals X1 and W1 are at high voltage levels and signals W2 through W4 are at 0V.
Is set to At this time, since the data D is at the “0” level, the transistor 26 is turned off and the cell transistor CT is turned off.
Since no high voltage is applied to 2, the electrons injected into the floating gate of this cell transistor CT2 are not emitted.

At the timing between times t4 and t5, the signal X1 is set to the high voltage level, the signals W1 to W4 are set to 0V, and the selection transistor ST is turned on. At this time, since the data D is at the "1" level, the transistor 26 is turned on, and a high voltage is applied to the cell transistor CT1, so that the electric field applied to the thin insulating film becomes large and a tunnel effect occurs. The electrons injected into the floating gate of CT1 are emitted. At this time, the transistor
Since the cell transistor CT1 exists between the cell transistor CT2 and the cell transistors CT2 to CT4, no high voltage is applied to the cell transistors CT2 to CT4.
Programming is performed only on cell transistor CT1.

On the other hand, when reading data, signals R and X1 are set to "1" level, and the control gate of the cell transistor to be read is set to 0V. At this time, the gates of the other cell transistors are set to "1" level. The timing chart of FIG. 3 shows a case where data is sequentially read from the cell transistors CT4 to CT1, and between the time t0 and t1, the data is read from the cell transistor CT4.
From the cell transistor CT3 between the times t1 and t2, and from the cell transistor CT2 between the times t2 and t3, the time t3
, T4, data is read from the cell transistor CT1. Now, assuming that the signal W1 is set to 0V and the signals W2 to W4 are set to "1" level, the cell transistor C
Data is read from T1. If the programming is performed as described above, since electrons are emitted from the floating gate of the cell transistor CT1, the threshold voltage thereof is negative and the threshold voltage is turned on even when the signal W1 is 0V. The control gates of the other cell transistors CT2 to CT4 are at the "1" level and are on. Therefore, all the cell transistors CT1 to CT4 are turned on,
The potential of the node N2 drops. This is used as the data detection circuit 28
To read data from the cell transistor CT1. Also, the signal W2 becomes 0V and the cell transistor C
When T2 is selected, the cell transistor CT2
Since the electrons are still injected into the
If it is V, it is turned off. Therefore, the node N2 is charged by the transistor 29, which is connected to the data detection circuit 28.
To detect. Note that the threshold voltages of the cell transistors CT1 to CT4 in the state where electrons are injected need to be set so as to be turned on when the control gates thereof become "1" level.

FIGS. 4A to 4C show an example of the structure of a transistor suitable for the cell transistors CT1 to CT4 shown in FIG. 1. A part of the insulating film on the channel region is made as thin as about 100 Å. It is formed of an oxide film to reduce the cell size. (A) is a plan view of the pattern, (b) is a cross-sectional view taken along line BB 'of (a), and (c) is a cross-sectional view taken along line CC' of (a). Where 30 is a P-type silicon substrate, 31 and 32 are N ⁺ -type sources,
The drain region, 33 is a thin oxide film, 34 is a floating gate, and 35 is a control gate.

FIGS. 5A and 5B show another example of a structure suitable for the cell transistors CT1 to CT4 in FIG. 1. All the insulating films on the channel region are thinly oxidized to about 100 angstroms. The film 33 is formed. 5, the same parts as those in FIG. 4 are denoted by the same reference numerals, FIG. 5 (a) is a plan view of the pattern, and FIG. 5 (b) is a cross-sectional view taken along line CC 'of FIG. .

FIGS. 6A and 6B show still another example of the structure suitable for the cell transistors CT1 to CT4 in FIG. 1, and a part of the channel region is a depletion type transistor. (A) is a plan view of the pattern, and (b) is a cross-sectional view taken along line BB 'of (a). In such a configuration, even if the amount of injected electrons is too large and the cell transistor has a threshold voltage at which the cell transistor is not turned on even when a signal of the “1” level is supplied to the control gate, the N voltage is not increased.
^The source / drain regions 31,
Since 32 is connected, current flows. In reading data from the cell transistor having such a configuration, when a potential of "0" level is applied to the control gate, a difference in the amount of current caused by whether or not electrons are injected into the floating gate is detected. Performed by

FIG. 7 shows a configuration example of a nonvolatile semiconductor memory device in which the above-mentioned memory cells are arranged in a matrix. In FIG. 7, reference numeral 37 denotes a row decoder, 38 denotes a first column decoder, and 39 denotes a second column decoder. Data input / output lines IO1 to IO8 are connected to circuits surrounded by a dashed line in FIG. You. The above row decoder
37 are signals X1, X2,..., Signals W11, W12,.
n, signals W21, W22,..., W2n are output to select the row direction of the memory cell array. The column decoder 38 outputs signals Y1, Y2,..., Ym to selectively control conduction of the column selection MOS transistors Q1 to Qm, thereby inputting data to one of the memory cell blocks B1 to Bm. This is for supplying data to be programmed via output lines IO1 to IO8, or for deriving read data. On the other hand, the column decoder 39 outputs signals Z2 to Z2.
Outputs Zm and outputs depletion type MOS
By selectively controlling the conduction of the transistors QD2 to QDm, the memory cell blocks B1 to Bm are programmed.
Are sequentially specified.

In the above configuration, programming is performed from a memory cell located far from row decoder 27. FIG. 8 is a timing chart of each signal at the time of this programming. That is, programming is performed from the memory cells connected to the signal line X1 of the memory cell block Bm.
In this program, the signals X1, Ym, Z2 to Zm
And a high voltage is applied. In this state, first, the signals W11 to W11 are output.
With W1n set to a high voltage, electrons are injected into the floating gates of all cell transistors. Next, the signals are sequentially set to "0" level from the signal W1n to the signal W11. At this time, when the control gate is at the "0" level, the program data is transferred to the data input / output lines IO1 to IO8, the column selection transistors Qm
Electrons are emitted only when a high voltage is applied to the drain via the selection transistor STm, and data is programmed in each cell transistor.

FIG. 9 shows a timing chart at the time of reading, in which signals X, X corresponding to a selected memory cell are shown.
Y becomes "1" level. Also, one of the signals W11 to W1n corresponding to each cell transistor of the selected memory cell is selected.
One is at the “0” level, and the control gates of the unselected cell transistors are all at the “1” level. by this,
Data is read out as in the case of FIG.

FIG. 10 summarizes the levels of the signals W11 to W1n in a truth table. When the input data I is at the "1" level, the signals W11 to W1n are all at the "1" level and the cell Electrons are injected into the floating gate of the transistor. When the data I is at the "0" level and the R is at the "0" level, programming is performed individually, and when the R is at the "1" level, the data is read.

FIG. 11 shows each signal X1, X2,
The truth tables of W11 to W14 and W21 to W24 are shown for three addresses A0 to A2. In this example, at the time of reading, for example, if X1 = 0, the signals W11-W
Although all 14 are set to the "0" level, one of W11 to W14 may be set to the "0" level as in the case of X1 = 1.

FIG. 12 shows another embodiment of the present invention, in which "0" level is applied between the cell transistor CT4 and the ground point in FIG. 1 during programming and "1" during reading.
N-channel type M whose conduction is controlled by the signal φ which becomes the level
An OS transistor 40 is provided. 12, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. According to such a configuration, when a high voltage is applied to the drain at the time of programming, even if there is a leak current from the cell transistors CT1 to CT4, this leak current can be cut off by the transistor 40. Thus, deterioration of the program characteristics can be prevented. The transistor 40 may be shared by a plurality of cell blocks.

FIG. 13 shows another configuration example when the circuit of FIG. 1 is formed in a matrix. This circuit corresponds to one of the memory cell blocks B1 to Bm shown in FIG. 7. In such a configuration, the MOS transistors QT1, QT2 controlled by signals X1, X2,. ,.., And the signals are input via these transistors QT1, QT2,..., The signals Z2, Z3,.
If the signals W1n1,..., W121 and W111 inputted to the corresponding memory blocks by taking logic with m etc. are set to a high voltage, it is possible to freely program from any memory block. At this time, if the signals W111, W121,..., W1n1 are wired by the aluminum wiring of the second layer using a two-layer aluminum wiring, the chip size is increased by increasing the wiring of the signals W111, W121,. Need less.

A latch circuit is provided for each column line, and data to be written into these latch circuits is latched. Based on the latched data of the memory cells for one row, a latch circuit is provided for each column line. If the potential is set to a high potential or 0 V, all the memory cells of all the column lines for one row can be programmed, so that the array dividing MOS transistors QD2 to QDm shown in FIG. 7 can be omitted.

[0034]

As described above, according to the present invention,
A nonvolatile semiconductor memory device in which the size of a memory cell can be reduced while data can be electrically rewritten and cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a view for explaining a nonvolatile semiconductor memory device according to one embodiment of the present invention;

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. 1;

FIG. 4 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1;

FIG. 5 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1;

FIG. 6 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1;

FIG. 7 is a diagram showing a configuration example of a memory formed by arranging the cell transistors of FIG. 1 in a matrix.

FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 7;

FIG. 9 is a timing chart for explaining the operation of the circuit of FIG. 7;

FIG. 10 is a diagram showing the level of each signal in the circuit of FIG. 7;

FIG. 11 is a diagram showing the level of each signal in the circuit of FIG. 7;

FIG. 12 is a diagram for explaining another embodiment of the present invention.

FIG. 13 is a view for explaining another embodiment of the present invention.

FIG. 14 is a diagram showing a symbol of a cell transistor.

FIG. 15 is a diagram showing a control gate voltage-drain current characteristic of the cell transistor shown in FIG. 14;

FIG. 16 is a diagram showing a circuit configuration example of an EEPROM configured using the cell transistors of FIG. 14;

FIG. 17 is a diagram showing an example of a pattern configuration of the circuit of FIG. 16;

[Explanation of symbols]

ST: selection transistor, CT1 to CT4: cell transistor, 40: transistor cut off during programming, 37: row decoder, IO1 to IO8: data input / output line, Q1 to Qm: column selection transistor, 38: first column Decoders, QD2 to QDm ... array dividing transistors, 39
... Second column decoder, QT1, QT2,.

Claims (3)

(57) [Claims] 1. A semiconductor device comprising: a control gate; a floating gate; and an insulating film having a thickness capable of causing a tunnel effect provided on an entire surface between the floating gate and a channel region, and a current path connected in series. Connected to one end of a plurality of cell transistors and a plurality of cell transistors connected in series
And a plurality of these cell transistors connected in series.
A memory cell comprising a selection transistor for selecting collectively, selecting means for selecting individually cell transistors of multiple <br/> number selected collectively by the selection transistor, writing
Latch means for latching embedded data,
The current path of the cell transistor selected by the selection means based on the write data latched by the means.
At one end, by applying a voltage corresponding to the write data via the selection transistor comprises a writing means for performing a program by injecting or emitting electrons through the insulating film on the floating gate A nonvolatile semiconductor memory device characterized by the above-mentioned. 2. A selection transistor having one end connected to a column line and a gate connected to a first row line, and a series connection between the other end of the selection transistor and a reference potential, each of which is a control gate. , A floating gate, and a plurality of cell transistors provided on the entire surface between the floating gate and the channel region, the insulating film having a thickness capable of causing a tunnel effect, and the second row line being connected to the control gate. A memory cell array in which memory cells consisting of
A row decoder for supplying a decode signal to the cell transistor and the selection transistor constituting each of the memory cells via the second row line and the first row line, respectively; and writing data for each column of the memory cell array. Luck
Latch means for latching.
One end of the current path of the cell transistor selected by the row decoder based on the write data for one row
, By applying a voltage corresponding to the write data, characterized by comprising a writing means for performing a program by injecting or emitting electrons through the insulating film into the floating gate of the cell transistor selected Nonvolatile semiconductor memory device. 3. One end is connected to a column line and a gate is connected to a first row.
And a selection transistor connected to the line.
Connected in series between the other end of the transistor and the reference potential.
Are the control gate, the floating gate, and the floating gate
The tunnel effect provided on the entire surface between the
And the control gate has a second row line.
A memory cell comprising a plurality of connected cell transistors
Memory cell array in which memory cells are arranged in a matrix,
An array dividing transistors for dividing the memory cell array into a plurality of blocks, a column decoder for specifying a block of memory cells for performing a program by selectively conduction control the array divided transistors, each main
Cell transistors and selection transistors
The second row line and the first row respectively.
A row decoder for supplying a decode signal via a line,
The above row in the block specified by the column decoder
The current flow of the cell transistor selected by the decoder
A voltage corresponding to the write data is applied to one end of the path
The floating gate of the selected cell transistor
Injecting or emitting electrons through the insulating film
; And a writing means for performing a program with, characterized by performing the program in blocks of memory cells
The nonvolatile semiconductor memory device according to.