JP2575220B2 - Cell switching equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell switching device for exchanging cells obtained by blocking various types of multimedia information such as voice, data, and images at high speed.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional cell switching apparatus shown in, for example, the specification and drawings attached to Japanese Patent Application No. 217226 in 1988. In the figure, reference numerals _{11 to} 1n denote n incoming lines to which a packet is input, and this packet has a fixed length and each includes a header section containing coded destination information. 2 ₁ to 2 m is the m number of outgoing lines is output in accordance with destination the packet is designated by the header portion. 3 ₁ ~3l is l number of buffers where the packets inputted is temporarily stored, free to connect the incoming line 1 ₁ 1n are the packets are input 4, the vacant buffer 3 ₁ ~3l This is a buffer selection switch.

5 ₁ ~5l is prepared corresponding to each of the buffer 3 ₁ ~3l, the packets stored in the buffer 3 ₁ ~3l associated is the header memory circuit for extracting and storing only the header portion . 6 ₁ ~6l is provided corresponding to each header memory circuits 5 ₁ ~5l, outgoing selection to significantly only output to be transmitted to the output line corresponding to the memory contents of the corresponding header memory circuits 5 ₁ ~5l Circuit.

7 ₁ ~7m is prepared corresponding to each of the output line 2 ₁ to 2 m, in response to an output for sending the respective outgoing line selecting circuits 6 ₁ ~6l, the buffer 3 ₁ ~3l buffer number it Encoder. 8 ₁ ~8m is provided to an encoder 7 ₁ ~7m correspondingly coded buffer number is written in each of the encoders 7 ₁ ~7m, first-in first-out in which it is read out in order of input (hereinafter FI
FO) type FIFO memory. 9 _{1 to} 9m for each outgoing line
2 ₁ to 2 m are provided in correspondence, it is controlled by the buffer number which is output from the corresponding FIFO memory 8 ₁ ~8m, buffer
3 is a buffer connection switch for outputting the outgoing lines 2 ₁ to 2 m which is designated the packets accumulated in ₁ ～3L in its header portion.

Here, a packet is used instead of a cell as a unit of information to be transmitted, but the multimedia information is divided into block units, and a header including destination information is added thereto. And the packet express the same thing. However, in general, the number of packets is 1
The difference is that while the length of one block is treated as a variable length, the cell is treated as a fixed length defined by international standards.

Next, the operation will be described. Here, FIG. 5 is a time chart showing the timings of the respective parts of the signal, when the vacant buffer 3 ₁ and 3l, control in the case of simultaneously receiving the packet output line 2 ₁ addressed from the incoming line 1 ₁ and 1n It shows the flow. The packet handled here has a fixed length as described above, and its header portion includes a coded outgoing line number as destination information.

When a packet to the incoming line 1 ₁ 1n arrives, free buffers selection switch 4 selects a free one of the buffer 3 ₁ ～3L, connects the incoming line 1 ₁ 1n which it arrived packet. Here, as shown in FIGS. 5 (a) and (b),
Packet same outgoing line 2 ₁ of the output line number "1" is specified as a destination in the header part, when arriving at the same time from the incoming line 1 ₁ and 1n, free buffer selection switch 4, for example incoming lines 1 ₁ to
1n the youth turn order, and the vacant buffer 3 ₁ ~3l also to connect them to choose the young number order. Therefore, in this case, the input line ₁₁ is changed to the buffer 3 by the empty buffer selection switch 4.
₁ , incoming lines 1n are connected to buffers 31 respectively, and incoming lines 1 ₁
Arriving packet A to within Buffers 3 _1, packet B arriving at incoming lines 1n are respectively accumulated in the buffer 3l.

By the switching of the free buffer selection switch 4, the header memory circuit 5 ₁ the packet A is corresponding to Buffers 3 _1, packet B is also supplied to the header memory circuit 5l corresponding to the buffer 3l. Here, the header memory circuits 5 ₁ -
5l is for extracting only the header part of each received packet and storing the outgoing line number as its contents. Therefore,
The header memory circuit 5 ₁ and 5l, respectively outgoing 2 ₁ of the output line number "1" is stored. The contents of these header memory circuits 5 ₁ ~5l is sent to the corresponding outgoing line selecting circuit 6 ₁ ~6l,
Each outgoing line selecting circuits 6 ₁ ~6l the corresponding header memory circuits 5 ₁ ~5l
Are made significant, ie, “1”, only the output sent to the output line corresponding to the outgoing line number designated by the contents of “1”, and the output sent to other output lines is insignificant, ie, remains “0”.

Thus, the outgoing line selecting circuit 6 ₁ is set to "1" to indicate the output to the encoder 7 ₁ to 5 (c), the outgoing line selecting circuit 6l fifth view the output of the encoder 7 ₁ (d) It is set to “1” as shown. Here, the encoder 7 ₁ ～7M is when any one of the output in the outgoing line selecting circuit 6 ₁ ～6L becomes "1", the corresponding outgoing line selecting circuit 6 ₁ buffer 3 ～6L is associated ₁ ～3L the buffer number encoding, and stores it in the FIFO memory 8 ₁ ~8m associated with itself. 5 (c) and as shown in (d), the output of the two outgoing lines selecting circuits 6 ₁ and 6l are simultaneously "1"
If it becomes, the encoder ₇₁ stores the buffer number, for example, the FIFO memory ₈₁ to the young turn order.

Therefore, the FIFO memory 8 _1, buffer 3 _first buffer number is stored first, the buffer 3l buffer number is stored subsequently. Buffer connection switch 9 _{1 to} 9 m
From the FIFO memory 8 ₁ ～8M associated reads in the order stored a buffer number stored therein, the buffer number - is granted buffer 3 ₁ -
Connect to outgoing lines 2 ₁ to 2 m associated with 3l to itself.

That is, reads the first Buffers numbers from the FIFO memory ₈₁ as the buffer connection switch 9 ₁ shown in FIG. 5 (e),
After the connection process is completed, the next packet number is read. When the buffer number is read, first buffer 3 ₁
The Connect to outgoing line 2 _1, and outputs the packet A stored in the buffer 3 ₁ As shown in FIG. 5 (f) to the output line 2 _1. Departure
When transmission of the packet A to 2 ₁ is completed, the packet number is read out as described above, is connected buffer 3l is in the output line 2 ₁ by simultaneously accumulated in the buffer 3l as of FIG. 5 (g) packet B is outputted to the outgoing line 2 _1. Therefore,
The outgoing line 2 _1, Figure 5 packet as shown in (h) A and B
Are output continuously.

Buffer connection switch 9 ₁ ～9M the packet output line 2 ₁ -
Each time for sending the 2m, releases the corresponding buffer 3 ₁ ~3l,
This is notified to the empty buffer selection switch 4 to prepare for the subsequent packet reception.

[Problems to be solved by the invention]

Since the conventional cell switching apparatus is constructed as described above, the buffer 3 ₁ when reading cell (packet) from ～3L, 1 single buffer 3 ₁ in order to avoid collisions with other cells
The ～3L can not only one cell accumulates, when the number of write of the cells exceeds the number of buffer 3 ₁ ～3L, the cell will be discarded, also reducing the discard rate of cell it is necessary to prepare a large number of buffer 3 ₁ ~3l in order further includes a buffer 3 ₁ ~3l as a result the incoming line
1 ₁ 1n and the output line 2 ₁ to 2 m for connection, there is a problem such as free buffer selection switch 4 and a scale of the buffer connection switch 9 ₁ ~9m increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. Even if the number of buffers is reduced, cells are less likely to be discarded due to cell collision, and a switch for connecting a buffer to an incoming line and an outgoing line is provided. It is an object of the present invention to obtain a cell switching device capable of reducing the scale of a cell.

[Means for solving the problem]

A cell switching device according to the present invention writes a cell consisting of a data portion and a header portion including destination information thereof into a buffer memory by controlling a first switch, or writes the written cell into a buffer by controlling a second switch. A destination queue that reads from the memory and manages the buffer number and address of this buffer memory so that the cells do not reverse order, and writes so that multiple cells are not written to the same buffer memory at the same time. The destination-specific queue is managed in a management memory in a buffer number table.

[Action]

A cell exchange device according to the present invention writes a cell comprising a data portion and a header portion including destination information thereof into a buffer memory by controlling a first switch, or controls a second switch to write the written cell into a buffer memory. A destination queue that reads from the memory and manages the buffer number and address of this buffer memory so that the cells do not reverse order, and writes so that multiple cells are not written to the same buffer memory at the same time. By managing the queues for each destination in the management memory in the form of a buffer number table, it is possible to reduce or prevent competition between a plurality of cells that occurs when input cells are read from the buffer memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 designates a plurality of cells (4 in this embodiment) to which input lines I ₀ , I ₁ ,... The outgoing lines 2 are assigned outgoing line numbers O ₀ , O ₁ ,..., And a plurality of outgoing lines (four in this embodiment) in which cells are output according to the destination specified in the header portion thereof. Line. Reference numeral 10 denotes a header processing circuit provided corresponding to each of the input lines 1 and detecting the destination output line 2 from the header portion of the cell input from the corresponding input line 1.

Further, 11 is provided with buffer numbers # 0, # 1,..., Respectively, and stores the cells at a specified address, and by specifying the address, the cells are stored irrespective of the writing order. the buffer of the plurality can be read cells (six in this example), one buffer 11 into a plurality (e.g., three) conventional buffers 3 ₁ shown cell in Figure 4 in that it can accumulate in Different from 3l. 12
Are provided corresponding to each of the buffers 11, for example, FI
Manage free addresses using FO type memory,
This is a storage control circuit that provides a read address and a write address to the associated buffer 11.

Reference numeral 13 denotes an input space switch for selectively connecting each of the header processing circuits 10 to a predetermined buffer 11, and reference numeral 14 denotes an output space switch for selectively connecting each buffer 11 to a predetermined output line 2. 15 controls the switching of the incoming line space switch 13 to select the buffer 11 in which the cells are stored, and controls the switching of the outgoing line space switch 14 to specify the cells stored in the buffer 11 in the header portion thereof. A buffer control circuit for outputting the output line 2 to be output in a predetermined order.

Further, in the buffer control circuit 15, 16 receives the outgoing line numbers O _{0 to} O ₃ of the cell detected at the time of cell arrival in the header processing circuit 10 associated with each of the incoming lines 1, and This is a control device for selecting the buffer 11 to be stored. Reference numeral 17 denotes a write buffer selection circuit that controls the switching of the input line space switch 13 in order to connect the buffer 11 selected by the control device 16 to the corresponding header processing circuit 10. Reference numeral 18 refers to the outgoing line numbers O _{0 to} O ₃ sent from the buffer selecting circuit 17 and divides the arriving cells by destination, and writes the write address on the buffer 11 in which the cells are written into the buffer 11. Is an address exchange circuit which is obtained from the storage control circuit 12 corresponding to.

Reference numeral 19 denotes a queue for each destination, which is constituted by a FIFO type memory and is provided corresponding to each of the outgoing lines 2. In the destination queue 19, for each outgoing line 2 associated with the outgoing line 2, a write address on the buffer 11 in which cells destined for the outgoing line 2 are stored is stored by the address exchange circuit 18 by the address exchange circuit 18. Written in order of arrival. 20 determines a cell to be read from the buffer 11 by referring to the queue 19 for each destination, and uses the address read from the queue 19 for each destination as a read address as a storage control circuit 12 associated with the corresponding buffer 11. And a read buffer selecting circuit that controls the switching of the output line space switch 14 and connects the buffer 11 to the corresponding output line 2.

Numeral 21 is connected to the control device 16 and changes the state of the destination-specific queue 19 to buffer numbers # 1 to # 4 so that a plurality of cells output to a plurality of output lines 2 at the same time are not written to the same buffer 11. This is a write buffer management memory for managing in table # 5.

Next, the operation will be described. In a time slot,
If one or more cells are input to the input line 1, a header processing circuit 10 arriving cell reads the outgoing line number O ₀ ~ O ₃ destination of the cell from its header as the destination information, the incoming line number I ₀ ~I ₃ sequentially sends the address information of each cell to the controller 16. The controller 16 determines a buffer number for writing each cell. At this time, it is desirable to select the buffer number so that the cells enter the buffers 11 as uniformly as possible. However, when reading out the cells later, a plurality of cells destined for each outgoing line 2 to be read out in the same time slot are the same. buffer
When the data is in the buffer 11, only one of the cells can be read out. Therefore, the control device 16 needs to select the buffer 11 so as to avoid this. To perform this control, a write buffer management memory 21 is associated with the control device 16. The write buffer management memory 21 manages the buffer numbers in which the cells are written by arranging the cell numbers in the arrival order of the cells for each of the destination outgoing lines 2. That is, as shown in FIG. 2, the outgoing line numbers O _{0 to} O ₃ are arranged vertically, and the time slot numbers t, t are arranged horizontally.
+1, t + 2, t + 3 are prepared, and the buffer number of the buffer 11 in which the cell is written is stored therein. As the cells always input and output as the time slot elapses, it is necessary to rewrite the contents of the table. However, by providing a pointer indicating the next time slot number to be output, the buffer in which each cell is written is provided. Eleven buffer numbers can be identified for each destination and arrival order, and the inside of the memory can be reused cyclically.

For example, the table of the write buffer management memory 21 is
When the state as shown in FIG., The incoming line 1 of outgoing numbers O ₁ of the output line 2 addressed cells of the incoming line number I ₀ is to enter one. However, in the drawing, a to i indicate the sky. Control device 16
Selects the write buffer 11 with reference to the table of the write buffer management memory 21. Cells addressed this O ₁ enters the end of the outgoing line number O ₁ corresponding row. Since the buffer number # 1 exists in the time slot t + 1, the time slot t +
In the column to be read out in step 2, the write buffer number of this cell will be in the column of h in the table. Next, the control device 16
Reads buffer numbers in the same time slot t + 2 column as h to determine buffer numbers, obtains buffer numbers # 5 and # 4, and obtains other buffers # 0
To # 3. Method of determining the buffer number is number order as mentioned before, since the cell buffer number written last is the buffer number # 0 in the destination by queue 19 destined O _3, the next number Buffer number #
Select 1. When the buffer number is determined, it is written into the write buffer management memory 21 at position h.

On the other hand, when a plurality of cells are input to the input line 1, it is necessary to select a plurality of write buffers 11. At this time, since a plurality of cells entering in the same time slot cannot write two or more cells in the same buffer 11 due to the structure, it is necessary to select different buffer numbers, that is, exclusively select a buffer number. There must be. Thus, after determining the cell write buffer number entered in input line 1 incoming line number I _0, and I _1, I _2, I ₃ in order of input line number, will exclusively determined. However, cells for which the buffer 11 could not be selected are discarded there. When there is a bias in the destination of the input cell, a large number of cells are stored in the buffer 11, and when the buffer 11 is full, the newly arrived cell is discarded.

When the write buffer 11 is determined, the write buffer selecting circuit 17 instructs the input line space switch 13 to connect the header processing circuit 10 corresponding to the input line 1 to which the cell has been input and the buffer 11 for writing the cell. The address of the buffer 11 is specified by the write address of the storage control circuit 12 provided corresponding to each buffer 11, and the address is passed through the address exchange circuit 18 to the destination-specific queue corresponding to the outgoing line 2 of the destination. Written behind to prevent cell reversal. The read buffer selection circuit 20 reads the address at the head of the destination queue 19 corresponding to all outgoing lines 2,
The output is sent to the corresponding storage control circuit 12 and instructs the output line space switch 14 to connect the buffer 11 in which the address where the cell to be read is written is specified to the predetermined output line 2. In response to this instruction, the output line space switch 14 connects the buffer 11 and the output line 2, and the buffer 11 outputs cells to the output line 2. The empty address of the buffer 11 is managed by the storage control circuit 12. Here, the read address sent from the read buffer selecting circuit 20 is stored in the FIFO as an empty address, and another cell is input from the input line 1 and the buffer is input. When data is written to the buffer 11, the address at the head of this FIFO is used as the next write address, and is sent to the buffer 11 and the address exchange circuit 18 so that the buffer
Use 11 addresses cyclically and efficiently.

FIG. 3 is an explanatory diagram showing the state of randomly input cells at the incoming line 1, buffer 11, destination-specific queue 19, and outgoing line 2 for each time slot in a table. Here, input lines 1 with input numbers I ₀ , I ₁ , I ₂ , and I ₃ are A, B, C, and D, respectively.
And the name of the cell is expressed using the destination, incoming line, and input time slot. For example, a cell arriving at incoming line A (I ₀ ) destined to outgoing line 2 of outgoing line number O ₃ in time slot 1 is expressed as 3A ₁ . In the figure (A)
Of the line indicates the arrival of a cell input lines A~D (I ₀ ~I ₃₎ separately. In the column where the cell has arrived, the name of the cell has been written, and a blank area indicates that the slot has not arrived. The row (b) in the figure is for each buffer of buffer numbers # 0 to # 5 and for each buffer.
11 shows the presence state of cells for each address in 11. In the example shown, the number of buffers is 6, and one buffer 11
It is assumed that the number of cells stored in is three, that is, one buffer 11 has three addresses. For example, the buffer 11 of the buffer number # 0 has three addresses # 01 to # 03, but arrives at the incoming line D (I ₃ ) in the time slot 2 during the time slots 3 to 5 in the address # 02. Cell 1D ₂ to O ₁
Is stored. The row (c) in the figure shows the transition of the queue 19 for each destination. Eventually, the speed at which the cell leaves each outgoing line 2 of the outgoing line numbers O _{0 to} O ₃ is constant, but the rate at which the cells arrive at the incoming line 1 and the destination depend on the time. Yes, it is necessary to hold for the time slot in which the cell in the buffer 11 exists to absorb it. At that time, in order to manage the buffer number and the address in the buffer 11, the queue 19 for each destination has a queue of addresses in the buffer 11 for all destinations so as to output the cell that has arrived first. The address written in the upper part of the figure is the front of the matrix, and the lower part is the last. For example, cells addressed O ₂ in the time slot 8 are currently in the three buffers, the order of reading is # 11, # 21, and # 41. The queue 19 for each destination manages both the buffer number and the address in the buffer, and refers only to the head of the queue.However, the write buffer management memory 21 manages only the buffer number, and stores not only the head but also the memory. You can refer to it freely. In the figure, (d) shows cells output to each of the outgoing lines 2 of O _{0 to} O ₃ for each time slot.

According to the present invention, the number of cells that can be written to one buffer 11 in the same time slot is one, so the buffers 11 for writing cells when a plurality of cells arrive in a certain time slot are different from each other. You have to choose. Also, at the time of reading, since the number of cells that can be read from one buffer 11 in the same time slot is one, they must be different from each other. For this purpose, candidate buffers 11 are set to # 0, # 1, # 2, # 3, # 4, # 5, # 0, # 1,.
The procedure is as follows: it is individually applied to the cells that have arrived, and it is determined after writing and reading that both conditions are satisfied.

For example, cell 0C ₁₀ last entered in time slot ₁₀
Are stored in the buffer 11 of # 1 in the time slot 11. Of the four cells entered in time slot 11 to incoming lines 1, the cell 3A _11, the following # 2 of the buffer 11 of # 1 can be mentioned as candidates. Cell 3A ₁₁ is destined for O ₃ , but now O ₃
Since three cells are present in the buffer 11, they are time slots 15 when they are read. If buffer # 2
If it is stored in 11, in time slot 15 to be read, # 2
The buffer 11 becomes the fact that read-only cells 3A _11, there is no problem because nothing is stored in the buffer 11 for the current time slot 11 in # 2. Similarly, cells 3B ₁₁ and 0C ₁₁ input to incoming line 1 in time slot 11 also enter buffers 3 of # 3 and # 4, respectively. But cell 2D ₁₁ is #
Once in 5 buffer 11 becomes the same buffer and the cell 3A ₁₀ in outgoing 2 addressed queues O _3, since either would be cell waits, cell 2D ₁₁ is the # 0 buffer 11
Put in. In the next time slot 12, the buffer 11 selects from the buffer number # 1. The selection of the buffer 11 has been described above. The address in the buffer 11 is used so that the storage control circuit 12 uses three addresses as uniformly as possible. Also, cells that have filled the buffer 11 with cells and overflowed are discarded there.
On the other hand, the destination-specific queue 19 is a memory (FIFO) from which data written before can be read first, and the number of the write buffer 11 is put at the end of the queue. When reading cells, first, the read buffer selection circuit 20
The buffer number and the address are read from 19, and then the outgoing line space switch 14 connects the buffer 11 and the outgoing line 2 according to the instruction of the read buffer selecting circuit 20, and the buffer 11 outputs the cell to the outgoing line 2.

In addition, there are the following methods to reduce the cell discard rate.

A cell that is to be discarded in a certain time slot is output in the next time slot of the time slot that should have been output without being discarded there. For example, the controller 16 selects the buffer 11 so that a cell which is to be discarded in i of FIG. 2 is put in the next g. At this time, an empty signal is put in i in the table of the write buffer management memory 21 and the corresponding destination queue 19, and
The cells from the outgoing line 2 outgoing lines numbers O ₃ is in the time slot is not output.

In the above-described embodiment, the destination-specific queue 19 is a FIFO. However, in order to create a queue of addresses, a read pointer, a write pointer, or the like is used so that the write order can be understood. May be replaced.

Further, in the above embodiment, when writing cells to the buffer 11, the buffer 11 is selected in numerical order.However, in order to reduce cell discarding, the buffer 11 may be selected from a buffer having many empty addresses. Good. Further, a control circuit may be set so that one cell is output to two or more outgoing lines to provide a broadcasting function. Further, a destination-specific queue 19 may be provided for each destination by a plurality of priority levels. If provided, the cell output can be given priority.

In the above embodiment, when a cell arrives at the input line 1 of I _{0 to} I ₃ , I ₀ , I ₁ , I ₂ , I ₃ and the buffer are always arranged in the order of the input numbers.
Had selected the 11, because the direction of the incoming line 1 of the incoming line number I ₃ is likely to occur disposal of the cell than the incoming line 1 of the incoming line number I _0,
There is a method of changing the input line in which cells are easily discarded by changing the selection order one after another. For example, in one time slot I ₀ , I ₁ , I ₂ , I ₃ , in the next time slot I ₁ ,
_{I 2, I 3, I 0} , in the _{next, I 2, I 3, I} 0, I 1, Yuku make a selection of the buffer 11 in the order of ....

Further, in the above embodiment, the number of incoming lines, the number of outgoing lines is 4, the number of buffers is 6, and the buffer size is 3. However, the present invention is not limited to these. A link connection, in which case the cell discard rate is reduced by making the speed between the stages higher than the speed of the incoming line, or a serial / parallel conversion circuit and a parallel / serial conversion circuit are provided before and after this cell switching device. The speed of the switch may be reduced, and in any case, the same effect as in the above embodiment is obtained.

〔The invention's effect〕

As described above, according to the present invention, a cell consisting of a data part and a header part including the destination information is written to the buffer memory by controlling the first switch, or the written cell is controlled to the second switch. The queue is read out from the buffer memory, and the buffer number and the address of the buffer memory are managed according to the destination so that the cells do not reverse the order, and a plurality of cells are not written into the same buffer memory at the same time. Since the write management memory is configured to manage the queues for each destination in the form of a table of buffer numbers, it is possible to reduce and prevent competition between a plurality of cells that occurs when reading input cells from the buffer memory, This has the effect of reducing waste.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a cell switching device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of the contents of a write buffer management memory, and FIG. 3 is a block diagram of the embodiment shown in FIG. FIG. 4 is a block diagram showing a conventional cell switching apparatus, and FIG. 5 is a time chart showing the timing of signals in each section. 1 is an incoming line, 2 is an outgoing line, 10 is a header processing circuit, 11 is a buffer, 13 is an incoming line space switch, 14 is an outgoing line space switch, 15
Is a buffer control circuit, 19 is a queue for each destination, and 21 is a write buffer management memory. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A plurality of incoming lines for inputting a cell comprising a data portion and a header portion including destination information thereof; a plurality of outgoing lines for outputting the cell to a destination specified by the header portion; A buffer memory capable of storing one or more cells for writing a cell from a writing line or reading the written cell to the output line, and a first switch for selecting an input line for writing the cell by the buffer memory A second switch for selecting the outgoing line for reading the written cell by the buffer memory;
A buffer queue of the buffer memory in which the cell is written for each destination line and a queue for each destination which manages the address so that the cell does not reverse the order, and a plurality of cells which are simultaneously output to the plurality of output lines are the same. A write management memory that manages the queues for each destination in a table of buffer numbers so as not to be written to the buffer memory of A cell switching device provided with a buffer control circuit for outputting data in the following order.