JP2575458B2 - How to make an exposure mask - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a method for producing an exposure mask, a method for producing a mask based on design data of a semiconductor circuit designed to be divided into a plurality of hierarchies for the purpose of shortening a mask producing time. In a method for producing an exposure mask, data correction means for performing logical processing and / or shift processing on a pattern of a basic gate circuit designed in one design hierarchy of circuit pattern design, and a pattern of a gate circuit provided with the data correction means And gate circuit exposure means for exposing the mask substrate on a gate circuit basis based on the data of the basic type gate circuit arrangement address designed in another design hierarchy.

[Industrial applications]

The present invention relates to a method for producing a mask for exposure, and more particularly, to a method for producing a mask that can simplify data processing when producing a mask used for producing a semiconductor circuit or the like.

[Conventional technology]

When designing a pattern of a semiconductor integrated circuit such as a gate array circuit, instead of patterning the entire integrated circuit at once, a basic circuit is extracted from a large number of gate circuits constituting the integrated circuit. The integrated circuit is divided into a plurality of layers, for example, the layout design of a basic circuit is performed after designing the patterns, thereby improving the design efficiency.

When a mask is created based on the design data divided into a plurality of hierarchies, solid development is performed to combine the data of the pattern design and the data of the layout design.

Then, the data obtained by this solid development is used as pattern data of the entire integrated circuit, and the mask substrate is collectively exposed based on this data. However, in the lithography process of the semiconductor device, the pattern becomes thinner or thicker. It is necessary to correct the data in consideration of these phenomena in advance.

For this reason, after the data processing by solid development is completed, a shift process for correcting the pattern data by predicting the pattern thickness or thinning is performed.

In addition, when this shift processing is performed, a pattern may be separated or a pattern that is not originally conductive may come into contact with the shift processing. Therefore, a logical processing for correcting these data in anticipation thereof is performed.

As described above, when fabricating a mask, the resist on the substrate is exposed based on the pattern data of the semiconductor circuit that has been subjected to solid development, logic processing, and shift processing, and the mask is formed by performing image, etching, and resist removal. (Eighth
Figure).

[Problems to be solved by the invention]

However, since the logic processing and the shift processing are performed collectively for all the patterns of the solid-expanded semiconductor circuit, as the number of gate circuits included in the semiconductor integrated circuit increases, the time required to create a mask increases, and the production efficiency increases. Is reduced.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a method for producing an exposure mask that can reduce the time required for producing a mask.

[Means for solving the problem]

The above object is to provide an exposure mask creating method for creating a mask on the basis of design data of a semiconductor circuit designed in a plurality of layers, wherein the basic type gate circuits 21 to 2n designed in one design layer of the circuit pattern design are provided. Data correction means for performing logical processing or / and shift processing of the pattern, and the patterns of the gate circuits 21 to 2n to which the data correction means are applied, based on the address of the gate circuit arrangement design data designed in another design hierarchy. A gate circuit exposing means for exposing the mask substrate 5 in units of gate circuits is provided.

(Operation)

When designing a pattern of a semiconductor circuit, design the pattern of the gate circuits 21 to 2n, which form a plurality of basic types, without designing the whole image of the chip at once, and then design the gate circuit arrangement For example, the semiconductor circuit is designed in a plurality of layers.

Next, a case of forming a mask for a semiconductor exposure apparatus will be described by taking a mask for diffusing n-type impurities as an example.

First, the pattern data of the n-type impurity diffusion masks relating to the gate circuits 21 to 2n forming several types of basic types are read out, and the data are subjected to logical processing and shift processing, thereby correcting thickening and thinning in the semiconductor circuit forming process. I do.

Next, one of the basic gate circuits 21 to 2n is called, and address data for arranging the gate circuit 2 on the mask substrate 5 is called from the layout design data. And n
A pattern for pattern impurity diffusion or the like is exposed on the substrate one by one for each gate circuit.

This operation is performed for all the remaining gate circuits 22 to 2n, and the exposure scan of the pattern mask for n-type impurity diffusion is completed.

After that, the phenomenon, etching,
The mask is completed by performing the resist removal process.

 The above steps are applied to other patterns.

〔Example〕

FIG. 2 shows an example of an integrated circuit. In the figure, reference numeral 1 denotes a semiconductor integrated circuit constituted by a gate array in which a large number of gate circuits 2 are arranged.

When designing the pattern of the semiconductor integrated circuit 1, first, a logic circuit, a RAM, a RO,
M, gate circuits 21 to 2n which form a basic type such as an I / O circuit are extracted, and then a pattern design drawing 3 of each layer is designed for each of the basic type gate circuits 21 to 2n, and an n-type impurity diffusion layer, gate layer to create a pattern 3P ₁ ~3P _m of each layer of bulk wirings (Figure 3).

Thereafter, a layout diagram 4 necessary for arranging the basic type gate circuits 21 to 2n is designed (FIG. 4).

As described above, when designing the pattern of the semiconductor integrated circuit 1, the drawing is divided into a plurality of layers by the CAD method, and the data is stored in a storage device (not shown).

Next, an embodiment of the present invention will be described with reference to a flow chart shown in FIG. 1 by taking a mask for an n-type impurity diffusion pattern constituting the semiconductor integrated circuit 1 as an example.

Reads the design data of a plurality of basic gate circuit n-type impurity diffused pattern 3P ₁₁ ~3P _1n used in 21~2n shown in Figure 4, by shifting process this data, the etching in the semiconductor circuit creating step Correct fat and thin. In addition, logical processing before the shift processing is performed to prevent the pattern from being deformed due to the shift processing.

Data obtained by these logical processes and shift processes is stored in a storage device.

Next, the call the n-type impurity diffusion pattern 3-Way ₁₁ of the first gate circuit 21 of the basic type, after calling address to place the gate circuit 21 from the data of the layout 4, the mask corresponding to the address against an electron beam exposure start position of the substrate 5, performs exposure scanning in accordance with the data of the pattern 3-Way ₁₁ for n-type impurity diffusion of the gate circuit 21 (fifth and sixth view).

In this case, when there are a plurality of blocks in which the gate circuits 21 are arranged, exposure scanning is performed in block units according to the arrangement order.

Above after completion of the exposure scanning of the pattern 3-Way _11, such as, other basic gate circuit similar process on the same substrate 5 for the data of the pattern 3P ₁₂ ~3P _1n for n-type impurity diffusion in 22~2n Is performed for each basic type gate circuit, thereby completing the mask exposure for n-type impurity diffusion.

Note that reference numerals 3P ₂ (3P _{21 to} 3P _2n ) to 3P _m (3P _{m1 to} 3
P _mn ) shows a pattern diagram of a gate layer, a bulk wiring layer, and the like other than the n-type impurity diffusion patterns in the basic type gate circuits 21 to 2n.

On the resist 6 on the mask substrate 5 that has been subjected to the above-described exposure processing, a latent image pattern for the n-type impurity diffusion of the semiconductor circuit 1 is formed. Thereafter, development, etching, and resist removal are sequentially performed. Then, the chromium film 7 formed between the mask substrate 5 and the resist 6 becomes a pattern for n-type impurity diffusion.

The above steps can be used when directly forming a mask, but can also be used when manufacturing a reticle. When a reticle is used, a reduced projection exposure is performed by a photorepeater to produce a mask.

In the above-described embodiment, the design data divided into two levels of the pattern design of the gate circuit 2 and the layout design of the gate circuit 2 has been described. However, as shown in FIG. If there is a required fixed circuit area 10 and a variable circuit area 11 that changes the circuit according to the user's request, design the layout of the gate circuit for each area,
After the exposure scan of the fixed circuit region 10, the mask substrate can be exposed in units of regions, such as by exposing the variable circuit region 11.

In the above-described embodiment, the pattern of the gate circuit 2 is exposed on the substrate in units of the gate circuit, and the pattern over a plurality of gate circuits, for example, a mask for electrode wiring connecting the gate circuits 2 to each other. The present invention cannot be applied to the case of creating a pattern, and it is necessary to go through conventional steps of solid development, logical processing, shift processing, and exposure (No. 8).
Figure).

〔The invention's effect〕

As described above, according to the present invention, when a semiconductor circuit is designed in a plurality of layers, a logic process and a shift process are performed on a pattern formed in a design stage of a basic gate circuit, and then a gate process is performed. Since the pattern of the basic type gate circuit is sequentially exposed in the unit of the gate circuit in the order of the arrangement address of the circuit, it is possible to omit solid development when creating a mask used for bulk wiring, impurity diffusion and the like. At the same time, only the gate circuit of the basic type is subjected to logical processing and shift processing, so that the time for data processing at the time of mask production can be greatly reduced, and the time for semiconductor circuit production can be shortened.

[Brief description of the drawings]

1 is a flowchart showing one embodiment of the present invention, FIG. 2 is a plan view showing an example of a semiconductor circuit, and FIG. 3 is a plan view showing a pattern diagram of a gate circuit formed by designing the semiconductor circuit. FIG. 4, FIG. 4 is a plan view showing a gate circuit layout diagram formed by designing a semiconductor circuit, FIG. 5 is a perspective view of a mask substrate showing a mask exposure state according to the present invention, and FIG. FIG. 7 is a sectional view of a mask substrate after mask exposure, FIG. 7 is a plan view of a mask formed by another embodiment of the present invention, and FIG. 8 is a flowchart showing a conventional method. (Reference Numerals) 1 ...... semiconductor integrated circuit, 2 ...... gate circuit, 21 to 2 n ...... gate circuit, 3 ...... layer pattern design drawing, 3-Way ₁ ...... n-type impurity diffusion pattern, 4 ...... layout 5, a mask substrate; 6, a resist; 7, a chromium film.

Claims (1)

(57) [Claims] In a method of producing an exposure mask for producing a mask based on design data of a semiconductor circuit designed in a plurality of layers, a basic gate circuit (21) designed in one design layer of a circuit pattern design is provided. ~ 2n) logically processing the pattern or /
Data correction means for performing a shift process, and a pattern of the gate circuit (21 to 2n) to which the data correction means has been applied, based on data of a basic gate circuit arrangement address designed in another design hierarchy, on a gate circuit basis. A method for producing an exposure mask, comprising: a gate circuit exposure means for exposing a mask substrate (5).